SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 D D D D D D D D D SN54ABT162601 . . . WD PACKAGE SN74ABT162601 . . . DGG OR DL PACKAGE (TOP VIEW) Members of the Texas Instruments Widebus Family B-Port Outputs Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA description These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors to reduce overshoot and undershoot. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 description (continued) The SN54ABT162601 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT162601 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS LEAB CLKAB A OUTPUT B H X X X Z L H X L L X L H X H H L L X X H B0‡ H L L X X L L L ↑ L L L L ↑ H H L L L L X B0‡ B0§ CLKENAB OEAB X X B0‡ L L L L H X † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 logic diagram (positive logic) OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA A1 1 56 55 2 28 30 29 27 CE 3 1D 54 B1 LE CLK CE 1D LE CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT162601 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT162601 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 recommended operating conditions (see Note 3) SN54ABT162601 VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage SN74ABT162601 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 2 2 0.8 Input voltage 0 0.8 V VCC –32 V A port B port –12 –12 A port 48 64 B port 12 12 High level output current High-level IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 Outputs enabled 10 10 –40 mA mA ns/V µs/V 200 125 V V VCC –24 IOH 0 UNIT 85 °C NOTE 3: All unused inputs of the devices must be held at VCC or GND to ensure proper device operation. Refer to the TI application note, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A port TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOH B port VCC = 4.5 V, VCC = 5 V, 5V VCC = 4 4.5 VOL A port VCC = 4 4.5 5V B port VCC = 4.5 V, MIN TA = 25°C SN54ABT162601 TYP† MAX MIN MAX –1.2 SN74ABT162601 MIN –1.2 –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOH = –1 mA 2* 2 3.35 3.3 3.35 IOH = –1 mA IOH = –3 mA 3.85 3.8 3.85 3.1 3 3.1 IOH = –12 mA IOL = 48 mA 2.6 VCC = 0 to 5.5 V, VI = VCC or GND A or B ports V V 0.55 0.55 0.55* 0.55 0.8 0.8 V 0.8 100 Control inputs UNIT 2.6 IOL = 64 mA IOL = 12 mA Vhys MAX mV ±1 ±1 ±1 VCC = 2.1 V to 5.5 V, VI = VCC or GND ±20 ±20 ±20 IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50** ±50 µA IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50** ±50 µA IOZH‡ VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V 10 10 10 µA IOZL‡ VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V –10 –10 –10 µA Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V ±100 µA 50 µA 5V VCC = 5 5.5 V, 5V VO = 2 2.5 VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high 3 3 3 Outputs low 36 36 36 3 3 3 50 50 50 II ICEX IO§ ICC A port B port A or B ports ±100* Outputs high 50 Control inputs 50 –50 –100 –180 –50 –180 –50 –180 –25 –55 –100 –25 –100 –25 –100 Outputs disabled VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC¶ Ci µA VI = 2.5 V or 0.5 V 3 Cio A or B ports VO = 2.5 V or 0.5 V 9 * On products compliant to MIL-PRF-38535, this parameter does not apply. ** On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA mA µA pF pF 5 SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(see Figure 1) SN54ABT162601 fclock tw Clock frequency Pulse duration th Setup time Hold time MAX 0 150 SN74ABT162601 MIN MAX 0 150 LEAB or LEBA high 2.5 2.5 CLKAB or CLKBA high or low 3.3 3 A before CLKAB↑ or B before CLKBA↑ tsu MIN 4.8 4.3 CLK high 2.5 2.5 CLK low 1.2 1 CLKEN before CLK↑ 2.7 2.7 A after CLKAB↑ or B after CLKBA↑ 0.5 0 2 0.5 0.5 0 A before LEAB↓ or B before LEBA↓ A after LEAB↓ or B after LEBA↓ CLKEN after CLK↑ UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ 6 FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C MIN SN54ABT162601 TYP MAX 1.5 2.8 4 1.5 5.1 1.5 4.8 2 3.7 5.2 2 6.1 2 5.7 1 2.5 3.6 1 4.5 1 4 2 3.3 4.5 2 5.1 2 4.9 2 3.3 4.5 2 5.6 2 5 2 3.6 4.7 2 5.4 2 5 2 3.4 4.8 2 6.1 2 5.6 2 3.8 5.2 2 6.4 2 5.9 1.5 3.1 4.7 1.5 5.4 1.5 5.3 1.5 3.1 4.3 1.5 5.2 1.5 5 1.5 3.3 4.7 1.5 6 1.5 5.5 1.5 3.5 4.8 1.5 5.8 1.5 5.3 2 3.5 4.6 2 5.5 2 5.1 2 3.7 4.7 2 5.8 2 5.4 2 3.8 5.3 1.5 6.6 2 6.1 2 3.6 5.1 2 6.2 2 5.7 150 A B B A LEBA A LEAB B CLKBA A CLKAB B OEBA A OEAB B OEBA A OEAB B POST OFFICE BOX 655303 MIN MAX SN74ABT162601 150 MIN 150 MHz 2 3.6 5.4 1.4 6.6 2 6.2 1.5 3.2 4.7 1.5 5.8 1.5 5.4 2 3.4 4.8 1.4 5.6 2 5.4 1.5 3.2 4.5 1.5 5.7 1.5 5.2 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns ns ns ns ns ns ns ns SN54ABT162601, SN74ABT162601 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS247G – AUGUST 1992 – REVISED JULY 1998 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V Data Input 0V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 3V 1.5 V Input Output Control 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated