SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 D D D D D D Members of the Texas Instruments Widebus+ Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Released as DSCC SMD 5962-9557601NXD D D D D D D Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (–32-mA IOH, 64-mA IOL) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package† 2A11 2A12 2A13 GND 2A14 2A15 2A16 2A17 2A18 2OEBA 2LEBA 2CLKBA VCC 2CLKAB 2LEAB 2OEAB 2B18 2B17 2B16 2B15 2B14 GND 2B13 2B12 2B11 ’ABTH32501 . . . PZ PACKAGE (TOP VIEW) 2A10 2A9 GND 2A8 2A7 2A6 2A5 GND 2A4 2A3 2A2 2A1 VCC 1A1 1A2 1A3 1A4 GND 1A5 1A6 1A7 1A8 GND 1A9 1A10 100 99 98 9796 959493 92 91 90 89 88 87 86 85 84 83 8281 80 79 78 77 76 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 16 59 17 58 18 57 19 56 20 55 21 54 22 53 23 52 24 51 25 2B10 2B9 GND 2B8 2B7 2B6 2B5 GND 2B4 2B3 2B2 2B1 VCC 1B1 1B2 1B3 1B4 GND 1B5 1B6 1B7 1B8 GND 1B9 1B10 1A11 1A12 1A13 GND 1A14 1A15 1A16 1A17 1A18 1OEBA 1LEBA 1CLKBA V CC 1CLKAB 1LEAB 1OEAB 1B18 1B17 1B16 1B15 1B14 GND 1B13 1B12 1B11 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 † The HS package is not production released. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2B12 2B11 2B10 2B9 GND 2B8 2B7 2B6 2B5 GND 2B4 2B3 2B2 2B1 VCC 1B1 1B2 1B3 1B4 GND 1B5 1B6 1B7 1B8 GND 1B9 1B10 1B11 1B12 1B13 1A13 GND 1A14 1A15 1A16 1A17 1A18 1OEBA 1LEBA 1CLKBA VCC 1CLKAB 1LEAB 1OEAB 1B18 1B17 1B16 1B15 1B14 GND 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2A13 2A12 2A11 2A10 2A9 GND 2A8 2A7 2A6 2A5 GND 2A4 2A3 2A2 2A1 VCC 1A1 1A2 1A3 1A4 GND 1A5 1A6 1A7 1A8 GND 1A9 1A10 1A11 1A12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GND 2A14 2A15 2A16 2A17 2A18 2OEBA 2LEABA 2CLKBA VCC 2CLKAB 2LEAB 2OEAB 2B18 2B17 2B16 2B15 2B14 GND 2B13 SN54ABTH32501 . . . HS PACKAGE† (TOP VIEW) † For HS package availability, please contact the factory or your local TI Field Sales Office. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 description These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is active low). When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH32501 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH32501 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0‡ B0§ H L L X † A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 logic diagram (positive logic) 1OEAB 1CLKBA 1LEBA 1OEBA 1CLKAB 1LEAB 1A1 41 37 36 35 39 40 14 CLK 62 LE 1B1 D CLK LE D To 17 Other Channels 2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB 2A1 85 89 90 91 87 86 12 CLK 64 LE D CLK LE D To 17 Other Channels Pin numbers shown are for the PZ package. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B1 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABTH32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. recommended operating conditions (see Note 3) SN54ABTH32501 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABTH32501 MIN 2 2 0.8 Input voltage 0 Low-level output current Outputs enabled VCC –24 V V 0.8 0 UNIT VCC –32 V V mA 48 64 mA 10 10 ns/V µs/V 200 125 –40 85 °C NOTE 3: Unused control pins must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH II = –18 mA IOH = –3 mA VCC = 5 V, IOH = –3 mA IOH = –24 mA –1.2 3 3 A or B ports Control inputs A or B ports A or B ports VI = VCC or GND VI = VCC or GND VCC = 5 5.5 5V V, VI = VCC or GND VCC = 4 4.5 5V VI = 0.8 V VI = 2 V V 2 0.55 0.55 IOL = 64 mA VCC = 0 to 5.5 V, VCC = 2.1 V to 5.5 V, UNIT V 2 0.55 100 Control inputs II(hold) I(h ld) –1.2 2.5 Vhys II MIN 2.5 IOH = –32 mA IOL = 48 mA VCC = 4 4.5 5V SN74ABTH32501 TYP† MAX MIN VCC = 4.5 V, VCC = 4.5 V, VCC = 4 4.5 5V VOL SN54ABTH32501 TYP† MAX TEST CONDITIONS 100 V mV ±1 ±20 ±5 µA ±50 100 100 –100 –100 µA IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE or OE = X ±50 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE or OE = X ±50 ±50 µA Ioff ICEX IO§ VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V Outputs high ±100 µA 50 µA VCC = 5.5 V, VO = 2.5 V Outputs high –180 mA ICC VCC = 5.5 5 5 V, V IO = 0, 0 VI = VCC or GND ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs 50 –50 –100 –180 Outputs low Outputs disabled VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V –50 –100 6 6 90 90 6 6 1 1 3.5 mA mA 3.5 pF Cio A or B ports 11.5 11.5 † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is specified by characterization. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABTH32501 6 fclock Clock frequency tw Pulse duration tsu Setup time th Hold time SN74ABTH32501 MIN MAX MIN MAX 0 150 0 150 LE high 3.5 3.3 CLK high or low 3.5 3.3 A or B before CLK↑ 4.3 3.5 A or B before LE↓ 2.5 1.6 A or B after CLK↑ 0.2 0 A or B after LE↓ 1.8 1.6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH FROM (INPUT) TO (OUTPUT) A or B B or A LEAB or LEBA A or B CLKAB or CLKBA A or B OEAB or OEBA A or B OEAB or OEBA tPLZ † All typical values are at VCC = 5 V, TA = 25°C. A or B tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ POST OFFICE BOX 655303 SN54ABTH32501 TYP† MAX MIN SN74ABTH32501 TYP† MAX UNIT 150 150 MHz MIN 0.5 2.9 5.2 1.3 2.9 4.8 0.5 2.7 5.8 1.4 2.7 5.4 0.7 3.4 5.7 1.6 3.4 5.3 0.7 3.6 5.9 1.9 3.6 5.5 0.5 3.2 5.7 1.5 3.2 5.3 0.7 3.3 5.8 1.7 3.3 5.4 0.5 3.2 6.2 1.2 3.2 5.6 0.5 3.6 6.6 1.5 3.6 6 0.7 3.6 7 1.8 3.6 5.9 0.7 3.5 6.1 1.7 3.5 5.6 • DALLAS, TEXAS 75265 ns ns ns ns ns 7 SN54ABTH32501, SN74ABTH32501 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS229F – JUNE 1992 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated