Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV I2C BUS compatible serial EEPROM BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16 / BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV / The BR24C08, BR24C16 and BR24E16 series are 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗I2C BUS is a registered trademark of Philips. zFeatures 1) 1k x 8 bits serial EEPROM. (BR24C08 / F / FJ / FV) 2k x 8 bits serial EEPROM. (BR24C16 / F / FJ / FV, BR24E16 / F / FJ / FV) 2) Two wire serial interface. (2Byte Address : BR24E16) 3) Operating voltage range : 2.7V∼5.5V 4) Low current consumption Active (at 5V) : 2.0mA (Typ.) Standby (at 5V) : 1.0µA (Typ.) 5) Auto erase and auto complete functions can be used during write operations. 6) Page write function : 16byte 7) DATA security Write protect feature Inhibit to WRITE at low Vcc 8) Noise filters at SCL and SDA pins. 9) Address can be incremented automatically during read operations. 10) Compact packages. 11) Rewriting possible up to 100,000 times. 12) Data can be stored for ten years without corruption. zAbsolute maximum ratings (Ta=25°C) Parameter Symbol Limits VCC −0.3~+6.5 Supply voltage 300(SSOP−B8) Pd Power dissipation Unit V ∗1 450(SOP8, SOP−J8) ∗2 800(DIP8) mW ∗3 Storage temperature range Tstg −65~+125 °C Operating temperature range Topr −40~+85 °C − −0.3~VCC+0.3 V Terminal voltage ∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. zRecommended operating conditions (Ta=25°C) Symbol Limits Unit Power supply voltage Parameter VCC 2.7~5.5 V Input voltage VIN 0~VCC V BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV Memory Ics zBlock diagram BR24C08 / F / FJ / FV A0 1 2 ADDRESS DECODER 10bits SLAVE · WORD ADDRESS REGISTER START A2 3 VCC 8bits 10bits A1 8 8kbits EEPROM ARRAY DATA REGISTER 7 WP STOP 6 CONTROL LOGIC SCL ACK GND 4 VCC LEVEL DETECT HIGH VOLTAGE GEN. 5 SDA 8 VCC Pin name I/O VCC − Power supply Ground (0V) Function GND − A0, A1 − Out of use. Please connect to GND. A2 I Slave address set SCL I Serial clock input SDA I/O WP I Slave and word address, serial data input, serial data output ∗ Wite protect pin ∗An open drain output requires a pull-up resistor. BR24C16 / F / FJ / FV A0 1 16kbits EEPROM ARRAY 8bits 11bits A1 2 ADDRESS DECODER 11bits SLAVE · WORD ADDRESS REGISTER START A2 3 DATA REGISTER 7 WP STOP CONTROL LOGIC 6 SCL 5 SDA 8 VCC Pin name I/O VCC − Power supply GND − Ground (0V) A0, A1, A2 I Out of use. Please connect to GND. SCL I Serial clock input SDA I/O WP I ACK GND 4 VCC LEVEL DETECT HIGH VOLTAGE GEN. Function Slave and word address, serial data input, serial data output ∗ Wite protect pin ∗An open drain output requires a pull-up resistor. BR24E16 / F / FJ / FV A0 1 16kbits EEPROM ARRAY 8bits 11bits A1 2 ADDRESS DECODER 11bits SLAVE · WORD ADDRESS REGISTER START A2 3 DATA REGISTER 7 WP STOP 6 CONTROL LOGIC SCL Pin name I/O VCC − Power supply GND − Ground (0V) A0, A1, A2 I Slave address set SCL I Serial clock input SDA I/O ACK GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA Function WP I Slave and word address, serial data input, serial data output Wite protect pin ∗An open drain output requires a pull-up resistor. ∗ Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV zElectrical characteristics DC characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Parameter Symbol Min. Typ. Max. Unit Conditions VIH 0.7VCC − − V − "LOW" input voltage VIL − − 0.3VCC V "LOW" output voltage VOL − − 0.4 V IOL=3.0mA(SDA) "HIGH" input voltage − Input leakage current ILI −1 − 1 µA VIN=0V~VCC Output leakage current ILO −1 − 1 µA VOUT=0V~VCC operating current ICC − − 3.0 mA VCC=5.5V, fSCL=400kHz Standby current ISB − − 3.0 µA VCC=5.5V, SDA SCL=VCC A0, A1, A2=GND, WP=GND This product is not designed for protection against radioactive rays. Operating timing characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Vcc=5V±10% Parameter Symbol Vcc=3V±10% Min. Typ. Max. Min. Typ. Max. Unit SCL frequency fSCL − − 400 − − 100 kHz Dataclock "HIGH" time tHIGH 0.6 − − 4.0 − − µs Dataclock "LOW" time tLOW 1.2 − − 4.7 − − µs SDA / SCL rise time tR − − 0.3 − − 1.0 µs SDA / SCL fall time tF − − 0.3 − − 0.3 µs Start condition hold time tHD : STA 0.6 − − 4.0 − − µs Start condition setup time tSU : STA 0.6 − − 4.7 − − µs Input data hold time tHD : DAT 0 − − 0 − − ns Input data setup time tSU : DAT 100 − − 250 − − ns tPD 0.1 − 0.9 0.2 − 3.5 µs Output data delay time tDH 0.1 − − 0.2 − − µs tSU : STO 0.6 − − 4.7 − − µs Bus open time before start or transfer tBUF 1.2 − − 4.7 − − µs Internal write cycle time tWR − − 10 − − 10 ms tI − − 0.05 − − 0.1 µs Output data hold time Stop condition setup time Noise erase valid time (SDA/SCL pins) Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV zTiming charts tR tF tHIGH SCL tHD : STA tSU : DAT tLOW tHD : DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU : STA tHD : STA tSU : STO SDA START BIT STOP BIT Data is read on the rising edge of SCL. Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing SCL SDA D0 ACK Write data (n) tWR STOP CONDITION START CONDITION Fig.2 Write cycle timing zCircuit operation (1) Start condition (recognition of start bit) Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be executed unless this condition is satisfied. (See Fig.1 for the synchronized data input / output timing.) (2) Stop condition (recognition of stop bit) To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed. (See Fig.1 for the synchronized data input / output timing.) (3) Precautions concerning write commands In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (4) Device addressing BR24C08 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 1bit of the slave address (A2 … device address) are used to select the device. This IC can address up to two devices on the same bus. 4) The next 2bits (P1, P0 … page select) are used by the master to select four 256 word page of memory. P1, P0 set to ‘0’ ‘0’ $ $ $ $ $ $ $ 1 page (000 ~0FF) P1, P0 set to ‘0’ ‘1’ $ $ $ $ $ $ $ 2 page (100 ~1FF) P1, P0 set to ‘1’ ‘0’ $ $ $ $ $ $ $ 3 page (200 ~2FF) P1, P0 set to ‘1’ ‘1’ $ $ $ $ $ $ $ 4 page (300 ~3FF) 5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 P1 P0 R/W BR24C16 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 3bits (P2, P1, P0 … page select) are used by the master to select four 256 word page of memory. P2, P1, P0 set to ‘0’ ‘0’ ‘0’$ $ $ $ $ $ $ 1 page (000 ~0FF) P2, P1, P0 set to ‘0’ ‘0’ ‘1’$ $ $ $ $ $ $ 2 page (100 ~1FF) : : P2, P1, P0 set to ‘1’ ‘1’ ‘1’$ $ $ $ $ $ $ 8 page (700 ~7FF) 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 P2 P1 P0 R/W BR24E16 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 3bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC can address up to eight devices on the same bus. 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 A1 A0 R/W Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (5) Write protect (WP) When WP pin set to VCC (High level), write protect is set by all address. When WP pin set to GND (Low level), enable to write to all address. Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected. (6) ACK signal The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output (µ-COM when a write or read command of the slave address input ; this IC when reading data). For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address input, µ-COM when a read command data output). The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8 bits). When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each 8 bits of data (word address and write data). When data is being read from the IC, 8bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Fig.3 for acknowledge signal (ACK signal) response.) Start condition (start bit) SCL (from µ-COM) 1 8 9 SDA (µ−COM output data) SDA (IC output data) Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) Acknowledge signal (ACK signal) BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV Memory Ics (7) Byte write BR24C08 / F / FJ / FV S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 WORD ADDRESS WA 7 0 A2 P1 P0 S T O P DATA WA 0 R A / C W K D7 D0 A C K A C K WP Fig.4 BR24C16 / F / FJ / FV S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 WORD ADDRESS WA 7 0 P2 P1 P0 WA 0 R A / C W K S T O P DATA D7 D0 A C K A C K WP Fig.5 BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS ∗ ∗ ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 R A / C W K 2nd WORD ADDRESS WA 10 WA 0 A C K S T O P DATA D7 A C K WP Fig.6 $ Data is written to the address designated by the word address (n address). $ After 8 bits of data are input, the data is written to the memory cell by issuing the stop bit. D0 A C K BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV Memory Ics (8) Page write BR24C08 / F / FJ / FV S T A R T SDA LINE W R I T E SLAVE ADDRESS 1 0 1 WORD ADDRESS DATA WA 7 0 P2 P1 P0 S T O P WA 0 R A / C W K D7 D0 A C K A C K WP Fig.7 BR24C16 / F / FJ / FV S T A R T SDA LINE W R I T E SLAVE ADDRESS DATA(n) WORD ADDRESS(n) WA 7 1 0 1 0 P2 P1 P0 WA 0 R A / C W K D7 S T O P DATA(n+15) D0 D0 A C K A C K A C K WP Fig.8 BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) ∗ ∗ ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 R A / C W K 2nd WORD ADDRESS(n) WA 10 WA 0 D7 A C K A C K S T O P DATA(n+15) DATA(n) D0 D0 A C K A C K WP Fig.9 $ A 16 byte write is possible using this command. $ The page write command arbitrarily sets the upper 4 bits (WA7 to WA4) of the word address. The lower 4 bits (WA3 and WA0) can write up to 16 bytes of data with the address being incremented internally. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (9) Current read BR24C08 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS 1 0 1 R E A D 0 A2 P1 P0 S T O P DATA D7 D0 R A / C W K A C K Fig.10 BR24C16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS 1 0 1 R E A D 0 P2 P1 P0 S T O P DATA D7 D0 R A / C W K A C K Fig.11 BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS 1 0 1 R E A D 0 A2 A1 A0 S T O P DATA D7 R A / C W K D0 A C K Fig.12 $ In case the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the next word address (n+1). If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current read outputs the data of the word address (n). If the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides s single byte of data. At this point, this IC discontinues transmission. $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) $ This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (10) Random read BR24C08 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS W R I T E S T A R T WORD ADDRESS(n) WA 7 1 0 1 0 A2 P1 P0 WA 0 R A / C W K SLAVE ADDRESS R E A D 1 0 1 0 A2 P1P0 A C K S T O P DATA(n) D7 D0 A C K R A / C W K Fig.13 BR24C16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS W R I T E S T A R T WORD ADDRESS(n) WA 7 1 0 1 0 P2 P1 P0 WA 0 R A / C W K SLAVE ADDRESS R E A D 1 0 1 0 P2 P1P0 A C K S T O P DATA(n) D7 D0 A C K R A / C W K Fig.14 BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) ∗ ∗ ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 R A / C W K S T A R T 2nd WORD ADDRESS(n) WA 10 WA 0 1 0 1 0 A2 A1A0 A C K A C K SLAVE ADDRESS R E A D DATA(n) D7 R A / C W K S T O P D0 A C K Fig.15 $ This command can read the designated word address data. $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) $ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (11) Sequential read BR24C08 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 P1 P0 DATA(n) D7 S T O P DATA(n+x) D0 R A / C W K D7 A C K D0 A C K A C K Fig.16 BR24C16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 P2 P1 P0 DATA(n) D7 S T O P DATA(n+x) D0 R A / C W K D7 A C K D0 A C K A C K Fig.17 BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D 1 0 1 0 A2 A1 A0 DATA(n) D7 R A / C W K S T O P DATA(n+x) D0 D7 A C K A C K D0 A C K Fig.18 $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words can be read] $ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. $ Sequential reading can also be done with a random read. BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV Memory Ics zExternal dimensions (Units : mm) BR24C08F BR24C16F BR24E16F 9.3 ± 0.3 5 5.0 ± 0.2 8 5 7.62 1 4 0.11 1.5 ± 0.1 1.27 0.4 ± 0.1 0.15 0°~15° SOP8 BR24C08FV BR24C16FV BR24E16FV 3.0 ± 0.2 0.175 6.4 ± 0.3 0.2 ± 0.1 1 2 3 4 0.45Min. 1.27 0.42 ± 0.1 8 5 1 4 4.4 ± 0.2 3.9 ± 0.2 8 7 6 5 0.22 ± 0.1 (0.52) 0.15 ± 0.1 4.9 ± 0.2 0.1 1.15 ± 0.1 0.5 ± 0.1 2.54 BR24C08FJ BR24C16FJ BR24E16FJ 6.0 ± 0.3 0.3Min. 0.3 ± 0.1 DIP8 1.375 ± 0.1 0.15 ± 0.1 4 0.51Min. 3.2 ± 0.2 3.4 ± 0.3 1 6.2 ± 0.3 6.5 ± 0.3 8 4.4 ± 0.2 BR24C08 BR24C16 BR24E16 0.3Min. 0.65 0.1 0.1 SOP-J8 SSOP-B8