BSI Very Low Power/Voltage CMOS SRAM 128K X 8 bit FEATURES • Wide Vcc operation voltage : 2.4V ~ 5.5V • Very low power consumption : Vcc = 3.0V C-grade : 17mA (@55ns) operating current I- grade : 18mA (@55ns) operating current C-grade : 14mA (@70ns) operating current I- grade : 15mA (@70ns) operating current 0.1uA (Typ.) CMOS standby current Vcc = 5.0V C-grade : 46mA (55ns) operating current I- grade : 47mA (55ns) operating current C-grade : 38mA (70ns) operating current I- grade : 39mA (70ns) operating current 0.6uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE BS62LV1027SC BS62LV1027TC BS62LV1027STC BS62LV1027PC BS62LV1027JC BS62LV1027DC BS62LV1027SI BS62LV1027TI BS62LV1027STI BS62LV1027PI BS62LV1027JI BS62LV1027DI Vcc RANGE SPEED (ns) POWER DISSIPATION Operating STANDBY (ICCSB1 , Max) 55ns : 3.0~5.5V 70ns : 2.7~5.5V Vcc=5.0V Vcc=3.0V PKG TYPE (ICC, Max) Vcc=3V Vcc=5V 70ns 70ns 55/70 8.0uA 1.3uA 14mA 38mA O O 2.4V ~ 5.5V 55/70 20uA 2.5uA 15mA 39mA • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 The BS62LV1027 is a high performance, very low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.1uA at 3V/25oC and maximum access time of 55ns at 3V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV1027 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1027 is available in DICE form , JEDEC standard 32 pin 450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4 mm STSOP and 8mmx20mm TSOP. 2.4V ~ 5.5V 32 31 30 29 28 27 BS62LV1027SC 26 BS62LV1027SI 25 BS62LV1027PC 24 BS62LV1027PI 23 BS62LV1027JC 22 BS62LV1027JI 21 20 19 18 17 • A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 DESCRIPTION O -40 C to +85 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 • Easy expansion with CE2, CE1, and OE options • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V O +0 C to +70 C BS62LV1027TC BS62LV1027STC BS62LV1027TI BS62LV1027STI SOP-32 TSOP-32 STSOP-32 PDIP-32 SOJ-32 DICE SOP-32 TSOP-32 STSOP-32 PDIP-32 SOJ-32 DICE BLOCK DIAGRAM PIN CONFIGURATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND BS62LV1027 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A6 A7 A12 A14 A16 A15 A13 A8 A9 A11 Address Input Buffer 20 Row 1024 Memory Array 1024 x 1024 Decoder 1024 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 CE2 CE1 WE OE Vdd Gnd 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 128 Column Decoder 14 Control Address Input Buffer A5 A4 A3 A2 A1 A0 A10 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS62LV1027 1 Revision 2.1 Jan. 2004 BSI BS62LV1027 PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address inputs select one of the 131,072 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE MODE WE CE1 CE2 OE Not selected (Power Down) X H X X X X L X Output Disabled H L H Read H L H Write L L H PARAMETER I CCSB, I CCSB1 H High Z I CC L D OUT I CC X D IN I CC OPERATING RANGE RATING UNITS -0.5 to Vcc+0.5 V V TERM Terminal Voltage with Respect to GND T BIAS Temperature Under Bias -40 to +85 O T STG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W I OUT DC Output Current 20 mA C RANGE AMBIENT TEMPERATURE Vcc Commercial 0 O C to +70 O C 2.4V ~ 5.5V Industrial -40 O C to +85 O C 2.4V ~ 5.5V C 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. R0201-BS62LV1027 Vcc CURRENT High Z ABSOLUTE MAXIMUM RATINGS(1) SYMBOL I/O OPERATION 2 CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not 100% tested. Revision 2.1 Jan. 2004 BSI BS62LV1027 DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) PARAMETER NAME VIL VIH IIL PARAMETER MIN. TYP. (1) MAX. TEST CONDITIONS Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V UNITS -0.5 -- 0.8 V 2.0 2.2 -- Vcc+0.3 V Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA ILO Output Leakage Current Vcc = Max, CE1= VIH, CE2= VIL, or OE = VIH, VI/O = 0V to Vcc -- -- 1 uA VOL Output Low Voltage Vcc = Max, IOL = 2.0mA -- -- 0.4 V VOH Output High Voltage Vcc = Min, IOH = -1.0mA 2.4 -- -- V ICC Operating Power Supply Current CE1 = VIL, or CE2 = VIH, IDQ = 0mA, F = Fmax(3) ICCSB Standby Current-TTL CE1 = VIH, or CE2 = VIL, IDQ = 0mA Vcc=3.0V ICCSB1(4) Standby Current-CMOS CE1≧Vcc-0.2V or CE2≦0.2V, VIN≧Vcc-0.2V or VIN≦0.2V Vcc=3.0V ------- ----0.1 0.6 15 39 0.5 1.0 2.5 20 (5) Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V 70ns Vcc=3.0V Vcc=5.0V Vcc=5.0V Vcc=5.0V mA mA uA 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . 4. IccSB1_Max. is 1.3uA/8.0uA at Vcc=3.0V/5.0V and TA=70oC. 5. Icc_Max. is 18mA(@3V)/ 47mA(@5V) under 55ns operation. DATA RETENTION CHARACTERISTICS ( TA = -40oC to + 85oC ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS 1.5 -- -- V -- 0.05 0.3 uA 0 -- -- ns TRC (2) -- -- ns VDR Vcc for Data Retention CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V ICCDR(3) Data Retention Current CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V tCDR Chip Deselect to Data Retention Time tR See Retention Waveform Operation Recovery Time 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR_MAX. is 0.2uA at TA=70OC. LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR ≥ 1.5V Vcc CE1 Vcc tR t CDR CE1 ≥ Vcc - 0.2V VIH LOW VCC DATA RETENTION WAVEFORM (2) VIH ( CE2 Controlled ) Data Retention Mode Vcc VDR ≧ 1.5V Vcc CE2 R0201-BS62LV1027 VIL Vcc tR t CDR CE2 ≦ 0.2V 3 VIL Revision 2.1 Jan. 2004 BSI BS62LV1027 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times WAVEFORM INPUTS OUTPUTS 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level 0.5Vcc MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L Output Load CL = 30pF+1TTL CL = 100pF+1TTL MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME t AVAX t AVQV t E1LQV t E2HOV t GLQV t E1LQX t E2HOX t GLQX t E1HQZ t E2HQZ t GHQZ t RC t AA t ACS1 t ACS2 t OE t CLZ1 t CLZ2 t OLZ t CHZ1 t CHZ2 t OHZ t AXOX t OH R0201-BS62LV1027 CYCLE TIME : 55ns (Vcc = 3.0~5.5V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 70ns (Vcc = 2.7~5.5V) MIN. TYP. MAX. UNIT Read Cycle Time 55 -- -- 70 -- -- ns Address Access Time -- -- 55 -- -- 70 ns Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns -- -- 30 -- -- 40 ns Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns 10 -- -- 10 -- -- ns Output Enable to Output Valid Output Enable to Output in Low Z Chip Deselect to Output in High Z (CE1) -- -- 35 -- -- 40 ns Chip Deselect to Output in High Z (CE2) -- -- 35 -- -- 40 ns Output Disable to Output in High Z -- -- 30 -- -- 35 ns Data Hold from Address Change 10 -- -- 10 -- -- ns 4 Revision 2.1 Jan. 2004 BSI BS62LV1027 SWITCHING WAVEFORMS (READ CYCLE) (1,2,4) READ CYCLE1 t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE1 CE2 t t ACS1 t ACS2 t (5) (5) CHZ1, t CHZ2 CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t t CE1 t CE2 t OH OLZ t ACS1 (5) CLZ1 t t OE t OHZ (5) (1,5) t CHZ1 ACS2 t (5) (2,5) CHZ2 CLZ2 D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. R0201-BS62LV1027 5 Revision 2.1 Jan. 2004 BSI BS62LV1027 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME CYCLE TIME : 70ns (Vcc = 2.7~5.5V) MIN. TYP. MAX. CYCLE TIME : 55ns (Vcc = 3.0~5.5V) MIN. TYP. MAX. DESCRIPTION UNIT t AVAX t WC Write Cycle Time 55 -- -- 70 -- -- ns t E1LWH t CW Chip Select to End of Write 55 -- -- 70 -- -- ns t AVWL t AS Address Set up Time 0 -- -- 0 -- -- ns t AVWH t AW Address Valid to End of Write 55 -- -- 70 -- -- ns t WLWH t WP Write Pulse Width 35 -- -- 50 -- -- ns t WHAX t WR1 Write Recovery Time (CE1 , WE) 0 -- -- 0 -- -- ns t E2LAX t WR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns t WLOZ t WHZ Write to Output in High Z -- -- 25 -- -- 30 ns t DVWH t DW Data to Write Time Overlap 25 -- -- 30 -- -- ns t WHDX t DH Data Hold from Write Time 0 -- -- 0 -- -- ns t GHOZ t OHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns t WHQX t OW End of Write to Output Active 5 -- -- 5 -- -- ns SWITCHING WAVEFORMS (WRITE CYCLE) t WC WRITE CYCLE1 (1) ADDRESS t (3) WR1 OE (11) t CW (5) CE1 (5) CE2 t CW t WE t WR2 AW t t AS (11) (3) WP (2) (4,10) t OHZ D OUT t DH t DW D IN R0201-BS62LV1027 6 Revision 2.1 Jan. 2004 BSI BS62LV1027 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t (5) CW CE1 CE2 (5) (11) t t CW AW t WR2 t WP (3) (2) WE t AS (4,10) t WHZ D OUT t OW t DH (7) (8) t DW (8,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV1027 7 Revision 2.1 Jan. 2004 BSI BS62LV1027 ORDERING INFORMATION BS62LV1027 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC PACKAGE J: SOJ S: SOP P: PDIP T: TSOP (8mm x 20mm) ST: Small TSOP (8mm x 13.4mm) D: DICE Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32 R0201-BS62LV1027 8 Revision 2.1 Jan. 2004 BSI BS62LV1027 PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV1027 9 Revision 2.1 Jan. 2004 BSI BS62LV1027 PACKAGE DIMENSIONS (continued) PDIP - 32 SOJ - 32 R0201-BS62LV1027 10 Revision 2.1 Jan. 2004