[ /Title (CA31 46, CA314 6A, CA318 3, CA318 3A) /Subject (HighVoltage Transistor Arrays ) /Autho r () /Keywords (Intersil Corporation, five, transistor array, low cost NPN, 40V, 50ma 75ma, mhz ft, high volt- CA3146, CA3146A, CA3183, CA3183A TM Data Sheet April 2000 File Number 532.5 High-Voltage Transistor Arrays Features The CA3146A, CA3146, CA3183A, and CA3183 are general purpose high voltage silicon NPN transistor arrays on a common monolithic substrate. • Matched General Purpose Transistors - VBE Match . . . . . . . . . . . . . . . . . . . . . . . . ±5mV (Max) Types CA3146A and CA3146 consist of five transistors with two of the transistors connected to form a differentially connected pair. These types are recommended for low power applications in the DC through VHF range. (CA3146A and CA3146 are high voltage versions of the popular predecessor type CA3046.) • Operation from DC to 120MHz (CA3146, CA3146A) • Low Noise Figure . . . . . . . . . . 3.2dB (CA3146, CA3146A) • High IC . . . . . . . . . . . . 75mA (Max) (CA3183, CA3183A) Applications Types CA3183A and CA3183 consist of five high current transistors with independent connections for each transistor. In addition two of these transistors (Q1 and Q2) are matched at low current (i.e., 1mA) for applications where offset parameters are of special importance. A special substrate terminal is also included for greater flexibility in circuit design. (CA3183A and CA3183 are high voltage versions of the popular predecessor type CA3083.) • General Use in Signal Processing Systems in DC through VHF Range The types with an “A” suffix are premium versions of their non-“A” counterparts and feature tighter control of breakdown voltages making them more suitable for higher voltage applications. Pinouts • Custom Designed Differential Amplifiers • Temperature Compensated Amplifiers • Lamp and Relay Drivers (CA3183, CA3183A) • Thyristor Firing (CA3183, CA3183A) CA3146, CA3146A (PDIP, SOIC) TOP VIEW 1 For detailed application information, see companion Application Note AN5296 “Application of the CA3018 Integrated Circuit Transistor Array.” Q1 2 DIFF. PAIR Ordering Information PART NUMBER (BRAND) 14 Q5 13 SUBSTRATE 3 12 Q2 4 11 Q4 TEMP. RANGE (oC) PACKAGE PKG. NO. CA3146AE -40 to 85 14 Ld PDIP E14.3 CA3146AM (3146A) -40 to 85 14 Ld SOIC M14.15 CA3146E -40 to 85 14 Ld PDIP E14.3 CA3146M (3146) -40 to 85 14 Ld SOIC M14.15 CA3146M96 (3146) -40 to 85 14 Ld SOIC Tape and Reel M14.15 CA3183AE -40 to 85 16 Ld PDIP E16.3 CA3183AM96 (3183A) -40 to 85 16 Ld SOIC Tape and Reel M16.15 CA3183E -40 to 85 16 Ld PDIP E16.3 CA3183M (3183) -40 to 85 16 Ld SOIC M16.15 CA3183M96 (3183) -40 to 85 16 Ld SOIC Tape and Reel 10 6 9 7 16 1 2 15 Q1 Q2 3 14 Q5 4 M16.15 8 Q3 CA3183, CA3183A (PDIP, SOIC) TOP VIEW 13 SUBSTRATE 5 12 6 11 Q4 7 10 Q3 8 1 5 9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 CA3146, CA3146A, CA3183, CA3183A Absolute Maximum Ratings Thermal Information Collector-to-Emitter Voltage (VCEO) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Collector-to-Base Voltage (VCBO) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Collector-to-Substrate Voltage (VCIO, Note 1) CA3146A, CA3183A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Emitter to Base Voltage (VEBO) all types. . . . . . . . . . . . . . . . . . . . . 5V Collector Current CA3146A, CA3146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA Base Current (IB) - CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . 20mA Thermal Resistance (Typical, Note 2) θJA (oC/W) 14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 200 16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 95 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Power Dissipation (Any One Transistor, Note 3) CA3146A, CA3146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW CA3183A, CA3183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range (all types) . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any collector voltage in order to maintain isolation between transistors, and to provide for normal transistor action. To avoid undesired coupling between transistors, the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal resistances to calculate the junction temperature. Electrical Specifications CA3146 Series TEST CONDITIONS PARAMETER TA = 25oC SYMBOL TYPICAL PERF. CURVE FIG. NO. CA3146 CA3146A MN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH TRANSISTOR Collector-to-Base Breakdown Voltage V(BR)CBO IC = 10µA, IE = 0 - 40 72 - 50 72 - V Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 - 30 56 - 40 56 - V Collector-to-Substrate Breakdown Voltage V(BR)CIO ICI = 10µA, IB = 0, IE = 0 - 40 72 - 50 72 - V Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 10µA, IC = 0 - 5 7 - 5 7 - V Collector-Cutoff Current ICEO VCE = 10V, IB = 0 1 - See Curve 5 - See Curve 5 µA Collector-Cutoff Current ICBO VCB = 10V, IE = 0 2 - 0.002 100 - 0.002 100 nA DC Forward-Current Transfer Ratio hFE VCE = 5V, IC = 10mA 3 - 85 - - 85 - - VCE = 5V, IC = 1mA 3 30 100 - 30 100 - - VCE = 5V, IC = 10µA 3 - 90 - - 90 - - Base-to-Emitter Voltage Collector-to-Emitter Saturation Voltage VBE VCE = 3V, IC = 1mA 4 0.63 0.73 0.83 0.63 0.73 0.83 V VCE SAT IC = 10mA, IB = 1mA 5 - 0.33 - - 0.33 - V DC CHARACTERISTICS FOR TRANSISTORS Q1 AND Q2 (As A Differential Amplifier) Magnitude of Input Offset Voltage |VBE1 - VBE2| Magnitude of Base-to-Emitter Temperature Coefficient 2 |VIO| VCE = 5V, IE = 1mA 6, 7 - 0.48 5 - 0.48 5 mV ∆V BE ---------------∆T VCE = 5V, IE = 1mA - - 1.9 - - 1.9 - mV/oC CA3146, CA3146A, CA3183, CA3183A Electrical Specifications CA3146 Series (Continued) TEST CONDITIONS PARAMETER TA = 25oC SYMBOL TYPICAL PERF. CURVE FIG. NO. CA3146 CA3146A MN TYP MAX MIN TYP MAX UNITS - - 1.1 - - 1.1 - µV/oC Magnitude of VIO (VBE1 - VBE2) Temperature Coefficient ∆V IO -------------∆T VCE = 5V, IC1 = IC2 = 1mA Magnitude of Input Offset Current |IIO1 - IIO2| (CA3146AE and CA3146E Only) IIO VCE = 5V, IC1 = IC2 = 1mA 8 - 0.3 2 - 0.3 2 µA NF f = 1kHz, VCE = 5V, IC = 100µA, Source Resistance = 1kΩ 10 - 3.25 - - 3.25 - dB Forward-Current Transfer Ratio hFE f = 1kHz, VCE = 5V, IC = 1mA 12 - 100 - - 100 - - Short-Circuit Input Impedance hIE f = 1kHz, VCE = 5V, IC = 1mA 12 - 3.5 - - 2.7 - kΩ Open-Circuit Output Impedance hOE f = 1kHz, VCE = 5V, IC = 1mA 12 - 15.6 - - 15.6 - µS Open-Circuit Reverse Voltage Transfer Ratio hRE f = 1kHz, VCE = 5V, IC = 1mA 12 - 1.8 x 10-4 - - 1.8 x 10-4 - - Forward Transfer Admittance YFE f = 1MHz, VCE = 5V, IC = 1 mA 13 - 31j1.5 - - 31-j1.5 - mS Input Admittance YIE f = 1MHz, VCE = 5V, IC = 1 mA 14 - 0.3 + j0.04 - - 0.35 + j0.04 - mS Output Admittance YOE f = 1MHz, VCE = 5V, IC = 1 mA 15 - 0.001 + j0.03 - - 0.001 + j0.03 - mS Reverse Transfer Admittance YRE f = 1MHz, VCE = 5V, IC = 1 mA 16 Gain-Bandwidth Product fT VCE = 5V, IC = 3mA 17 300 500 - 300 500 - MHz DYNAMIC CHARACTERISTICS Low Frequency Noise Figure Low-Frequency, Small-Signal Equivalent-Circuit Characteristics: Admittance Characteristics: See Curve See Curve mS Emitter-to-Base Capacitance CEB VEB = 5V, IE = 0 18 - 0.70 - - 0.70 - pF Collector-to-Base Capacitance CCB VCB = 5V, IC = 0 18 - 0.37 - - 0.37 - pF Collector-to-Substrate Capacitance CCl VCl = 5V, IC = 0 18 - 2.2 - - 2.2 - pF Electrical Specifications CA3183 Series TEST CONDITIONS PARAMETER SYMBOL TA = 25oC TYPICAL PERF. CURVE FIG. NO. CA3183 CA3183A MIN TYP MAX MIN TYP MAX UNITS DC CHARACTERISTICS FOR EACH TRANSISTOR Collector-to-Base Breakdown Voltage V(BR)CBO IC = 100µA, IE = 0 - 40 - - 50 - - V Collector-to-Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 - 30 - - 40 - - V Collector-to-Substrate Breakdown Voltage V(BR)ClO ICI = 100µA, IB = 0, IE = 0 - 40 - - 50 - - V Emitter-to-Base Breakdown Voltage V(BR)EBO IE = 500µA, IC = 0 - 5 - - 5 - - V ICEO VCE = 10V, IB = 0 19 - - 10 - - 10 µA Collector-Cutoff Current 3 CA3146, CA3146A, CA3183, CA3183A Electrical Specifications CA3183 Series (Continued) TEST CONDITIONS PARAMETER TA = 25oC SYMBOL TYPICAL PERF. CURVE FIG. NO. CA3183 CA3183A MIN TYP MAX MIN TYP MAX UNITS 20 - - 1 - - 1 µA 21, 22 40 - - 40 - - - Collector-Cutoff Current ICBO VCB = 10V, IE = 0 DC Forward-Current Transfer Ratio hFE VCE = 3V, IC = 10mA VCE = 5V, IC = 50mA - 40 - - 40 - - - Base-to-Emitter Voltage VBE VCE = 3V, IC = 10mA 23 0.65 0.75 0.85 0.65 0.75 0.85 V VCE SAT (Note 3) IC = 50mA, IB = 5mA 24 - 1.7 3.0 - 1.7 3.0 V Collector-to-Emitter Saturation Voltage FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER) Absolute Input Offset Voltage |VIO| VCE = 3V, IC = 1mA 25 - 0.47 5 - 0.47 5 mV Absolute Input Offset Current |IIO| VCE = 3V, IC = 1mA 26 - 0.78 2.5 - 0.78 2.5 µA Typical Performance Curves DC Characteristics - CA3146 Series 102 IB = 0 COLLECTOR CUTOFF CURRENT (nA) COLLECTOR CUTOFF CURRENT (nA) 103 102 VCE = 10V 10 VCE = 5V 1 10-1 10-2 10-3 0 25 50 75 100 IE = 0 10 VCB = 15 1 10-1 VCB = 10 10-2 VCB = 5 10-3 10-4 125 0 25 TEMPERATURE (oC) VCE = 5V 160 125 VCE = 5V TA = 125oC 140 120 100 25oC 80 60 -55oC 40 20 0.01 100 FIGURE 2. ICBO vs TEMPERATURE FOR ANY TRANSISTOR BASE TO EMITTER VOLTAGE (V) DC FORWARD CURRENT TRANSFER RATIO FIGURE 1. ICEO vs TEMPERATURE FOR ANY TRANSISTOR 50 75 TEMPERATURE (oC) 0.1 1 COLLECTOR CURRENT (mA) FIGURE 3. hFE vs IC FOR ANY TRANSISTOR 4 10 0.9 IE = 3mA 0.8 0.7 0.6 IE = 1mA 0.5 0.4 -75 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) FIGURE 4. VBE vs TEMPERATURE FOR ANY TRANSISTOR CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves DC Characteristics - CA3146 Series (Continued) 5 TA = 25oC VCE = 5V IE = 10mA 4 OFFSET VOLTAGE (mV) COLLECTOR TO EMITTER SATURATION VOLTAGE (V) 1.50 1.25 1.0 hFE = 10 0.75 0.50 0.25 3 2 IE = 1mA 0.75 0.50 IE = 0.1mA 0.25 0 10 20 30 0 -75 40 -50 -25 0 0.7 3 0.6 2 0.5 1 |VBE1 - VBE2| 0 0.1 1.0 10 INPUT OFFSET CURRENT (µA) BASE TO EMITTER VOLTAGE (V) VCE = 5V TA = 25oC 0.4 0.01 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 8. IIO vs IC FOR Q1 AND Q2 Dynamic Characteristics (For Any Transistor) - CA3146 Series 20 NOISE FIGURE (dB) NOISE FIGURE (dB) 125 0.1 0.01 0.01 10 VCE = 5V RS = 500Ω TA = 25oC 15 100 1.0 FIGURE 7. VBE AND VIO vs IE FOR Q1 AND Q2 20 75 VCE = 5V TA = 25oC EMITTER CURRENT (mA) Typical Performance Curves 50 FIGURE 6. VIO vs TEMPERATURE FOR Q1 AND Q2 INPUT OFFSET VOLTAGE Q1 AND Q2 (mV) FIGURE 5. VCE SAT vs IC FOR ANY TRANSISTOR 0.8 25 TEMPERATURE (oC) COLLECTOR CURRENT (mA) f = 0.1kHz f = 1kHz 10 f = 10kHz VCE = 5V RS = 1000Ω TA = 25oC f = 0.1kHz 15 f = 1kHz 10 f = 10kHz 5 5 0 0.01 0 0.1 COLLECTOR CURRENT (mA) FIGURE 9. NF vs IC AT RS = 500Ω 5 1.0 0.01 0.1 COLLECTOR CURRENT (mA) FIGURE 10. NF vs IC AT RS = 1kΩ 1.0 CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued) 30 100 NOISE FIGURE (dB) 25 20 NORMALIZED h PARAMETERS VCE = 5V RS = 10000Ω TA = 25oC f = 0.1kHz 15 f = 1kHz 10 f = 10kHz 5 VCE = 5V f = 1kHz TA = 25oC 10 hFE 1.0 hRE 0.1 1.0 0.1 0.01 0.1 COLLECTOR CURRENT (mA) 6 INPUT CONDUCTANCE (gIE) OR SUSCEPTANCE (bIE) (mS) 30 gFE 20 10 0 bFE -10 10 FIGURE 12. hFE, hIE, hOE, hRE vs IC COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA 40 1.0 COLLECTOR CURRENT (mA) FIGURE 11. NF vs IC AT RS = 10kΩ FORWARD TRANSFER CONDUCTANCE (gFE) OR SUSCEPTANCE (bFE) (mS) AT 1mA hIE 0 0.01 COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA 5 4 bIE 3 2 1 gIE -20 0.1 10 1.0 0 100 0.1 COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 3V, IC = 1mA 5 bOE 4 3 2 1 gOE 0 0.1 1.0 10 FREQUENCY (MHz) FIGURE 15. FIGURE 15. yOE vs FREQUENCY 6 10 100 FIGURE 14. yIE vs FREQUENCY 100 REVERSE TRANSFER CONDUCTANCE (gRE) OR SUSCEPTANCE (bRE) (mS) FIGURE 13. yFE vs FREQUENCY 6 1.0 FREQUENCY (MHz) FREQUENCY (MHz) OUTPUT CONDUCTANCE (gOE) OR SUSCEPTANCE (bOE) (mS) hOE hFE = 100 hIE = 2.7kΩ hRE = 1.88 x 10-4 hOE = 15.6µS COMMON EMITTER CIRCUIT, BASE INPUT TA = 25oC, VCE = 5V, IC = 1mA gRE IS SMALL AT FREQUENCIES LESS THAN 500MHz 0 bRE -0.5 -1.0 -1.5 -2.0 1 10 FREQUENCY (MHz) FIGURE 16. FIGURE 16. yRE vs FREQUENCY 100 CA3146, CA3146A, CA3183, CA3183A Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued) TA = 25oC VCE = 5V TA = 25oC 1000 900 800 4 700 CAPACITANCE (pF) GAIN BANDWIDTH PRODUCT (MHz) Typical Performance Curves 600 500 400 300 200 3 2 CCI 1 CEB 100 CCB 0 0 1 2 3 4 5 6 7 8 9 10 11 0 12 13 14 1 2 3 4 5 COLLECTOR CURRENT (mA) FIGURE 17. fT vs IC 10-2 10-3 -25 0 25 50 75 100 FIGURE 19. ICEO vs TEMPERATURE FOR ANY TRANSISTOR 10-3 10-4 -50 -25 0 25 50 75 FIGURE 20. ICBO vs TEMPERATURE FOR ANY TRANSISTOR TA = 25oC 100 75 IC = 0.1mA 50 IC = 1mA IC = 10mA 25 DC FORWARD CURRENT TRANSFER RATIO (hFE) 125 VCE = 10V 90 80 70 VCE = 3V 60 50 40 0 25 50 75 100 TEMPERATURE (oC) FIGURE 21. hFE vs TEMPERATURE FOR ANY TRANSISTOR 7 100 TEMPERATURE (oC) 100 -25 14 10-2 VCE = 3V DC FORWARD CURRENT TRANSFER RATIO (hFE) 10 11 12 13 VCB = 10V TEMPERATURE (oC) 0 -50 9 10-1 10-1 10-4 -50 8 DC Characteristics - CA3183 Series VCE = 10V 1 7 FIGURE 18. CEB, CCB, CCI vs BIAS VOLTAGE COLLECTOR CUTOFF CURRENT (nA) COLLECTOR CUTOFF CURRENT (nA) Typical Performance Curves 6 BIAS VOLTAGE (V) 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 22. hFE vs IC FOR ANY TRANSISTOR CA3146, CA3146A, CA3183, CA3183A Typical Performance Curves TA = 25oC hFE = 10 TA = 0oC 0.8 TA = 70oC TA = 25oC 1.0 COLLECTOR TO EMITTER SATURATION VOLTAGE (V) BASE TO EMITTER VOLTAGE (V) 0.9 DC Characteristics - CA3183 Series (Continued) 0.7 0.6 0.5 0.4 0.1 0.3 0.1 1.0 10 10 FIGURE 24. VCE SAT vs IC FOR ANY TRANSISTOR ABSOLUTE INPUT - OFFSET CURRENT (µA) ABSOLUTE INPUT - OFFSET VOLTAGE (mV) FIGURE 23. VBE vs IC FOR ANY TRANSISTOR VCE = 3V TA = 25oC 1.0 TA = 0oC TA = 70oC 0.1 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 25. |VIO| vs IC FOR DIFFERENTIAL AMPLIFIER (Q1 AND Q2) 8 100 COLLECTOR CURRENT (mA) COLLECTOR CURRENT (mA) VCE = 3V TA = 25oC 1.0 0.1 0.1 1.0 10 COLLECTOR CURRENT (mA) FIGURE 26. |IIO| vs IC FOR DIFFERENTIAL AMPLIFIER (Q1 AND Q2) CA3146, CA3146A, CA3183, CA3183A Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 9 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 14 0.355 18.66 19.68 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 14 10.92 7 3.81 4 9 Rev. 0 12/93 CA3146, CA3146A, CA3183, CA3183A Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 C D 0.735 0.775 D1 0.005 - E 0.300 0.325 E1 0.240 0.280 6.10 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 10 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 16 0.204 0.355 18.66 - 19.68 5 0.13 - 5 7.62 8.25 6 7.11 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 16 10.92 7 3.81 4 9 Rev. 0 12/93 CA3146, CA3146A, CA3183, CA3183A Small Outline Plastic Packages (SOIC) M14.15 (JEDEC MS-012-AB ISSUE C) N INDEX AREA H 0.25(0.010) M 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- α e A1 B 0.25(0.010) M C A M C B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3367 0.3444 8.55 8.75 3 E 0.1497 0.1574 3.80 4.00 4 e 0.10(0.004) MILLIMETERS 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 14 0o 14 8o 0o 7 8o Rev. 0 12/93 CA3146, CA3146A, CA3183, CA3183A Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- α e B 0.25(0.010) M C 0.10(0.004) C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MAX MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e A1 MIN 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α 16 0o 16 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 12 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029