HA-5002 Data Sheet November 1998 110MHz, High Slew Rate, High Output Current Buffer File Number 2921.4 Features • • • • • • • • The HA-5002 is a monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing the advantages of the Intersil D.I. technologies, the HA-5002 current buffer offers 1300V/µs slew rate with 110MHz of bandwidth. The ±200mA output current capability is enhanced by a 3Ω output impedance. The monolithic HA-5002 will replace the hybrid LH0002 with corresponding performance increases. These characteristics range from the 3000kΩ input impedance to the increased output voltage swing. Monolithic design technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller gain error. Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.995 High Input Impedance . . . . . . . . . . . . . . . . . . . . . 3000kΩ Low Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . 3Ω Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . 1300V/µs Very Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . 110MHz High Output Current . . . . . . . . . . . . . . . . . . . . . . . ±200mA Pulsed Output Current . . . . . . . . . . . . . . . . . . . . . . 400mA Monolithic Construction Applications • • • • The HA-5002 will provide many present hybrid users with a higher degree of reliability and at the same time increase overall circuit performance. • • • • Line Driver Data Acquisition 110MHz Buffer Radar Cable Driver High Power Current Booster High Power Current Source Sample and Holds Video Products Ordering Information PART NUMBER (BRAND) For the military grade product, refer to the HA-5002/883 datasheet, AnswerFAX document #3705. TEMP. RANGE (oC) PACKAGE PKG. NO. HA2-5002-2 -55 to 125 8 Pin Metal Can T8.C HA2-5002-5 0 to 75 8 Pin Metal Can T8.C HA3-5002-5 0 to 75 8 Ld PDIP E8.3 HA4P5002-5 0 to 75 20 Ld PLCC N20.35 HA7-5002-2 -55 to 125 8 Ld CERDIP F8.3A HA7-5002-5 0 to 75 8 Ld CERDIP F8.3A HA9P5002-5 (H50025) 0 to 75 8 Ld SOIC M8.15 HA9P5002-9 (H50029) -40 to 85 8 Ld SOIC M8.15 Pinouts V2- 2 7 V2+ NC 3 6 NC 4 5 V1- NC 3 2 1 20 19 IN 8 V1+ NC 4 18 NC V2- 5 17 V2+ NC 6 16 NC NC 7 15 NC NC 8 14 NC V2+ 1 7 2 NC V1- 6 5 3 V2- NC 4 OUT 1 10 11 12 13 NC V1- NC NOTE: Case Voltage = Floating 9 IN IN OUT OUT NC 8 V1+ 1 HA-5002 (METAL CAN) TOP VIEW NC V1+ HA-5002 (PLCC) TOP VIEW NC HA-5002 (PDIP, CERDIP, SOIC) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-5002 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 44V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V1+ to V1Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . ±200mA Output Current (50ms On, 1s Off) . . . . . . . . . . . . . . . . . . . . ±400mA Thermal Resistance (Typical, Note 2) θJA (oC/W)θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 115 28 PDIP Package . . . . . . . . . . . . . . . . . . . 92 N/A Metal Can Package . . . . . . . . . . . . . . . 155 67 PLCC Package. . . . . . . . . . . . . . . . . . . 74 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 157 N/A Max Junction Temperature (Hermetic Packages, Note 1) . . . . . . 175oC Max Junction Temperature (Plastic Packages, Note 1) . . . . . . . . 150oC Max Storage Temperature Range . . . . . . . . . . . . . . -65oC to 150oC Max Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300oC (PLCC and SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5002-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-5002-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HA-5002-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including load conditions, must be designed to maintain the maximum junction temperature below 175oC for the ceramic and can packages, and below 150oC for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified Electrical Specifications TEST CONDITIONS PARAMETER HA-5002-2 HA-5002-5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 5 20 - 5 20 mV Full - 10 30 - 10 30 mV Full - 30 - - 30 - µV/οC INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Input Resistance Input Noise Voltage 25 - 2 7 - 2 7 µA Full - 3.4 10 - 2.4 10 µA Full 1.5 3 - 1.5 3 - MΩ 10Hz-1MHz 25 - 18 - - 18 - µVP-P RL = 50Ω 25 - 0.900 - - 0.900 - V/V RL = 100Ω 25 - 0.971 - - 0.971 - V/V TRANSFER CHARACTERISTICS Voltage Gain (VOUT = ±10V) RL = 1kΩ 25 - 0.995 - - 0.995 - V/V RL = 1kΩ Full 0.980 - - 0.980 - - V/V VIN = 1VP-P 25 - 110 - - 110 - MHz 25 - 40 - - 40 - A/mA RL = 100Ω 25 ±10 ±10.7 - ±10 ±11.2 - V RL = 1kΩ, VS = ±15V Full ±10 ±13.5 - ±10 ±13.9 - V RL = 1kΩ, VS = ±12V Full ±10 ±10.5 - ±10 ±10.5 - V VIN = ±10V, RL = 40Ω 25 - 220 - - 220 - mA Full - 3 10 - 3 10 Ω 25 - <0.005 - - <0.005 - % Full Power Bandwidth (Note 3) 25 - 20.7 - - 20.7 - MHz Rise Time 25 - 3.6 - - 3.6 - ns Propagation Delay 25 - 2 - - 2 - ns Overshoot 25 - 30 - - 30 - % -3dB Bandwidth AC Current Gain OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Resistance VIN = 1VRMS, f = 10kHz Harmonic Distortion TRANSIENT RESPONSE Slew Rate 25 1.0 1.3 - 1.0 1.3 - V/ns Settling Time To 0.1% 25 - 50 - - 50 - ns Differential Gain RL = 500Ω 25 - 0.06 - - 0.06 - % Differential Phase RL = 500Ω 25 - 0.22 - - 0.22 - Degrees 2 HA-5002 VSUPPLY = ±12V to ±15V, RS = 50Ω, RL = 1kΩ, CL = 10pF, Unless Otherwise Specified (Continued) Electrical Specifications TEST CONDITIONS PARAMETER HA-5002-2 HA-5002-5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 8.3 - - 8.3 - mA POWER REQUIREMENTS Supply Current AV = 10V Power Supply Rejection Ratio Full - - 10 - - 10 mA Full 54 64 - 54 64 - dB NOTE: 3. Slew Rate PBW = --------------------------- ; V P = 10V . 2πV P EAK Test Circuit and Waveforms +15V V1+ V2+ RS IN OUT V2- V1-15V RL FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE VIN VIN VOUT VOUT RS = 50Ω, RL = 100Ω RS = 50Ω, RL = 1kΩ SMALL SIGNAL WAVEFORMS SMALL SIGNAL WAVEFORMS VIN VIN VOUT VOUT RS = 50Ω, RL = 100Ω RS = 50Ω, RL = 1kΩ LARGE SIGNAL WAVEFORMS LARGE SIGNAL WAVEFORMS 3 HA-5002 Schematic Diagram V1+ R8 R9 RN1 Q19 R4 Q26 Q20 Q25 R10 V2+ R1 Q18 Q12 Q3 Q9 Q1 Q27 Q6 Q10 R5 Q7 IN R11 Q4 OUT RN2 Q21 Q5 Q11 Q2 Q22 Q8 Q15 Q23 Q24 Q17 Q16 V2- R6 Q13 Q14 R7 R12 R2 R3 RN3 V1- Application Information Layout Considerations Short Circuit Protection The wide bandwidth of the HA-5002 necessitates that high frequency circuit layout procedures be followed. Failure to follow these guidelines can result in marginal performance. The output current can be limited by using the following circuit: V+ VR LIM = -------------------------- = -------------------------I OUTMAX I OUTMAX Probably the most crucial of the RF/video layout rules is the use of a ground plane. A ground plane provides isolation and minimizes distributed circuit capacitance and inductance which will degrade high frequency performance. V+ V1 + IOUTMAX = 200mA (CONTINUOUS) RLIM V2+ OUT IN Other considerations are proper power supply bypassing and keeping the input and output connections as short as possible which minimizes distributed capacitance and reduces board space. V2- V1 - RLIM V- Power Supply Decoupling Capacitive Loading For optimal device performance, it is recommended that the positive and negative power supplies be bypassed with capacitors to ground. Ceramic capacitors ranging in value from 0.01 to 0.1µF will minimize high frequency variations in supply voltage, while low frequency bypassing requires larger valued capacitors since the impedance of the capacitor is dependent on frequency. The HA-5002 will drive large capacitive loads without oscillation but peak current limits should not be exceeded. Following the formula I = Cdv/dt implies that the slew rate or the capacitive load must be controlled to keep peak current below the maximum or use the current limiting approach as shown. The HA-5002 can become unstable with small capacitive loads (50pF) if certain precautions are not taken. Stability is enhanced by any one of the following: a source resistance in series with the input of 50Ω to 1kΩ; increasing capacitive load to 150pF or greater; decreasing CLOAD to 20pF or less; adding an output resistor of 10Ω to 50Ω; or adding feedback capacitance of 50pF or greater. Adding source resistance generally yields the best results. It is also recommended that the bypass capacitors be connected close to the HA-5002 (preferably directly to the supply pins). Operation at Reduced Supply Levels The HA-5002 can operate at supply voltage levels as low as ±5V and lower. Output swing is directly affected as well as slight reductions in slew rate and bandwidth. 4 HA-5002 1.8 MAXIMUM POWER DISSIPATION (W) 1.6 1.4 CAN T JMAX – T A P DMAX = -------------------------------------------θ JC + θ CS + θ SA PLCC 1.2 Where: TJMAX = Maximum Junction Temperature of the Device 1.0 TA = Ambient 0.8 CERDIP θJC = Junction to Case Thermal Resistance SOIC 0.6 θCS = Case to Heat Sink Thermal Resistance PDIP θSA = Heat Sink to Ambient Thermal Resistance 0.4 QUIESCENT POWER DISSIPATION AT ±15V SUPPLIES 0.2 T JMAX – T A P DMAX = -------------------------------θ JA Graph is based on: 0.0 25 65 45 85 125 105 TEMPERATURE (oC) FIGURE 2. MAXIMUM POWER DISSIPATION vs TEMPERATURE Typical Application +12V V1 + V2+ RS RM 50Ω 50Ω VIN RG -58 VOUT VIN V1- RL 50Ω V2-12V VOUT FIGURE 3. COAXIAL CABLE DRIVER - 50Ω SYSTEM Typical Performance Curves 9 VS = ±15V, RS = 50Ω GAIN 0 -3 PHASE -6 0o -9 45o -12 90o -15 135o -18 180o 10 100 FREQUENCY (MHz) FIGURE 4. GAIN/PHASE vs FREQUENCY (RL = 1kΩ) 5 VOLTAGE GAIN (dB) 3 1 VS = ±15V, RS = 50Ω 6 PHASE SHIFT VOLTAGE GAIN (dB) 6 3 GAIN 0 -3 PHASE -6 0o -9 45o -12 90o -15 135o -18 180o 1 10 100 FREQUENCY (MHz) FIGURE 5. GAIN/PHASE vs FREQUENCY (RL = 50Ω) PHASE SHIFT 9 HA-5002 Typical Performance Curves (Continued) 0.998 0.994 VS = ±15V VS = ±15V 0.992 0.997 VOLTAGE GAIN (V/V) VOLTAGE GAIN (V/V) 0.990 0.988 VOUT = -10V TO +10V 0.986 0.984 0.982 0.980 0.978 VOUT = 0 TO +10V 0.996 0.995 0.994 VOUT = 0 TO -10V 0.993 0.992 0.976 0.974 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 -20 20 40 60 80 100 120 7 VS = ±15V VS = ±15V 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 -60 -40 -20 TEMPERATURE (oC) 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE 15 0 FIGURE 7. VOLTAGE GAIN vs TEMPERATURE (RL = 1kΩ) BIAS CURRENT (µA) OFFSET VOLTAGE (mV) -40 TEMPERATURE (oC) FIGURE 6. VOLTAGE GAIN vs TEMPERATURE (RL = 100Ω) 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -60 0.991 -60 120 FIGURE 9. BIAS CURRENT vs TEMPERATURE 10 VS = ±15V, RLOAD = 100Ω VS = ±15V, IOUT = 0mA 14 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) 9 +VOUT -VOUT 13 12 8 7 6 5 4 11 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 120 FIGURE 10. MAXIMUM OUTPUT VOLTAGE vs TEMPERATURE 6 3 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 FIGURE 11. SUPPLY CURRENT vs TEMPERATURE 120 HA-5002 Typical Performance Curves (Continued) 10 VS = ±15V IOUT = 0mA 100K 8 -55oC IMPEDANCE (Ω) SUPPLY CURRENT (mA) 125oC, 25oC 6 4 ZIN 10K 1000 100 2 10 0 0 2 4 6 8 10 12 14 16 ZOUT 1 100K 18 1M SUPPLY VOLTAGE (±V) 80 RLOAD = 100Ω 70 60 TA = 25oC TA = 125oC, TA = -55oC 50 40 30 20 10 12 8 SUPPLY VOLTAGE (±V) 0 10K 5 FIGURE 14. VOUT MAXIMUM vs VSUPPLY 100K 1M FREQUENCY (Hz) 100M 10M FIGURE 15. PSRR vs FREQUENCY 1500 150 1400 100 VOUT - VIN (mV) SLEW RATE (V/µs) 100M FIGURE 13. INPUT/OUTPUT IMPEDANCE vs FREQUENCY PSRR (dB) VOUT MAX, VP-P AT 100kHz FIGURE 12. SUPPLY CURRENT vs SUPPLY VOLTAGE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 15 10M FREQUENCY (Hz) 1300 1200 1100 VS = ±15V TA = 25oC RL = 100 50 RL = 1K 0 -50 RL = 600 1000 -100 900 6 8 10 12 14 SUPPLY VOLTAGE (±V) 16 FIGURE 16. SLEW RATE vs SUPPLY VOLTAGE 7 18 -150 -10 -8 -6 -4 -2 0 2 4 INPUT VOLTAGE (VOLTS) 6 8 FIGURE 17. GAIN ERROR vs INPUT VOLTAGE 10 HA-5002 Die Characteristics DIE DIMENSIONS: SUBSTRATE POTENTIAL (Powered Up): 81 mils x 80 mils x 19 mils 2050µm x 2030µm x 483µm V1TRANSISTOR COUNT: METALLIZATION: 27 Type: Al, 1% Cu Thickness: 20kÅ ±2kÅ PROCESS: Bipolar Dielectric Isolation PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Metallization Mask Layout HA-5002 IN V1- V1- (ALT) V1+ (ALT) V2+ V2- V1+ OUT 8 HA-5002 Metal Can Packages (Can) T8.C MIL-STD-1835 MACY1-X8 (A1) REFERENCE PLANE A 8 LEAD METAL CAN PACKAGE e1 L L2 L1 INCHES ØD2 A A k1 Øe ØD ØD1 2 N 1 β Øb1 Øb F α k C L BASE AND SEATING PLANE Q BASE METAL Øb1 LEAD FINISH Øb2 SECTION A-A NOTES: 1. (All leads) Øb applies between L1 and L2. Øb1 applies between L2 and 0.500 from the reference plane. Diameter is uncontrolled in L1 and beyond 0.500 from the reference plane. 2. Measured from maximum diameter of the product. 3. α is the basic spacing from the centerline of the tab to terminal 1 and β is the basic spacing of each lead or lead position (N -1 places) from α, looking at the bottom of the package. 4. N is the maximum number of terminal positions. 5. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 6. Controlling dimension: INCH. 9 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.185 4.19 4.70 - Øb 0.016 0.019 0.41 0.48 1 Øb1 0.016 0.021 0.41 0.53 1 Øb2 0.016 0.024 0.41 0.61 - ØD 0.335 0.375 8.51 9.40 - ØD1 0.305 0.335 7.75 8.51 - ØD2 0.110 0.160 2.79 4.06 - e 0.200 BSC 5.08 BSC - e1 0.100 BSC 2.54 BSC - F - 0.040 - 1.02 - k 0.027 0.034 0.69 0.86 - k1 0.027 0.045 0.69 1.14 2 L 0.500 0.750 12.70 19.05 1 L1 - 0.050 - 1.27 1 L2 0.250 - 6.35 - 1 Q 0.010 0.045 0.25 1.14 - α 45o BSC 45o BSC β 45o BSC 45o BSC 3 N 8 8 4 3 Rev. 0 5/18/94 HA-5002 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 7. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 10. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 11. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 12. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 13. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 14. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 15. N is the maximum number of terminal positions. 16. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 10 MILLIMETERS e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 8 0.355 10.16 5 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 Rev. 0 12/93 HA-5002 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N20.35 (JEDEC MS-018AA ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 17. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 18. Dimensions and tolerancing per ANSI Y14.5M-1982. 19. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 20. To be measured at seating plane -C- contact point. 21. Centerline to be determined where center leads exit plastic body. 22. “N” is the number of terminal positions. 11 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.385 0.395 9.78 10.03 - D1 0.350 0.356 8.89 9.04 3 D2 0.141 0.169 3.59 4.29 4, 5 E 0.385 0.395 9.78 10.03 - E1 0.350 0.356 8.89 9.04 3 E2 0.141 0.169 3.59 4.29 4, 5 N 20 20 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE HA-5002 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) LEAD FINISH 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL E b1 M M (b) -Bbbb S C A-B S SECTION A-A D S D BASE PLANE Q -C- SEATING PLANE A L S1 α eA A A b2 b ccc M C A - B S e eA/2 c aaa M C A - B S D S D S NOTES: 23. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 24. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 25. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 26. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 27. This dimension allows for off-center lid, meniscus, and glass overrun. 28. Dimension Q shall be measured from the seating plane to the base plane. 29. Measure dimension S1 at all four corners. 30. N is the maximum number of terminal positions. 31. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 32. Controlling dimension: INCH 12 INCHES (c) MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - 3.81 BSC - eA/2 0.150 BSC L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 8 8 8 Rev. 0 4/94 HA-5002 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C A M MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S NOTES: 33. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 34. Dimensioning and tolerancing per ANSI Y14.5M-1982. 35. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 36. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 37. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 38. “L” is the length of terminal for soldering to a substrate. 39. “N” is the number of terminal positions. 40. Terminal numbers are shown for reference only. 41. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 42. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS MIN 0.050 BSC 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 5.80 - H 8 0o 6.20 - 8 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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