H CAT22C10 EE GEN FR ALO 256-Bit Nonvolatile CMOS Static RAM LE FEATURES ■ Single 5V Supply A D F R E ETM ■ Low CMOS Power Consumption: –Active: 40mA Max. –Standby: 30 µA Max. ■ Fast RAM Access Times: –200ns –300ns ■ JEDEC Standard Pinouts: –18-pin DIP –16-pin SOIC ■ Infinite EEPROM to RAM Recall ■ CMOS and TTL Compatible I/O ■ 10 Year Data Retention ■ Power Up/Down Protection ■ Commercial, Industrial and Automotive ■ 100,000 Program/Erase Cycles (E2PROM) Temperature Ranges ■ "Green" Package Options Available DESCRIPTION The CAT22C10 NVRAM is a 256-bit nonvolatile memory organized as 64 words x 4 bits. The high speed Static RAM array is bit for bit backed up by a nonvolatile EEPROM array which allows for easy transfer of data from RAM array to EEPROM (STORE) and from EEPROM to RAM (RECALL). STORE operations are completed in 10ms max. and RECALL operations typically within 1.5µs. The CAT22C10 features unlimited RAM write operations either through external RAM SOIC Package (J, W) A4 A3 A2 A1 NC A4 1 2 18 Vcc 17 A3 A2 3 4 16 15 NC A5 I/O3 A1 A0 5 6 7 8 14 13 12 11 I/O2 I/O1 I/O0 CS Vss WE STORE 9 10 RECALL CS Vss STORE The CAT22C10 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles (EEPROM) and has a data retention of 10 years. The device is available in JEDEC approved 18-pin plastic DIP and 16pin SOIC packages. PIN FUNCTIONS PIN CONFIGURATION DIP Package (P, L) writes or internal recalls from EEPROM. Internal false store protection circuitry prohibits STORE operations when VCC is less than 3.0V. A0 © 2004 by Catalyst Semiconductor, Inc., Patent Pending Characteristics subject to change without notice 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Pin Name Function A0–A5 Address Vcc A5 I/O4 I/O3 I/O2 I/O1 I/O0–I/O3 Data In/Out WE Write Enable CS Chip Select RECALL Recall WE RECALL STORE Store VCC +5V VSS Ground NC No Connect Doc. No. 1082, Rev. O CAT22C10 BLOCK DIAGRAM EEPROM ARRAY A0 ROW STATIC RAM SELECT ARRAY STORE A1 A2 A3 A4 A5 RECALL COLUMN SELECT CONTROL LOGIC STORE RECALL CS READ/WRITE CIRCUITS I/O0 I/O1 I/O2 I/O3 WE MODE SELECTION(1)(2)(3) Input CS WE RECALL STORE Standby H X H H Output High-Z RAM Read L H H H Output Data RAM Write L L H H Input Data (EEPROM→RAM) X H L H Output High-Z RECALL (EEPROM→RAM) H X L H Output High-Z RECALL (RAM→EEPROM) X H H L Output High-Z STORE (RAM→EEPROM) H X H L Output High-Z STORE Mode I/O POWER-UP TIMING(4) Symbol Parameter Min. Max. Units VCCSR VCC Slew Rate 0.5 0.005 V/ms Note: (1) RECALL signal has priority over STORE signal when both are applied at the same time. (2) STORE is inhibited when RECALL is active. (3) The store operation is inhibited when VCC is below ≈ 3.0V. (4) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1082, Rev. O 2 CAT22C10 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) .............. -2.0 to +VCC +2.0V VCC with Respect to Ground ................ -2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 10 Years MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 NEND(1) Endurance TDR(1) Data Retention VZAP(1) ESD Susceptibility 2000 Volts ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Unit Conditions ICC Current Consumption (Operating) 40 mA All Inputs = 5.5V TA = 0°C All I/O’s Open ISB Current Consumption (Standby) 30 µA CS = VCC All I/O’s Open ILI Input Current 10 µA 0 ≤ VIN ≤ 5.5V ILO Output Leakage Current 10 µA 0 ≤ VOUT ≤ 5.5V VIH High Level Input Voltage 2 VCC V VIL Low Level Input Voltage 0 0.8 V VOH High Level Output Voltage VOL Low Level Output Voltage VDH RAM Data Holding Voltage 2.4 1.5 V IOH = –2mA 0.4 V IOL = 4.2mA 5.5 V VCC CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Parameter Max. Unit Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. 3 Doc. No. 1082, Rev. O CAT22C10 A.C. CHARACTERISTICS, Write Cycle VCC = +5V ±10%, unless otherwise specified. 22C10-20 Symbol Parameter Min. Max. 22C10-30 Min. Max. Unit Conditions tWC Write Cycle Time 200 300 ns tCW CS Write Pulse Width 150 150 ns tAS Address Setup Time 50 50 ns CL = 100pF tWP Write Pulse Width 150 150 ns +1TTL gate tWR Write Recovery Time 25 25 ns VOH = 2.2V tDW Data Valid Time 100 100 ns VOL = 0.65V tDH Data Hold Time 0 0 ns VIH = 2.2V ns VIL = 0.65V tWZ(1) Output Disable Time tOW Output Enable Time 100 100 0 0 ns 22C10-20 22C10-30 A.C. CHARACTERISTICS, Read Cycle VCC = +5V ±10%, unless otherwise specified. Symbol Parameter Min. Max. tRC Read Cycle Time 200 tAA Address Access Time 200 tCO CS Access Time 200 tOH Output Data Hold Time 0 tLZ(1) CS Enable Time 0 tHZ(1) CS Disable Time Min. Max. Unit Conditions ns CL = 100pF 300 ns +1TTL gate 300 ns VOH = 2.2V 0 ns VOL = 0.65V 0 ns VIH = 2.2V ns VIL = 0.65V 300 100 100 Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1082, Rev. O 4 CAT22C10 A.C. CHARACTERISTICS, Store Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter tSTC Store Time tSTP Store Pulse Width tSTZ(1) Store Disable Time tOST(1) Store Enable Time Min. Max. Units 10 ms 200 100 0 Conditions ns CL = 100pF + 1TTL gate ns VOH = 2.2V, VOL = 0.65V ns VIH = 2.2V, VIL = 0.65V Units Conditions A.C. CHARACTERISTICS, Recall Cycle VCC = +5V ±10%, unless otherwise specified. Limits Symbol Parameter Min. Max. tRCC Recall Cycle Time 1.4 µs tRCP Recall Pulse Width 300 ns CL = 100pF + 1TTL gate tRCZ Recall Disable Time ns VOH = 2.2V, VOL = 0.65V tORC Recall Enable Time ns VIH = 2.2V, VIL = 0.65V tARC Recall Data Access Time 100 0 1.1 µs Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 5 Doc. No. 1082, Rev. O CAT22C10 array into the Static RAM. When the STORE input is taken low, it initiates a store operation which transfers the entire Static RAM array contents into the EEPROM array. DEVICE OPERATION The configuration of the CAT22C10 allows a common address bus to be directly connected to the address inputs. Additionally, the Input/Output (I/O) pins can be directly connected to a common I/O bus if the bus has less than 1 TTL load and 100pF capacitance. If not, the I/O path should be buffered. Standby Mode The chip select (CS) input controls all of the functions of the CAT22C10. When a high level is supplied to the CS pin, the device goes into the standby mode where the outputs are put into a high impendance state and the power consumption is drastically reduced. With ISB less than 100µA in standby mode, the designer has the flexibility to use this part in battery operated systems. When the chip select (CS) pin goes low, the device is activated. When CS is forced high, the device goes into the standby mode and consumes very little current. With the nonvolatile functions inhibited, the device operates like a Static RAM. The Write Enable (WE) pin selects a write operation when WE is low and a read operation when WE is high. In either of these modes, an array byte (4 bits) can be addressed uniquely by using the address lines (A0–A5), and that byte will be read or written to through the Input/Output pins (I/O0–I/O3). Read When the chip is enabled (CS = low), the nonvolatile functions are inhibited (STORE = high and RECALL = high). With the Write Enable (WE) pin held high, the data in the Static RAM array may be accessed by selecting an address with input pins A0–A5. This will occur when the outputs are connected to a bus which is loaded by no more than 100pF and 1 TTL gate. If the loading is greater than this, some additional buffering circuitry is recom- The nonvolatile functions are inhibited by holding the STORE input and the RECALL input high. When the RECALL input is taken low, it initiates a recall operation which transfers the contents of the entire EEPROM Figure 1. Read Cycle Timing tRC ADDRESS tAA tCO CS tLZ tOH HIGH-Z DATA I/O Doc. No. 1082, Rev. O tHZ DATA VALID 6 CAT22C10 mended. supplied to pins I/O0–I/O3. When these conditions, including the write pulse width time (tWP) are met, the data will be written to the specified location in the Static RAM. A write function may also be initiated from the standby mode by driving WE low, inhibiting the nonvolatile functions, supplying valid addresses, and then taking CS low and supplying input data. Write With the chip enabled and the nonvolatile functions inhibited, the Write Enable (WE) pin will select the write mode when driven to a low level. In this mode, the address must be supplied for the byte being written. After the set-up time (tAS), the input data must be Figure 2. Write Cycle Timing tWC ADDRESS tCW CS tAS tWR tWP WE tDW tDH DATA VALID DATA IN tWZ tOW HIGH-Z DATA OUT Figure 3. Early Write Cycle Timing tWC ADDRESS tCW CS tAS tWR tWP WE tDW tDH DATA VALID DATA IN HIGH-Z DATA OUT 7 Doc. No. 1082, Rev. O CAT22C10 place independent of the state of CS, WE or A0–A5. The STORE pin must be held low for the duration of the Store Pulse Width (tSTP) to ensure that a store operation is initiated. Once initiated, the STORE pin becomes a “Don’t Care”, and the store operation will complete its transfer of the entire contents of the Static RAM array into the EEPROM array within the Store Cycle time (tSTC). If a store operation is initiated during a write cycle, the contents of the addressed Static RAM byte and its corresponding byte in the EEPROM array will be unknown. Recall At anytime, except during a store operation, taking the RECALL pin low will initiate a recall operation. This is independent of the state of CS, WE, or A0–A5. After the RECALL pin has been held low for the duration of the Recall Pulse Width (tRCP), the recall will continue independent of any other inputs. During the recall, the entire contents of the EEPROM array is transferred to the Static RAM array. The first byte of data may be externally accessed after the recalled data access time from end of recall (tARC) is met. After this, any other byte may be accessed by using the normal read mode. During the store operation, the outputs are in a high impedance state. A minimum of 100,000 store operations can be performed reliably and the data written into the EEPROM array has a minimum data retention time of 10 years. If the RECALL pin is held low for the entire Recall Cycle time (tRCC), the contents of the Static RAM may be immediately accessed by using the normal read mode. A recall operation can be performed an unlimited number of times without affecting the integrity of the data. DATA PROTECTION DURING POWER-UP AND POWER-DOWN The outputs I/O0–I/O3 will go into the high impedance state as long as the RECALL signal is held low. The CAT22C10 has on-chip circuitry which will prevent a store operation from occurring when VCC falls below 3.0V typ. This function eliminates the potential hazard of spurious signals initiating a store operation when the system power is below 3.0V typ. Store At any time, except during a recall operation, taking the STORE pin low will initiate a store operation. This takes Figure 4. Recall Cycle Timing tRCC ADDRESS tRCP RECALL tARC CS tORC HIGH-Z DATA I/O DATA UNDEFINED tRCZ Figure 5. Store Cycle Timing tSTC tSTP STORE tSTZ HIGH-Z DATA I/O Doc. No. 1082, Rev. O 8 DATA VALID CAT22C10 ORDERING INFORMATION Prefix Device # CAT 22C10 Optional Company ID Product Number Suffix J I Temperature Range Blank = Commercial (0˚ - 70˚C) I = Industrial (-40˚ - 85˚C) A = Automotive (-40˚ - 105˚C)* Package P: PDIP J: SOIC (JEDEC) L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) -TE13 -20 Tape & Reel Speed 20: 200ns 30: 300ns * -40˚ to +125˚C is available upon request Notes: (1) The device used in the above example is a 22C10JI-20TE13 (SOIC, Industrial Temperature, 200ns Access Time, Tape & Reel) 9 Doc. No. 1082, Rev. O REVISION HISTORY Date 04/16/2004 Revision Comments O Add Lead free logo Update Features Update Pin Configuration Update Ordering Information Update Rev. Number Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1082 O 04/16/04