CAT5261 Dual Digitally Programmable Potentiometers (DPP™) with 256 Taps and SPI Interface FEATURES DESCRIPTION Two linear-taper digitally programmable potentiometers The CAT5261 is two Digitally Programmable Potentiometers (DPPs™) integrated with control logic and 8 bytes of NVRAM memory. Each DPP consists of a series of resistive elements connected between two externally accessible end points. The tap points between each resistive element are connected to the wiper outputs with CMOS switches. A separate 8-bit control register (WCR) independently controls the wiper tap switches for each DPP. Associated with each wiper control register are four 8-bit non-volatile memory data registers (DR) used for storing up to four wiper settings. Writing to the wiper control register or any of the nonvolatile data registers is via a SPI serial bus. On powerup, the contents of the first data register (DR0) for each of the potentiometers is automatically loaded into its respective wiper control register. 256 resistor taps per potentiometer End to end resistance 50 kΩ or 100 kΩ Potentiometer control and memory access via SPI interface Low wiper resistance, typically 100 Nonvolatile memory storage for up to four wiper settings for each potentiometer Automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation Standby current less than 1µA 1,000,000 nonvolatile WRITE cycles 100 year nonvolatile memory data retention The CAT5261 can be used as a potentiometer or as a two terminal, variable resistor. It is intended for circuit level or system level adjustments in a wide variety of applications. It is available in the -40°C to 85°C industrial operating temperature range and offered in a 24-lead SOIC and TSSOP package. 24-lead SOIC and 24-lead TSSOP Industrial temperature range Industrial temperature range For Ordering Information details, see page 14. FUNCTIONAL DIAGRAM PIN CONFIGURATION SOIC/TSSOP (W, Y) SO 1 ¯¯¯¯¯ 24 HOLD A0 2 23 SCK NC 3 22 NC NC 4 21 NC NC 5 20 NC NC 6 VCC 7 RL0 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 ¯¯¯ CS 11 14 A1 ¯¯¯ WP 12 13 SI RH0 CS SCK SI SO WIPER CONTROL REGISTERS RW0 RW1 CAT 19 NC 5261 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice SPI BUS INTERFACE RH1 WP A0 A1 HOLD 18 GND CONTROL LOGIC NONVOLATILE DATA REGISTERS RL0 1 RL1 Doc. No. MD-2122 Rev. G CAT5261 PIN DESCRIPTIONS SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses and data to be written to the CAT5261. Input data is latched on the rising edge of the serial clock. Pin # Name 1 SO Serial Data Output 2 A0 Device Address, LSB 3 NC No Connect SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT5261. During a read cycle, data is shifted out on the falling edge of the serial clock. 4 NC No Connect 5 NC No Connect 6 NC No Connect 7 VCC Supply Voltage 8 RL0 Low Reference Terminal for Potentiometer 0 9 RH0 High Reference Terminal for Potentiometer 0 10 RW0 Wiper Terminal for Potentiometer 0 11 Chip Select 12 ¯¯¯ CS ¯¯¯ WP A0, A1: Device Address Inputs These inputs set the device address when addressing multiple devices. A total of four devices can be addressed on a single bus. A match in the slave address must be made with the address input in order to initiate communication with the CAT5261. 13 SI Serial Input 14 A1 Device Address 15 RL1 Low Reference Terminal for Potentiometer 1 16 RH1 High Reference Terminal for Potentiometer 1 17 RW1 Wiper Terminal for Potentiometer 1 RH, RL: Resistor End Points The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. 18 GND Ground 19 NC No Connect 20 NC No Connect RW: Wiper The RW pins are equivalent to the wiper terminal of a mechanical potentiometer. 21 NC No Connect 22 NC No Connect SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT5261. Opcodes, byte addresses or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. Function Write Protection 23 SCK Bus Serial Clock ¯¯¯ CS : Chip Select ¯¯¯¯¯ 24 HOLD Hold ¯¯¯ CS is the Chip select pin. ¯¯¯ CS low enables the CAT5261 and ¯¯¯ CS high disables the CAT5261. ¯¯¯ CS high takes the SO output pin to high impedance and forces the devices into a Standby mode (unless an internal write operation is underway). The CAT5261 draws ZERO current in the Standby mode. A high to low transition on ¯¯¯ CS is required prior to any sequence being initiated. A low to high transition on ¯¯¯ CS after a valid write sequence is what initiates an internal write cycle. ¯¯¯ WP: Write Protect ¯¯¯ WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When ¯¯¯ WP is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). ¯¯¯ WP going low while ¯¯¯ CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, ¯¯¯ WP going low will have no effect on any write operation. ¯¯¯¯¯ : Hold HOLD ¯¯¯¯¯ pin is used to pause transmission to the CAT5261 while in the middle of a serial sequence without The HOLD ¯¯¯¯¯ must be brought low while SCK is low. The having to retransmit entire sequence at a later time. To pause, HOLD SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be ¯¯¯¯¯ is brought high, while SCK is low. (HOLD ¯¯¯¯¯ should be held high any ignored. To resume communication, HOLD ¯¯¯¯¯ may be tied high directly to VCC or tied to VCC through a resistor. time this function is not being used.) HOLD ¯¯¯ WP: Write Protect Input The ¯¯¯ WP pin when tied low prevents non-volatile writes to the device (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. See Write Protection on page 6 for more details. Doc. No. MD-2122 Rev. G 2 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 SERIAL BUS PROTOCOL The CAT5261 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT5261 to interface directly with many of today's popular microcontrollers. The CAT5261 contains an 8-bit instruction register .The instruction set and the operation codes are detailed in the instruction set table 3 on page 9. DEVICE OPERATION The CAT5261 is two resistor arrays integrated with an SPI serial interface logic, two 8-bit wiper control registers and eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and at the ends of the series resistors are connected to the output wiper terminals (RW) by a After the device is selected with ¯¯¯ CS going low the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice of the six op-codes that define the operation to be performed. CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile memory data registers via the SPI bus. Additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode. 3 Doc. No. MD-2122 Rev. G CAT5261 ABSOLUTE MAXIMUM RATINGS(1) Parameters Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground (1) (2) VCC with Respect to Ground Package Power Dissipation Capability (TA = 25ºC) Lead Soldering Temperature (10 s) Wiper Current Ratings -55 to +125 -65 to +150 -2.0 to +VCC + 2.0 -0.2 to +7.0 1.0 300 ±6 Units ºC °C V V W ºC mA Ratings +2.5 to +6.0 -40 to +85 Units V °C RECOMMENDED OPERATING CONDITIONS Parameters VCC Industrial Temperature POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol RPOT RPOT IW RW RW VTERM VN TCRPOT TCRATIO CH/CL/CW fc Parameter Potentiometer Resistance (-00) Potentiometer Resistance (-50) Potentiometer Resistance Tolerance RPOT Matching Power Rating Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (5) Relative Linearity (6) Temperature Coefficient of RPOT Ratiometric Temp. Coefficient Potentiometer Capacitances Frequency Response Test Conditions Min Limits Typ. 100 50 25°C, each pot IW = ±3 mA @ VCC = 3 V IW = ±3 mA @ VCC = 5 V 200 100 0 Max kΩ kΩ ±20 % 1 50 ±3 300 150 VCC % mW mA Ω Ω V nV√Hz % LSB (7) LSB (7) ppm/ºC ppm/ºC pF MHz (4) 0.4 (8) Rw(n)(actual)-R(n)(expected) Rw(n+1)-[Rw(n)+LSB](8) (4) (4) (4) RPOT = 50 kΩ (4) ±1 ±0.2 ±300 20 10/10/25 0.4 Units Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V. (4) This parameter is tested initially and after a design or process change that affects the parameter. (5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (7) LSB = RTOT / 255 or (RH - RL) / 255, single pot (8) n = 0, 1, 2, ..., 255 Doc. No. MD-2122 Rev. G 4 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 D.C. OPERATING CHARACTERISTICS VCC = +2.5 V to +6.0 V, unless otherwise specified. Symbol Max Units fSCL = 400 kHz, SDA = Open VCC = 6 V, Inputs = GNDs 1 mA Power Supply Current fSCK = 400 kHz, SDA Open 5 mA Non-volatile WRITE VCC = 6 V, Input = GND ISB Standby Current (VCC = 5 V) VIN = GND or VCC, SDA = Open 1 µA ILI Input Leakage Current VIN = GND to VCC 10 µA ILO Output Leakage Current VOUT = GND to VCC 10 µA VIL Input Low Voltage -1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 1.0 V VOL1 Output Low Voltage (VCC = 3 V) IOL = 3 mA 0.4 V VOH1 Output High Voltage IOH = -1.6 mA ICC1 ICC2 Parameter Test Conditions Power Supply Current Min VCC – 0.8 V (1) PIN CAPACITANCE TA = 25ºC, f = 1.0 MHz, VCC = 5 V, unless otherwise specified. Symbol COUT CIN (1) (1) Test Conditions Max Units Output Capacitance (SO) VOUT = 0 V 8 pF ¯¯¯¯¯, A0, A1) Input Capacitance (¯¯¯ CS , SCK, SI, ¯¯¯ WP, HOLD VIN = 0 V 6 pF Max Units A.C. CHARACTERISTICS Symbol Parameter Test Conditions Min tSU Data Setup Time 50 ns tH Data Hold Time 50 ns tWH SCK High Time 125 ns tWL SCK Low Time 125 ns fSCK Clock Frequency DC tLZ 3 MHz ¯¯¯¯¯ to Output Low Z HOLD 50 ns tRI(1) tFI(1) Input Rise Time 2 µs Input Fall Time 2 µs tHD tCD ¯¯¯¯¯ Setup Time HOLD ¯¯¯¯¯ Hold Time HOLD tV Output Valid from Clock Low tHO Output Hold Time tDIS Output Disable Time tHZ ¯¯¯¯¯ to Output High Z HOLD ¯¯¯ CS High Time tCS tCSS tCSH CL = 50 pF 100 ns 100 ns 200 0 ns 250 100 ¯¯¯ CS Setup Time ¯¯¯ CS Hold Time ns ns ns 2 ns 250 ns 250 ns Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 5 Doc. No. MD-2122 Rev. G CAT5261 POWER UP TIMING (1)(2) Symbol Parameter Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms Min Max Units WIPER TIMING Symbol Parameter tWRPO Wiper Response Time After Power Supply Stable 5 10 µs tWRL Wiper Response Time After Instruction Issued 5 10 µs Max Units 5 ms Max Units WRITE CYCLE LIMITS Symbol tWR Parameter Write Cycle Time RELIABILITY CHARACTERISTICS Symbol NEND (3) TDR(3) VZAP(3) ILTH(3) Parameter Reference Test Method Min Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte Data Retention MIL-STD-883, Test Method 1008 100 Years ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA Notes: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. (3) This parameter is tested initially and after a design or process change that affects the parameter. Figure 1. Synchronous Data Timing tCS VIH CS VIL tCSH tCSS SCK VIH tH tSU VIH SI tWL tWH VIL VALID IN VIL tRI tFI tV SO VOH HI-Z tHO tDIS HI-Z VOL Note: Dashed Line = mode (1, 1) Doc. No. MD-2122 Rev. G 6 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 ¯¯¯¯¯ Timing Figure 2. HOLD CS tCD tCD SCK tHD tHD HOLD tHZ HIGH IMPEDANCE SO tLZ by CMOS input signals or tied to VCC or VSS. The remaining two bits in the device address byte must be set to 0. INSTRUCTION AND REGISTER DESCRIPTION DEVICE TYPE / ADDRESS BYTE The first byte sent to the CAT5261 from the master/ processor is called the Device Address Byte. The most significant four bits of the Device Type address are a device type identifier. These bits for the CAT5261 are fixed at 0101[B] (refer to Table 1). INSTRUCTION BYTE The next byte sent to the CAT5261 contains the instruction and register pointer information. The four most significant bits used provide the instruction opcode I3 - I0. The R1 and R0 bits point to one of the four data registers of each associated potentiometer. The least two significant bits point to one of two Wiper Control Registers. The format is shown in Table 2. The two least significant bits in the slave address byte, A1 - A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 - A0 input pins for the CAT5261 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven Data Register Selection Data Register Selected R1 R0 DR0 0 0 DR1 0 1 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode I3 I2 Data Register Selection I1 I0 R1 (MSB) © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice R0 WCR/Pot Selection P1 P0 (LSB) 7 Doc. No. MD-2122 Rev. G CAT5261 If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as standard memory locations for system parameters or user preference data. WIPER CONTROL AND DATA REGISTERS Wiper Control Register (WCR) The CAT5261 contains two 8-bit Wiper Control Registers, one for each potentiometer. The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written by the host via Write Wiper Control Register instruction; it may be written by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction; it can be modified one step at a time by the Increment/decrement instruction (see Instruction section for more details). Finally, it is loaded with the content of its data register zero (DR0) upon power-up. Write in Process The contents of the Data Registers are saved to nonvolatile memory when the ¯¯¯ CS input goes HIGH after a write sequence is received. The status of the internal write cycle can be monitored by issuing a Read Status command to read the Write in Process (WIP) bit. INSTRUCTIONS Five of the ten instructions are three bytes in length. These instructions are: — Read Wiper Control Register – read the current wiper position of the selected potentiometer in the WCR — Write Wiper Control Register – change current wiper position in the WCR of the selected potentiometer — Read Data Register – read the contents of the selected Data Register — Write Data Register – write a new value to the selected Data Register The Wiper Control Register is a volatile register that loses its contents when the CAT5261 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers (DR) Each potentiometer has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Control Register. Any data changes in one of the Data Registers is a non-volatile operation and will take a maximum of 5ms. — Read Status – Read the status of the WIP bit which when set to "1" signifies a write cycle is in progress. Table 3. Instruction Set Instruction Read Wiper Control Register Note: 1/0 = data is one or zero Instruction Set I3 I2 I1 1 0 0 I0 1 R1 0 R0 0 WCR1/ P1 1/0 WCR0/ P0 1/0 Write Wiper Control Register 1 0 1 0 0 0 1/0 1/0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 XFR Data Register to Wiper Control Register 1 1 0 1 1/0 1/0 1/0 1/0 XFR Wiper Control Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Global XFR Data Registers to Wiper Control Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Control Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Control Register Read Status (WIP bit) 0 0 1 0 0 0 1/0 1/0 0 1 0 1 0 0 0 1 Doc. No. MD-2122 Rev. G 8 Operation Read the contents of the Wiper Control Register pointed to by P1-P0 Write new value to the Wiper Control Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 Transfer the contents of the Data Register pointed to by P1-P0 and R1R0 to its associated Wiper Control Register Transfer the contents of the Wiper Control Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Control Registers Transfer the contents of both Wiper Control Registers to their respective data Registers pointed to by R1-R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1-P0 Read WIP bit to check internal write cycle status © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 The basic sequence of the three byte instructions is illustrated in Figure 8. These three-byte instructions exchange data between the WCR and one of the Data Registers. The WCR controls the position of the wiper. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the potentiometers and one of its associated registers; or the transfer can occur between both potentiometers and one associated register. — Global XFR Data Register to Wiper Control Register This transfers the contents of all specified Data Registers to the associated Wiper Control Registers. — Global XFR Wiper Counter Register to Data Register This transfers the contents of all Wiper Control Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 9 and 10). The Increment/Decrement command is different from the other commands. Once the command is issued the master can clock the selected wiper up and/ or down in one segment steps; thereby providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. Four instructions require a two-byte sequence to complete, as illustrated in Figure 7. These instructions transfer data between the host/processor and the CAT5261; either between the host and one of the data registers or directly between the host and the Wiper Control Register. These instructions are: — XFR Data Register to Wiper Control Register This transfers the contents of one specified Data Register to the associated Wiper Control Register. — XFR Wiper Control Register to Data Register This transfers the contents of the specified Wiper Control Register to the specified associated Data Register. See Instructions format for more detail. Figure 7. Two-Byte Instruction Sequence SI 0 1 0 1 0 0 ID3 ID2 ID1 ID0 A3 A2 A1 A0 I3 Internal Address Device ID I2 I1 R1 R0 P1 P0 I0 Instruction Opcode Register Address Pot/WCR Address Figure 8. Three-Byte Instruction Sequence SI 0 1 0 1 0 0 A2 ID3 ID2 ID1 ID0 A3 A1 A0 I3 Internal Address Device ID I2 I1 I0 R1 R0 P1 P0 Instruction Opcode D7 D6 D5 D4 D3 D2 D1 D0 Data Pot/WCR Register Address Address WCR[7:0] or Data Register D[7:0] Figure 9. Increment/Decrement Instruction Sequence SI 0 1 0 1 0 ID3 ID2 ID1 ID0 A3 Device ID © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 0 A2 A1 A0 Internal Address I3 I2 I1 I0 Instruction Opcode 9 R1 R0 P1 P0 I N Pot/WCR C Data Register Address 1 Address I N C 2 I N C n D E C 1 D E C n Doc. No. MD-2122 Rev. G CAT5261 Figure 10. Increment/Decrement Timing Limits INC/DEC Command Issued tWRL SCK SI Voltage Out RW INSTRUCTION FORMAT Read Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 INSTRUCTION A 1 0 0 0 1 0 0 DATA P 1 P 0 7 6 5 4 3 2 1 0 ¯¯¯ CS Write Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 INSTRUCTION A 0 1 0 1 0 A 0 1 0 1 1 R 1 0 DATA 0 P 1 7 P 0 6 5 4 3 2 1 0 ¯¯¯ CS Read Data Register (DR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 INSTRUCTION R 0 DATA P 1 P 7 6 5 4 3 2 1 0 ¯¯¯ CS 0 Write Data Register (DR) DEVICE ADDRESSES INSTRUCTION DATA 0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3 2 1 0 ¯¯¯ High Voltage ¯¯¯ CS CS Write Cycle 1 0 1 0 1 0 Read Status (WIP) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS Doc. No. MD-2122 Rev. G 0 0 A 1 A 0 INSTRUCTION 0 1 0 1 0 0 10 DATA 0 1 7 0 6 0 5 0 4 0 3 0 2 0 1 W ¯¯¯ CS 0 I P © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 Global Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 INSTRUCTION A 0 0 0 0 1 R R 1 0 0 0 ¯¯¯ CS Global Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES 0 1 0 1 0 ¯¯¯ CS INSTRUCTION A A 1 0 0 0 R R 0 1 0 1 0 0 0 ¯¯¯ High Voltage CS Write Cycle Transfer Wiper Control Register (WCR) to Data Register (DR) DEVICE ADDRESSES 0 1 0 1 0 ¯¯¯ CS INSTRUCTION A A 1 1 1 0 R R P P ¯¯¯ High Voltage CS Write Cycle 1 0 1 0 1 0 0 Transfer Data Register (DR) to Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 INSTRUCTION A 0 1 1 0 1 R R P 1 0 1 P ¯¯¯ CS 0 Increment (I)/Decrement (D) Wiper Control Register (WCR) DEVICE ADDRESSES 0 1 0 1 ¯¯¯ CS 0 0 A 1 A 0 INSTRUCTION 0 0 1 0 0 0 DATA P P I/D I/D 1 0 ... I/D I/D ¯¯¯ CS Notes: (1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 11 Doc. No. MD-2122 Rev. G CAT5261 PACKAGE OUTLINE DRAWINGS SOIC 24-Lead 300 mils (W) E1 SYMBOL MIN E e PIN#1 IDENTIFICATION MAX A 2.35 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.33 D 15.20 15.40 E 10.11 10.51 E1 7.34 e b NOM 7.60 1.27 BSC h 0.25 0.75 L 0.40 1.27 θ 0° 8° θ1 5° 15° TOP VIEW h D A2 A A1 SIDE VIEW h θ1 θ θ1 L c END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC specification MS-013. Doc. No. MD-2122 Rev. G 12 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 TSSOP 24-Lead 4.4 mm (Y) b SYMBOL MIN NOM MAX A E1 E 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 D 7.70 7.80 7.90 E 6.25 6.40 6.55 E1 4.30 4.40 4.50 0.20 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.70 8° e TOP VIEW D c A2 A θ1 L1 A1 L SIDE VIEW END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC specification MO-153. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 13 Doc. No. MD-2122 Rev. G CAT5261 EXAMPLE OF ORDERING INFORMATION (1) Prefix Device # Suffix CAT 5261 Company ID W I Package W: SOIC Y: TSSOP Temperature Range I = Industrial (-40ºC to 85ºC) -00 - T1 Resistance 50: 50 kΩ 00: 100 kΩ Tape & Reel T: Tape & Reel 1: 1000/Reel - SOIC 2: 2000/Reel - TSSOP Product Number 5261 ORDERING INFORMATION Orderable Part Number Resistance (kΩ) CAT5261WI-50-T1 50 CAT5261WI-00-T1 100 CAT5261YI-50-T2 50 CAT5261YI-00-T2 100 CAT5261WI50 50 CAT5261WI00 100 CAT5261YI50 50 CAT5261YI00 100 Package Lead Finish SOIC TSSOP Matte-Tin SOIC TSSOP Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The device used in the above example is a CAT526159WI-00-T1 (SOIC, Industrial Temperature, 100 kΩ, Tape & Reel). Doc. No. MD-2122 Rev. G 14 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5261 REVISION HISTORY Date Rev. Description 18-Nov-03 A Initial Issue 04-Apr-04 B Updated wiper resistance from 50Ω to 100Ω Updated Functional Diagram Updated ¯¯¯ WP Pin Description Updated notes in Absolute Max Ratings Eliminated Commercial temp range in all areas Updated Potentiometer Characteristics table Updated DC Characteristics table Updated Pin Capacitance table Updated AC Characteristics table Added Wiper Timing Table on page 6 Corrected Synchronous Data Timing (Figure 1) drawing 21-Sep-04 C Updated Figure 8 (Three Byte Instruction Sequence) 31-Jul-07 D Updated Example of Ordering Information Update Package Outline Drawings Added MD- to document number 07-Feb-08 E Update Instruction Format – Read Data Register (DR) and Write Data Register (DR) 24-Nov-08 F Change logo and fine print to ON Semiconductor 05-Aug-09 G Update Ordering Information table ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-2122 Rev. G