Revised April 2002 CD4023BC Buffered Triple 3-Input NAND Gate General Description Features These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS. ■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4023BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4023BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4023BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Connection Diagram Block Diagram 1 Top View © 2002 Fairchild Semiconductor Corporation /3 Device Shown *All Inputs Protected by Standard CMOS Input Protection Circuit. DS005956 www.fairchildsemi.com CD4023BC Buffered Triple 3-Input NAND Gate October 1987 CD4023BC Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5 VDC to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5 VDC to VDD+0.5 VDC −65°C to +150°C Storage Temp. Range (TS) 5 VDC to 15 VDC Input Voltage (VIN) 0 VDC to VDD VDC Operating Temperature Range (TA) −55°C to +125°C Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. 260°C (Soldering, 10 seconds) Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol IDD VOL VOH VIL Parameter Quiescent Device Current −55°C Conditions Min VDD = 10V 0.5 0.005 0.5 15 VDD = 15V 1.0 0.006 1.0 30 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 4.95 4.95 5 4.95 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 VDD=5V, VO=4.5V |IO|<1µA VDD=5V, VO=0.5V 1.5 4 3.0 3.0 4.0 6 4.0 4.0 3 7.0 6 7.0 VDD=15V, VO=1.5V 11.0 11.0 9 11.0 LOW Level Output Current VDD=5V, VO = 0.4V Input Current 0.64 0.51 0.88 0.36 1.6 1.3 2.2 0.90 VDD = 15V, VO = 1.5V 4.2 3.4 8 2.4 −0.64 −0.51 −0.88 −0.36 VDD = 10V, VO = 9.5V −1.6 −1.3 −2.2 −0.90 VDD = 15V, VO = 13.5V −4.2 −3.4 −8 −2.4 www.fairchildsemi.com mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 0.1 10−5 0.1 1.0 Note 4: IOH and IOL are tested one output at a time. 2 V V VDD = 15V, VIN = 15V Note 3: VSS = 0V unless otherwise specified. V 3.5 VDD = 10V, VO = 0.5V HIGH Level Output Current VDD = 5V, VO = 4.6V µA 1.5 3.5 (Note 4) IIN 2 3.0 7.0 |IO|<1µA Units V 1.5 3.5 (Note 4) Max 7.5 VDD=10V, VO=1.0V IOH Min 0.25 VDD=15V, VO=13.5V IOL Max 0.004 HIGH Level Output Voltage VDD = 5V HIGH Level Input Voltage +125°C Typ 0.25 VDD=10V, VO=9.0V VIH Min VDD = 5V LOW Level Output Voltage VDD = 5V LOW Level Input Voltage +25°C Typ µA (Note 5) TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise specified Symbol tPHL tPLH tTHL, Parameter Propagation Delay, HIGH-to-LOW Level Propagation Delay, LOW-to-HIGH Level Transition Time tTLH Conditions Typ Max VDD = 5V Min 130 250 VDD = 10V 60 100 VDD = 15V 40 70 VDD = 5V 110 250 VDD = 10V 50 100 VDD = 15V 35 70 VDD = 5V 90 200 VDD = 10V 50 100 VDD = 15V 40 80 7.5 CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacity (Note 6) Any Gate 17 Units ns ns ns pF pF Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note AN-90. 3 www.fairchildsemi.com CD4023BC AC Electrical Characteristics CD4023BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 CD4023BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com CD4023BC Buffered Triple 3-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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