CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 D D D D D D D D D D 300-MHz Differential Clock Source for Direct RAMBUS Memory Systems for an 600-MHz Data Transfer Rate Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications Operates From a Single 3.3-V Supply and 120-mW at 300 MHz (Typ) Packaged in a Shrink Small-Outline Package (DBQ) Wide Phase-Lock Input Frequency Range 33 MHz to 100 MHz No External Components Required for PLL Supports Independent Channel Clocking Spread Spectrum Clocking Tracking Capability to Reduce EMI Designed For Use With TI’s 133-MHz Clock Synthesizers CDC925, CDC924, CDC922 and CDC921 DBQ PACKAGE (TOP VIEW) VDDIR REFCLK VDDP GNDP GNDI PCLKM SYNCLKN GNDC VDDC VDDIPD STOPB PWRDNB 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 S0 S1 VDDO GNDO CLK NC CLKB GNDO VDDO MULT0 MULT1 S2 NC – No internal connection description The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on desktop, workstation, server and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLK/M = SYNCLK/N, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLK/M and SYNCLK/N and adjusts the phase of BUSCLK such that the skew between PCLK/M and SYNCLK/N is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz with clock references ranging from 33 MHz to 100 MHz. The CDCR81 meets Rambus Clock Generator, Revision 1.0 specification up to 300 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Direct Rambus and Rambus are trademarks of Rambus Inc. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 description (continued) The CDCR81 is characterized for operation over free-air temperatures of 0°C to 85°C. functional block diagram PWRDWNB S0 S1 S2 STOPB Test MUX Bypass MUX ByPCLK PLLCLK CLK PLL B REFCLK CLKB Phase Aligner A PACLK φD 2 PCLKM MULT0 MULT1 SYNCLKN FUNCTION TABLE† S0 S1 S2 CLK CLKB Normal 0 0 0 Phase aligned clock Phase aligned clock B Bypass 1 0 0 PLLCLK PLLCLKB Test 1 1 0 REFCLK REFCLKB Output test (OE) 0 1 X Hi-Z Hi-Z Reserved 0 0 1 — — Reserved 1 0 1 — — Hi-Z Hi-Z MODE Reserved 1 1 1 † X = don’t care, Hi-Z = high impedance 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CLK 20 O Output clock CLKB 18 O Output clock (complement) GNDC 8 GND for phase aligner GNDI 5 GND for control inputs GNDO 17, 21 GND for clock outputs GNDP 4 MULT0 15 I PLL multiplier select MULT1 14 I PLL multiplier select NC 19 GND for PLL Not used PCLKM 6 I Phase detector input PWRDNB 12 I Active low power down REFCLK 2 I Reference clock S0 24 I Mode control S1 23 I Mode control S2 13 I Mode control STOPB 11 I Active low output disable SYNCLKN 7 I Phase detector input VDDC VDDIPD 9 10 VDD for phase aligner Reference voltage for phase detector inputs and STOPB 1 Reference voltage for REFCLK VDDIR VDDO 16, 22 VDDP 3 VDD for clock outputs VDD for PLL POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 PLL divider selection Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted, provided that (267 MHz < BUSCLK < 400 MHz) and (33 MHz < REFCLK < 100 MHz). Table 1. REFCLK and BUSCLK Frequencies MULT0 MULT1 REFCLK (MHz) MULTIPLY RATIO BUSCLK (MHz) 0 0 67 4 267 0 1 50 6 300 0 1 67 6 400 1 1 33 8 267 1 1 50 8 400 1 0 100 8/3 267 clock output driver states Table 2. Clock Output Driver States STATE PWRDNB STOPB CLK CLKB Powerdown 0 X GND GND CLK stop 1 0 Normal 1 1 VX, STOP PACLK/PLLCLK/ REFCLK† VX, STOP PACLKB/PLLCLKB/ REFCLKB † Depending on the state of S0, S1, and S2. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Output voltage range, VO, at any output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Input voltage range,VI, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V ESD rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C‡ TA = 70°C POWER RATING TA = 85°C POWER RATING DBQ 1400 mW 11 mW/°C 905 mW 740 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 recommended operating conditions Supply voltage, VDD High-level input voltage, VIH (CMOS) MIN NOM MAX UNIT 3.135 3.3 3.465 V 0.7×VDD Low-level input voltage, VIL (CMOS) Initial phase error at phase detector inputs (required range for phase aligner) – 0.5×tc(PD) REFCLK low-level input voltage, VIL REFCLK high-level input voltage, VIH V 0.3×VDD 0.5×tc(PD) V 0.3×VDDIR V 0.7×VDDIR Input signal low voltage, VIL (STOPB) V 0.3×VDDIPD Input signal high voltage, VIH (STOPB) Input reference voltage for (REFCLK) (VDDIR) Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD) 0.7×VDDIPD 1.235 3.465 1.235 3.465 V V V V High-level output current, IOH –16 mA Low-level output current, IOL 16 mA 85 °C Operating free-air temperature, TA 0 timing requirements Input cycle time, tc(in) MIN MAX 10 40 ns 250 ps 40% 60% 30 33 Input cycle-to-cycle jitter Input duty cycle over 10,000 cycles Input frequency modulation, fmod Modulation index, non-linear maximum 0.5% UNIT kHz 0.6% Phase detector input cycle time (PCLKM and SYNCLKN) Input slew rate, SR Input duty cycle (PCLKM and SYNCLKN) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 30 100 1 4 25% 75% ns V/ns 5 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS† PARAMETER MIN TYP‡ MAX UNIT VO(STOP) Output voltage during CLK Stop (StopB=0) See Figure 1 1.1 2 VO(X) VO Output crossing-point voltage See Figures 1 and 6 1.3 1.8 V Output voltage swing See Figure 1 0.4 0.6 V VIK Input clamp voltage VDD = 3.135 V, See Figure 1 –1.2 V VOH VOL IOH IOL High-level output voltage Low-level output voltage High-level output current 2 VDD = min to max, IOH = –1 mA VDD = 3.135 V, See Figure 1 IOH = –16 mA VDD = min to max, VDD = 3.135 V, IOL = 1 mA IOL = 16 mA VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, VO = 1 V VO = 1.65 V VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, Low-level output current II = –18 mA VO = 3.135 V VO = 1.95 V S0 = 0, IOZ(STOP) High-impedance-state output current during CLK stop Stop= 0, VO = GND or VDD IOZ(PD) High-impedance-state output current in powerdown state PWDNB= 0, VO = GND or VDD IIH g High-level input current ZO Output impedance Reference current 0.1 –32 –52 mA –51 –14.5 43 –21 61.5 mA 65 25.5 S1 = 1 –10 36 ± 10 µA ± 100 µA 100 µA VDD = 3.465 V, VI = VDD 10 PWRDNB, S0, S1, S2, MULT0, MULT1 VDD = 3.465 V, VI = VDD 10 REFCLK, PCLKM, SYNCLKN, STOPB VDD = 3.465 V, VI = 0 –10 PWRDNB, S0, S1, S2, MULT0, MULT1 VDD = 3.465 V, VI = 0 –10 High state RI at IO –14.5 mA to –16.5 mA 15 26 40 Low state RI at IO 14.5 mA to 16.5 mA 11 17 35 VDDIR IR, VDDIPD VDD = 3.465 3 465 V, V Input capacitance CO Output capacitance IDD(PD) Supply current in powerdown state V 0.5 REFCLK, PCLKM, SYNCLKN, STOPB CI µA µA 50 µA PWRDNB = 1 0.5 mA VI = VDD or GND VO = VDD or GND REFCLK = 0 MHz to 100 MHz, PWDNB = 0, STOPB = 1 POST OFFICE BOX 655303 Ω PWRDNB = 0 IDD(CLKSTOP) Supply current in CLK stop state BUSCLK configured for 400 MHz IDD(NORMAL) Supply current in normal state BUSCLK = 400 MHz † VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP ‡ All typical values are at VDD = 3.3 V, TA = 25°C. 6 2.4 VO = 1.65 V VO = 0.4 V High-impedance-state output current IIL V 1 IOZ Low-level input current VDD– 0.1 V • DALLAS, TEXAS 75265 1.8 pF 3.1 pF 200 µA 30 mA 70 mA CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tc(out) Clock output cycle time t(jitter) Total cycle jitter over 1, 2, 3, 4, 5, or 6 clock cycles TEST CONDITIONS Stopped phase alignment 267 MHz – 400 MHz Infinite phase alignment 267 MHz 300 MHz See Figure 3 PLL output phase error when tracking SSC Dynamic phase error t(DC) Output duty cycle over 10,000 cycles See Figure 4 267 MHz – 400 MHz –50 300 MHz ns 60 ps ps 50 ps –100 100 ps 45% 55% See Figure 5 50 267 MHz IInfinite fi it phase h alignment UNIT 3.75 70 Static phase error Stopped phase alignment MAX 80 See Figure 3 Phase detector phase error for distributed loop t(DC, err) TYP† 2.5 t(phase) t(phase, SSC) Output cycle-to-cycle duty cycle error MIN ps 70 See Figure 5 80 400 MHz ps 90 tr, tf Output rise and fall times (measured at 20%-80% of output voltage) See Figure 7 ∆t Difference between rise and fall times on a single device (20%–80%) |tf – tr| See Figure 7 200 450 ps 100 ps † All typical values are at VDD = 3.3 V, TA = 25°C. state transition latency specifications PARAMETER t(powerup) ( ) t(VDDpowerup)) Delay time, PWRDNB↑ to CLK/CLKB output settled (excluding t(DISTLOCK)) Delay time, PWRDNB↑ to internal PLL and clock are on and settled FROM TO Powerdown Normal VDD Normal Delay time, powerup to CLK/CLKB output settled MULT0 and MULT1 change to CLK/CLKB output resettled (excluding t(DISTLOCK)) t(CLKON) See Figure 8 MIN TYP† MAX UNIT 3 ms 3 See Figure 8 Delay time, powerup to internal PLL and clock are on and settled t(MULT) TEST CONDITIONS 3 ms 3 Normal Normal See Figure 9 1 ms STOPB↑ to CLK/CLKB glitch-free clock edges CLK Stop Normal See Figure 10 10 ns t(CLKSETL) STOPB↑ to CLK/CLKB output settled to within 50 ps of the phase before STOPB was disabled CLK Stop Normal See Figure 10 20 cycles t(CLKOFF) STOPB↑ to CLK/CLKB output disabled Normal CLK Stop See Figure 10 5 ns t(powerdown) Delay time, PWRDNB↓ to the device in powerdown mode STOPB Powerdown 1 ms t(STOP) Maximum time in CLKSTOP (STOPB = 0) before re-entering normal mode (STOPB = 1) STOPB Normal 100 µs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 state transition latency specifications (continued) PARAMETER FROM TO t(ON) Minimum time in normal mode (STOPB = 1) before re-entering CLKSTOP (STOPB = 0) Normal CLK stop t(DISTLOCK) Time from when CLK/CLKB output is settled to when the phase error between SYNCLKN and PCLKM falls within t(ERR-PD) Unlocked Locked TEST CONDITIONS MIN TYP† 100 68 Ω, ±5% 39 Ω, ±5% RT = 28 Ω 39 Ω, ±5% 68 Ω, ±5% RT = 28 Ω 100 pF 10 pF Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL) CLK CLKB tc1 tc2 Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles Figure 2. Cycle-to-Cycle Jitter CLK CLKB tc3 tc4 Cycle-to-cycle jitter = | tc3 – tc4| over 10000 consecutive cycles Figure 3. Short Term Cycle-to-Cycle Jitter over 4 Cycles 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ms 5 PARAMETER MEASUREMENT INFORMATION 10 pF MAX ms CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION CLK CLKB tpd1 tc5 Duty cycle = (tPd1/tc5) Figure 4. Output Duty Cycle CLK CLKB tpd2 tpd3 tc6 tc7 Duty cycle error = tpd2 – tpd3 Figure 5. Duty Cycle Error (Cycle-to-Cycle) CLK VO(X)+ VO(X), nom VO(X)– CLKB Figure 6. Crossing-Point Voltage VOH 80% 20% VOL tr tf Figure 7. Voltage Waveforms PWRDNB CLK/CLKB ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ tpowerdown tpowerup Figure 8. PWRDNB Transition Timings POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ÎÎ ÎÎ 9 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION MULT0 and/or MULT1 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ CLK/CLKB tMULT Figure 9. MULT Transition Timings tON tSTOP STOPB tCLKSETL tCLKON (see Note A) CLK/CLKB ÎÎÎÎ ÎÎÎÎ Output clock not specified glitches ok Clock enabled and glitch free ÎÎ ÎÎ Clock output settled within 50 ps of the phase before disabled NOTE A: Vref = VO ± 200 mV Figure 10. STOPB Transition Timings 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tCLKOFF (see Note A) CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 PARAMETER MEASUREMENT INFORMATION HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE I OH – High-Level Output Current – A 0 –0.02 Weak –0.04 Rambus (min) –0.06 Nom –0.08 Strong –0.1 Rambus (max) –0.12 0 0.5 1 1.5 2 2.5 3 3.5 4 VOH – High-Level Output Voltage – V Figure 11. Pullup IBIS I/V Chart LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE I OL – Low-Level Output Current – A 0.12 0.1 Rambus (max) 0.08 Strong 0.06 Nom 0.04 Weak 0.02 Rambus (min) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VOL – Low-Level Output Voltage – V Figure 12. Pulldown IBIS I/V Chart POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 MECHANICAL DATA DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 24–PIN SHOWN 0.012 (0,30) 0.008 (0,20) 0.025 (0,64) 24 0.005 (0,13) M 13 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (3,99) 0.150 (3,81) 1 Gage Plane 12 A 0.010 (0,25) 0°– 8° 0.035 (0,89) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.197 (5,00) 0.344 (8,74) 0.344 (8,74) A MIN 0.188 (4,78) 0.337 (8,56) 0.337 (8,56) DIM 4073301/C 02/97 NOTES: A. B. C. D. 12 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-137 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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