Digital Multi-Phase Buck Controller DESCRIPTION Compatible with IR ATL Drivers and tri-state Drivers 9 bytes of NVM storage available for customer use +3.3V supply voltage; 0ºC to 85ºC Ambient operation RoHS Compliant, MSL level 1 package APPLICATIONS Intel® VR11.x CPU VRD and VRM; DDR Memory High Performance Desktops and Servers Over-clocking and High-Efficiency Application The CHL8318-20 provides extensive OVP, UVP, OCP and OTP fault protection. Device and fault configuration parameters are easily defined using the IR Power Designer GUI and stored in on-chip non-volatile memory (NVM). The 3-pin SMBus interface can be used to monitor a variety of operating parameters on up to seven CHL8318-20 based VRs. The controller includes a unique sensorless and lossless input current monitoring capability. PIN DIAGRAM IRTN1 ISEN1 BASIC APPLICATION CHL8318-20 supports three NTC temperature sensors to report temperature and trigger VR HOT and OTP faults. Digital thermal balancing allows proportional current imbalance between phases. ISEN7 SMBus interface for configuring and monitoring; SMBus commands include monitoring input current and power IRTN7 SMBus Fault Indicators: OVP, UVP, OCP, OTP ISEN6 Enables Thermal Phase Balancing The CHL8318-20 deploys a number of efficiency shaping features such as variable MOSFET gate drive versus load, programmable PSI modes for optimum light-load along with programmable phase shedding to autonomously add/drop phases versus load. IRTN6 Designed for use with coupled inductors ISEN5 Adaptive Transient Algorithm minimizes capacitors ISEN4 1-phase to 4-phase PSI for Light Loads The IR CHL8318-20 includes a customized set of digital over-clocking features which require no external components. Gaming applications can use the SMBus interface to place the VRD into “Gamer Mode” to extend VID up to 2.3V with 6.25 mV resolution. IRTN5 IR Efficiency Shaping features a Variable Gate Drive and Dynamic Phase Control ISEN3 Customized Digital Over-Clocking features an easy-to-use SMBus Gamer command and a Gamer VID control up to 2.3V, Gamer Vmax, VID Override or Track, Digital Load-Line Adjust, Gamer OC/OVP, Gamer OFF pin and Gamer OTP IRTN4 Programmable 1-phase to 8-phase operation The CHL8318-20 is an 8-phase digital synchronous buck ® controller for core regulation of high-performance Intel VR11.1 and VR11.0 platforms. The CHL8318-20 is fully compliant with VR11.1 including Power Status Indicator (PSI) and for improved light load efficiency and accurate current output (IMON). IRTN3 Intel VR11.x compliant Digital PWM Controller IRTN2 ISEN2 FEATURES CHL8318-20 56 55 54 53 52 51 50 49 48 47 46 45 44 43 RCSP 1 42 IRTN8 RCSM 2 41 ISEN8 VCC 3 40 VCPU 4 39 VCC PWM8 VRTN 5 38 PWM7 SADDR/ GAMER_OFF 6 37 PWM6 IMON RRES 7 36 PWM5 35 PWM4 VINSEN 9 34 TSEN1 10 TSEN2 11 32 PWM3 PWM2 PWM1 TSEN3 12 31 NC EN 13 14 30 29 VCC V18A CHL8318-20 56 Pin 8mmx8mm QFN TOP VIEW 8 33 GND VAR_GATE Figure 1: CHL8318-20 Basic Application Circuit 1 September28, 2011 | FINAL | V1.02 VR_HOT VR_READY VID0 VID1 VID2 VID3 VID4 VID5 VID6 SCL PSI# VID7 SDA SALERT# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 2: CHL8318-20 Package Top View Digital Multi-Phase Buck Controller CHL8318-20 ORDERING INFORMATION CHL8318-20- Package QFN Tape & Reel Qty 3000 Part Number 1 CHL8318-20-00CRT QFN 3000 CHL8318-20-xxCRT T – Tape and Reel ISEN7 IRTN7 ISEN6 IRTN6 ISEN3 IRTN4 IRTN3 IRTN2 ISEN2 IRTN1 ISEN1 ISEN5 2. “xx” indicates customer specific configuration file. IRTN5 XX-Configuration File ID ISEN4 C – Operating Temperature (Commercial Standard) Notes: 1. For unprogrammed/default parts, use configuration file 00. Unprogrammed parts will not start up until programmed in order to ensure a safe power up. R – Package Type (DFN) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 RCSP 1 42 IRTN8 RCSM 2 41 ISEN8 VCC 3 40 VCPU 4 39 VCC PWM8 38 PWM7 37 PWM6 36 PWM5 35 PWM4 34 VRTN 5 SADDR/ GAMER_OFF 6 IMON RRES 7 VINSEN 9 TSEN1 10 TSEN2 11 32 PWM3 PWM2 PWM1 TSEN3 12 31 NC EN 13 VCC V18A 14 30 29 CHL8318-20 56 Pin 8mmx8mm QFN TOP VIEW 8 33 GND Figure 3: CHL8318-20 Top View Enlarged September28, 2011 | FINAL | V1.02 VR_HOT VR_READY VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SCL PSI# SDA SALERT# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2 2 VAR_GATE