CL7192E CL7192S Laser Processed Logic Device Family Key Features u Laser Processed Logic Device (LPLD) technology offers the ultimate combination of performance, flexibility, and low cost u Functionally, architecturally, and electrically compatible with industry-standard Altera® MAX® 7000 u High Density - 3,700 Usable gates - 192 Macrocells - 152 Maximum user I/O pins u Laser fuse technology provides very fast, dense interconnect routing u Low current consumption u Supports 3.3 volt or 5.0 volt I/O operation u Alpha particle immune CL7000 Product Family Overview Parameter Useable Gates Macrocells Logic Blocks Max user I/O pins Speed Grades Packages CL7128E CL7128S CL7160E CL7160S CL7192E CL7192S CL7256E CL7256S 2,500 3,200 3,750 5,000 128 160 192 256 8 10 12 16 100 104 124 164 -5, -6, -7, -10, -12, -15, -20 -5, -6, -7, -10, -12, -15, -20 -6, -7, -10, -12, -15, -20 -6, -7, -10, -12, -15, -20 84-pin PLCC 100-pin TQFP 84-pin PLCC 100-pin TQFP 160-pin PQFP 160-pin PQFP 208-pin PQFP 100-pin PQFP 160-pin PQFP 100-pin PQFP 160-pin PQFP 208-pin RQFP 7K tbl 01B December 2000 Page 1 CL7192E and CL7192S Laser Processed Logic Devices Description The Clear Logic CL7000 Laser Processed Logic Device (LPLD®) family offers the ultimate combination of performance, flexibility, and cost. This family is a system level second source to Altera MAX® 7000, 7000E, and 7000S products. For designs not requiring in-system reprogrammability, design verification can be performed using the programmable Altera devices, and Clear Logic LPLDs can be used for low cost, high volume production. Clear Logics innovative laser-based technology eliminates NRE costs, test vector development, ordering minimums and long lead times. No re-simulation or re-layout is required, as the device uses a cell-based, PLD-like architecture. Clear Logics NoFault® technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. The Clear Logic CL7000 Laser Processed Logic Device family is based upon a large array of macrocells. Each macrocell contains a logic array with five product terms, a product-term select matrix, and a configurable register. A group of sixteen macrocells forms a block. Laser-configured metal fuses implement logical functions and control signal routing. Laser configuration provides reduced cost and enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Additional Information For further information on designing with the CL7000 LPLD family, please consult the following documents: u AN-01: Requesting a First Article. This document provides instructions on how to submit a bitstream file for generation of first articles. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL7000 family. u AN-09: CL7000 Technology White Paper. This document outlines the technologies employed by the CL7000 LPLD family. u AN-10: Calculating CL7000 Power Consumption. This document provides guidelines for calculating power consumption based on design characteristics. u AN-11: CL7000 Test Methodology. This document discribes how Clear Logic provides 100% stuck-at fault coverage. Page 2 CL7192E and CL7192S Laser Processed Logic Devices u AN-12: CL7000 LPLD Timing and Function Compatability. This document shows how a seamless conversion from CPLD to ASIC can be achieve with no additional engineering with Clear Logic. Page 3 CL7192E and CL7192S Laser Processed Logic Devices Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 to 16 6 to 16 I/O Pins I/O Control Block 6 to 16 6 Output Enables Block B Block A Macrocells 1 - 16 36 36 I/O Control Block 6 to 16 Macrocells 33 - 48 Block D 36 36 Macrocells 65 - 80 36 6 to 16 6 to 16 6 to 16 Block G Macrocells 97 - 112 36 16 6 to 16 6 6 to 16 Macrocells 129 - 144 36 Macrocells 81 - 96 6 to 16 6 to 16 I/O Control Block 6 to 16 6 Block H 36 Macrocells 113 - 128 6 to 16 6 to 16 I/O Control Block 6 to 16 I/O Pins 16 6 to 16 36 36 Macrocells 145 - 160 6 to 16 6 to 16 I/O Control Block 6 to 16 I/O PIns 16 6 to 16 6 6 to 16 6 to 16 Block L Block K Macrocells 161 - 176 36 16 6 to 16 36 Macrocells 177 - 192 6 to 16 6 to 16 I/O Control Block 16 6 to 16 7192 drw 01 Page 4 6 to 16 I/O Pins 16 Block J 6 to 16 6 I/O Control Block Block F Block I 16 6 to 16 I/O Pins 6 to 16 I/O Pins 6 6 to 16 I/O Control Block Laser-Configured Interconnect Array (LIA) 6 to 16 6 6 to 16 I/O Pins I/O Control Block 6 to 16 Block E 16 I/O Control Block 6 to 16 6 6 to 16 6 to 16 I/O Pins Macrocells 49 - 64 6 to 16 16 6 to 16 6 I/O Control Block 6 to 16 I/O Pins 6 Block C 16 6 to 16 I/O Pins I/O Control Block 6 to 16 6 to 16 6 to 16 6 to 16 I/O Pins 6 to 16 16 16 6 Macrocells 17 - 32 6 to 16 6 to 16 I/O PIns CL7192E and CL7192S Laser Processed Logic Devices Macrocell Diagram Global Global Clear Clocks Local Array Fast Input Select 2 Configurable Register Parallel Logic Expanders Register Bypass D Clock/ Enable Select Product Term Select Matrix Clear Select PRN to I/O Control Block Q ENA CLRN VCC to LIA Shared Logic Expanders 36 Signals from LIA from I/O pin 7K drw 01 16 Expander Product Terms Pin Configuration Pin Name 160 pin PQFP INPUT/GCLK1 139 INPUT/GCLRn 141 INPUT/OE1 140 INPUT/OE2/GCLK2 142 TDI 146 TMS 23 TCK 98 TDO 135 GND 3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 126, 138, 143, 148 VCCINT 56, 65, 137, 144 VCCIO 10, 25, 40, 55, 74, 89, 103, 118, 133, 155 NC (No Connect) Total user I/O pins 1, 11, 39, 54, 67, 82, 110, 120 120 7192 tbl 01 Page 5 CL7192E and CL7192S Laser Processed Logic Devices DC Electrical Specifications Recommended Operating Conditions Symbol VCCINT VCCIO VI VO TA TJ tR tF tRVCC Parameter Conditions Supply voltage, internal logic and input buffers Commercial Grade Devices Industrial Grade Devices DC input voltage 5.0 volt commercial 5.0 volt industrial 3.3 volt operation Input voltage Output voltage Operating temperature Commercial temperature range Industrial temperature range Junction Operating temperature Commercial temperature range Industrial temperature range Input signal rise time Input signal fall time Min Max Unit 4.75 4.50 5.25 5.50 V V 4.75 4.50 3.00 -0.5 5.25 5.50 3.60 VCCINT+0.5 V V V V 0 VCCIO V 0 -40 70 85 °C °C 0 -40 90 105 40 40 °C °C ns ns 100 ms VCC rise time 7K tbl 02 Absolute Maximum Ratings Symbol VCC VI Parameter Supply voltage DC input voltage [1] Conditions Min Max Unit With respect to ground -2.0 7.0 V With respect to ground -2.0 7.0 V -25 25 mA IOUT DC output current, per pin TSTG Storage temperature No bias -65 150 °C TAMB Ambient temperature Under bias -65 135 °C TJ Junction temperature Under bias 135 °C 7K tbl 03 Page 6 CL7192E and CL7192S Laser Processed Logic Devices DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter VIH High-level input Voltage VIL Input LOW Voltage Conditions [1] Min Max Unit 2.0 VCCINT + 0.5 V -0.5 0.8 V 5.0-V high-level TTL output Voltage IOH = -4 mA DC, VCCIO = 4.75 V 2.4 V 3.3-V high-level TTL output Voltage IOH = -4 mA DC, VCCIO = 3.00 V 2.4 V 3.3-V high-level CMOS output Voltage IOH = -0.1 mA DC, VCCIO = 3.0 V VCCIO-0.2 V 5.0-V high-level TTL output Voltage IOL = 12 mA DC, VCCIO = 4.75 V 0.45 V 3.3-V high-level TTL output Voltage IOL = 12 mA DC, VCCIO = 3.00 V 0.45 V 3.3-V high-level CMOS output Voltage IOL = 0.1 mA DC, VCCIO = 3.0 V 0.2 V IIN Input Leakage Current VI = VCC or GND -10 10 µA IOZ Output Leakage Current VO = VCC or GND -40 40 µA VOH VOL 7K tbl 04 Capacitance Symbol Parameter Conditions C IN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 10 pF VOUT = 0 V, f = 1.0 MHz 10 pF 7K tbl 05 Page 7 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter Conditions Speed: -6 Min Max Speed: -7 Min Max Speed: -10 Min Max Unit tPD1 Input to non-registered output C L = 35 pF 6.0 7.5 10.0 ns tPD2 I/O input to non-registered output C L = 35 pF 6.0 7.5 10.0 ns tSU Global clock setup time 4.2 4.1 7.0 ns tH Global clock hold time -0.8 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.5 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 3.0 4.0 ns tCL Global clock low time 3.0 3.0 4.0 ns tASU Array clock setup time 1.9 1.0 2.0 ns tAH Array clock hold time 1.5 1.8 3.0 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 3.0 4.0 ns tACL Array clock low time 3.0 3.0 4.0 ns tODH Output data hold time after clock 1.0 1.0 1.0 ns tCNT Minimum global clock period fCNT Max. internal global clock frequency tACNT Minimum array clock period fACNT Max. internal array clock frequency C L = 35 pF 1.0 C L = 35 pF C L = 35 pF 3.7 4.7 6.0 7.8 6.9 144.9 10.0 8.0 125.0 6.9 144.9 5.0 10.0 100.0 8.0 125.0 ns ns MHz 10.0 100.0 ns ns MHz 7K tbl 06D1 Page 8 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications cont. External Timing Parameters Symbol Parameter Speed: -12P Conditions Min Max Speed: -12 Min Max Unit tPD1 Input to non-registered output C L = 35 pF 12.0 12.0 ns tPD2 I/O input to non-registered output C L = 35 pF 12.0 12.0 ns tSU Global clock setup time 7.0 10.0 ns tH Global clock hold time 0.0 0.0 ns tFSU Global clock setup time of fast input 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 4.0 4.0 ns tCL Global clock low time 4.0 4.0 ns tASU Array clock setup time 3.0 4.0 ns tAH Array clock hold time 4.0 4.0 ns tACO1 Array clock to output delay tACH Array clock high time 5.0 5.0 ns tACL Array clock low time 5.0 5.0 ns tODH Output data hold time after clock 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period fACNT Maximum internal array clock frequency C L = 35 pF 6.0 C L = 35 pF C L = 35 pF 6.0 12.0 12.0 11.0 90.9 11.0 90.9 11.0 90.9 ns ns MHz 11.0 90.9 ns ns MHz 7K tbl 06D2 Page 9 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications cont. External Timing Parameters Symbol Parameter Speed: -15 Conditions Min Max Speed: -20 Min Max Unit tPD1 Input to non-registered output C L = 35 pF 15.0 20.0 ns tPD2 I/O input to non-registered output C L = 35 pF 15.0 20.0 ns tSU Global clock setup time 11.0 12.0 ns tH Global clock hold time 0.0 0.0 ns tFSU Global clock setup time of fast input 3.0 5.0 ns tFH Global clock hold time of fast input 0.0 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 5.0 6.0 ns tCL Global clock low time 5.0 6.0 ns tASU Array clock setup time 4.0 5.0 ns tAH Array clock hold time 4.0 5.0 ns tACO1 Array clock to output delay tACH Array clock high time 6.0 8.0 ns tACL Array clock low time 6.0 8.0 ns tODH Output data hold time after clock 1.0 1.0 ns tCNT Minimum global clock period fCNT Maximum internal global clock frequency tACNT Minimum array clock period fACNT Maximum internal array clock frequency C L = 35 pF 8.0 C L = 35 pF C L = 35 pF 12.0 15.0 20.0 13.0 76.9 16.0 62.5 13.0 76.9 ns ns MHz 16.0 62.5 ns ns MHz 7K tbl 06D3 Page 10 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Conditions Speed: -6 Min Max Speed: -7 Min Max Speed: -10 Min Max Unit tiN Input pad and buffer delay 0.6 0.3 0.5 ns tIO I/O input pad and buffer delay 0.6 0.3 0.5 ns tFIN Fast input delay 2.7 3.2 1.0 ns tSEXP Shared expander delay 2.5 4.2 5.0 ns tPEXP Parallel expander delay 0.7 1.2 0.8 ns tLAD Logic array delay 2.4 3.1 5.0 ns tLAC Logic control array delay 2.4 3.1 5.0 ns tIOE Internal output enable delay 0.0 0.9 2.0 ns C L = 35 pF 0.4 0.5 1.5 ns C L = 35 pF 0.9 1.0 2.0 ns C L = 35 pF 5.4 5.5 5.5 ns C L = 35 pF 4.0 4.0 5.0 ns C L = 35 pF 4.5 4.5 5.5 ns C L = 35 pF 9.0 9.0 9.0 ns C L = 5 pF[3] 4.0 4.0 5.0 ns tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tXZ Output buffer disable delay tSU Register setup time 1.9 1.1 2.0 ns tH Register hold time 1.5 1.7 3.0 ns tFSU Register setup time of fast input 0.8 2.3 3.0 ns tFH Register hold time of fast input 1.7 0.7 0.5 ns tRD Register delay 1.7 1.4 2.0 ns tCOMB Combinatorial delay 1.7 1.2 2.0 ns tIC Array clock delay 2.4 3.2 5.0 ns tEN Register enable time 2.4 3.1 5.0 ns tGLOB Global control delay 1.0 2.5 1.0 ns tPRE Register preset time 3.1 2.7 3.0 ns tCLR Register clear time 3.1 2.7 3.0 ns tLIA LIA delay 1.0 2.4 1.0 ns 7K tbl 07D1 Page 11 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Speed: -12P Conditions Min Max Speed: -12 Min Max Unit tiN Input pad and buffer delay 1.0 2.0 ns tIO I/O input pad and buffer delay 1.0 2.0 ns tFIN Fast input delay 1.0 1.0 ns tSEXP Shared expander delay 7.0 7.0 ns tPEXP Parallel expander delay 1.0 1.0 ns tLAD Logic array delay 7.0 5.0 ns tLAC Logic control array delay 5.0 5.0 ns tIOE Internal output enable delay 2.0 2.0 ns C L = 35 pF 1.0 3.0 ns C L = 35 pF 2.0 4.0 ns C L = 35 pF 5.0 7.0 ns C L = 35 pF 6.0 6.0 ns C L = 35 pF 7.0 7.0 ns C L = 35 pF 10.0 10.0 ns 6.0 6.0 ns tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V [3] tXZ Output buffer disable delay C L = 5 pF tSU Register setup time 1.0 4.0 ns tH Register hold time 6.0 4.0 ns tFSU Register setup time of fast input 4.0 2.0 ns tFH Register hold time of fast input 0.0 2.0 ns tRD Register delay 2.0 1.0 ns tCOMB Combinatorial delay 2.0 1.0 ns tIC Array clock delay 5.0 5.0 ns tEN Register enable time 7.0 5.0 ns tGLOB Global control delay 2.0 0.0 ns tPRE Register preset time 4.0 3.0 ns tCLR Register clear time 4.0 3.0 ns tLIA LIA delay 1.0 1.0 ns 7K tbl 07D2 Page 12 CL7192E and CL7192S Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Speed: -15 Conditions Min Max Speed: -20 Min Max Unit tiN Input pad and buffer delay 2.0 3.0 ns tIO I/O input pad and buffer delay 2.0 3.0 ns tFIN Fast input delay 2.0 4.0 ns tSEXP Shared expander delay 8.0 9.0 ns tPEXP Parallel expander delay 1.0 2.0 ns tLAD Logic array delay 6.0 8.0 ns tLAC Logic control array delay 6.0 8.0 ns tIOE Internal output enable delay 3.0 4.0 ns C L = 35 pF 4.0 5.0 ns C L = 35 pF 5.0 6.0 ns C L = 35 pF 7.0 9.0 ns C L = 35 pF 6.0 10.0 ns C L = 35 pF 7.0 11.0 ns C L = 35 pF 10.0 14.0 ns 6.0 10.0 ns tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V [3] tXZ Output buffer disable delay C L = 5 pF tSU Register setup time 4.0 4.0 ns tH Register hold time 4.0 5.0 ns tFSU Register setup time of fast input 2.0 4.0 ns tFH Register hold time of fast input 1.0 3.0 ns tRD Register delay 1.0 1.0 ns tCOMB Combinatorial delay 1.0 1.0 ns tIC Array clock delay 6.0 8.0 ns tEN Register enable time 6.0 8.0 ns tGLOB Global control delay 1.0 3.0 ns tPRE Register preset time 4.0 4.0 ns tCLR Register clear time 4.0 4.0 ns tLIA LIA delay 2.0 3.0 ns 7K tbl 07D3 Page 13 CL7192E and CL7192S Laser Processed Logic Devices AC Test Conditions (A) VCCIO (B) 464 Ω VCCIO OUTPUT Includes jig capacitance All Input Pulses 464 Ω 3.0V 90% 90% OUTPUT 35 pF 250 Ω Includes jig capacitance 5 pF 250 Ω GND 10% 10% ≤ 3ns ≤ 3ns 7K drw 02A Notes to Tables 1. During transitions, inputs may undershoot to -2.0V for periods shorter than 20ns. Otherwise, minimum DC input voltage is 0.3V. 2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC. 3. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 4. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. Revision History Page 14 11 Jan. 1999: Created new document 30 Apr. 1999: Recompiled databook, no changes. 31 July 1999: Added -6ns speed grade, revised Product Family Overview 13 Oct. 1999: Corrected typographical error in AC Test Condition diagram (W changed to W) 1 Dec. 2000: Updated application note reference. CL7192E and CL7192S Laser Processed Logic Devices Ordering Information Part Number CL7192EQC160-20 Temperature Range Commercial Package Type 160-pin Plastic QFP Speed Altera Equivalent -20 EPM7192EQC-160-20 CL7192EQC160-15 -15 EPM7192EQC-160-15 CL7192EQC160-12 -12 EPM7192EQC-160-12 CL7192EQC160-12P CL7192EQC160-6 CL7192EQI160-20 Industrial CL7192SQC160-15 Commercial -12 PCI EPM7192EQC-160-12P -6 N/A -20 EPM7192EQI-160-20 -15 EPM7192SQC160-15 CL7192SQC160-10 -10 EPM7192SQC160-10 CL7192SQC160-7 -7 EPM7192SQC160-7 CL7192SQC160-6 -6 CL7192SQI160-10 Industrial 160-pin Plastic QFP -10 N/A EPM7192SQI160-10 7192 tbl 02 Page 15 CL7192E and CL7192S Laser Processed Logic Devices Page 16