CL7256A CL7256AE Link Processed Logic Device Family Key Features u Patented High Fidelity Conversion Technology u Link Processed Logic Device (LPLD®) technology offers the ultimate combination of performance, flexibility, and low cost u Functionally, architecturally, and electrically compatible with industry-standard Altera® MAX® 7000 u High Density - 5,000 Usable gates - 256 Macrocells - 164 Maximum user I/O pins u Metal Link technology provides very fast, dense interconnect routing u Low current consumption u Supports 3.3 volt operation u Alpha particle immune CL7000 Product Family Overview CL7128A CL7128AE CL7256A CL7256AE CL7512AE 2,500 5,000 10,000 128 256 512 Logic array Blocks 8 16 32 Max user I/O pins 100 164 212 -4, -5, -6, -7, -10, -12 -4, -5, -6, -7, -10, -12 -6, -7, -10, -12 84-Pin PLCC 100-Pin TQFP 100-Pin TQFP 100-Pin BGA 144-Pin TQFP 208-Pin PQFP 100-Pin BGA 144-Pin TQFP 256-Pin BGA 144-Pin TQFP 208-Pin PQFP 256-Pin FBGA Feature Useable Gates Macrocells Speed Grades Packages 256-Pin BGA 7KA tbl 01A December 2000 Page 77 CL7256A and CL7256AE Laser Processed Logic Devices Description The Clear Logic CL7000 Laser Processed Logic Device (LPLD®) family offers the ultimate combination of performance, flexibility, and cost. This family is a system level second source to Altera MAX® 7000A products. For designs not requiring insystem reprogrammability, design verification can be performed using the programmable Altera devices, and Clear Logic LPLDs can be used for low cost, high volume production. Clear Logic’s innovative laser-based technology eliminates NRE costs, test vector development, ordering minimums and long lead times. No re-simulation or re-layout is required, as the device uses a cell-based, PLD-like architecture. Clear Logic’s NoFault® technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. The Clear Logic CL7000 Laser Processed Logic Device family is based upon a large array of macrocells. Each macrocell contains a logic array with five product terms, a product-term select matrix, and a configurable register. A group of sixteen macrocells forms a block. Laser-configured metal fuses implement logical functions and control signal routing. Laser configuration provides reduced cost and enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Additional Information For further information on designing with the CL7000 LPLD family, please consult the following documents: u AN-01: Requesting a First Article. This document provides instructions on how to submit a bitstream file for generation of first articles. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL7000 family. u AN-09: CL7000 Technology White Paper. This document outlines the technologies employed by the CL7000 LPLD family. u AN-10: Calculating CL7000 Power Consumption. This document provides guidelines for calculating power consumption based on design characteristics. u AN-11: CL7000 Test Methodology. This document describes how Clear Logic provides 100% stuck-at fault coverage. Page 78 CL7256A and CL7256AE Laser Processed Logic Devices u AN-12: CL7000 LPLD Timing and Function Compatibility. This document shows how a seamless conversion from CPLD to ASIC can be achieve with no additional engineering with Clear Logic. Page 79 CL7256A and CL7256AE Laser Processed Logic Devices Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn 6 Output Enables 6 to 16 6 to 16 I/O Pins I/O Control Block 6 to 16 6 Output Enables Block A Block B 36 36 Macrocells 1 - 16 Macrocells 17 - 32 6 to 16 6 to 16 6 to 16 6 to 16 6 6 6 to 16 I/O Control Block 6 to 16 Block C Block D 36 36 Macrocells 33 - 48 Macrocells 49 - 64 6 to 16 6 to 16 6 6 to 16 6 to 16 Block E Block F 36 36 Macrocells 65 - 80 6 to 16 I/O Control Block 6 to 16 Block G 36 Macrocells 97 - 112 16 6 to 16 6 6 to 16 6 to 16 I/O Pins I/O Control Block 6 to 16 Block I Macrocells 129 - 144 36 16 6 to 16 Laser-Configured Interconnect Array (LIA) 6 to 16 6 Macrocells 81 - 96 6 to 16 6 to 16 6 Block H 36 Macrocells 113 - 128 6 to 16 6 to 16 6 to 16 6 Block J 36 Macrocells 145 - 160 6 to 16 6 to 16 6 to 16 I/O 6 to 16 Macrocells 161 - 176 36 36 Macrocells 177 - 192 6 to 16 6 to 16 I/O Control Block 6 to 16 I/O Pins 16 6 to 16 6 6 to 16 6 to 16 Block M Macrocells 193 - 208 Block N 36 16 6 to 16 36 Macrocells 209 - 224 6 to 16 6 to 16 I/O Control Block 6 to 16 I/O Pins 16 6 to 16 6 6 6 to 16 I/O 6 to 16 Control Block Block P Block O Macrocells 225 - 240 36 16 6 to 16 36 Macrocells 241 - 256 6 to 16 6 to 16 I/O Control Block 6 to 16 I/O PIns 16 6 to 16 7256A drw 01 Page 80 Pins 6 to 16 Block L 6 to 16 6 to 16 I/O Pins I/O Control Block 16 6 I/O Control Block 6 to 16 I/O Pins 16 Block K 16 6 to 16 I/O Pins I/O Control Block 6 6 to 16 I/O Control Block 6 to 16 I/O Pins 6 to 16 6 6 to 16 I/O Pins I/O Control Block 16 16 6 to 16 I/O Pins 6 to 16 I/O Pins 6 to 16 6 to 16 6 I/O Control Block I/O Control Block 16 16 6 to 16 I/O Pins 6 to 16 I/O Pins 16 16 6 to 16 I/O Pins I/O Control Block CL7256A and CL7256AE Laser Processed Logic Devices Macrocell Diagram Global Global Clear Clocks Local Array Fast Input Select 2 Configurable Register Parallel Logic Expanders Register Bypass D Clock/ Enable Select Product Term Select Matrix Clear Select Shared Logic Expanders 36 Signals from LIA from I/O pin PRN to I/O Control Block Q ENA CLRN VCC to LIA 7K drw 01 16 Expander Product Terms Page 81 CL7256A and CL7256AE Laser Processed Logic Devices Pin Configuration Pin Name 100 pin TQFP 100 pin FBGA 144 pin TQFP 208 pin PQFP 256 pin FBGA INPUT/GCLK1 87 A6 125 184 D9 INPUT/GCLRn 89 B5 127 182 E8 INPUT/OE1 88 B6 126 183 E9 INPUT/OE2/GCLK2 90 A5 128 181 D8 TDI 4 A1 4 176 D4 TMS 15 F3 20 127 J6 TCK 62 F8 89 30 J11 TDO 73 A10 104 189 D13 38, 86 D6, G5 52, 57, 124, 129 75, 82, 180, 185 A8, C9, G9, K8, P9 A3, B10, C2, D14, F6, G10, H8, J9, K7, L11, M3, P6, P10, R2, R3, T1, T15 B9, C8, G8, K9, P8 GNDINT GND VCCINT VCCIO NC (No Connect) Total user I/O pins 11, 26, 43, 59, 74, 95 C3, D7, E5, F6, G4, H8 3, 13, 17, 33, 59, 64, 85, 105, 135 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 39, 91 D5, G6 51, 58, 123, 130 74, 83, 179, 186 3, 18, 34, 51, 66, 82 C8, D4, E6, F5, G7, H3 B3, B5, C14, E15, 5, 23, 41, 63, 85, F11, G3, G7, G15, 24, 50, 73, 76, 95, 107, 125, 143, 165, H9, J8, K10, L3, 115, 144 191 L6, M15, P14, T2, T3 - - - 84 84 120 A1, A2, A6, A12, A13, A14, A15, A16, B1, B2, B15, B16, C1, C15, C16, D1, 1, 2, 51, 52, 53, 54, D3, D15, D16, G1, 103, 104, 105, 106, G16, H15, H16, J1, 155, 156, 157, 158, K1, L1, L2, M1, 207, 208 M16, N1, N2, N14, N15, N16, P1, P2, P15, P16, R1, R14, R15, R16, T7, T8, T10, T11, T14, T16 164 164 7256A tbl 01 Page 82 CL7256A and CL7256AE Laser Processed Logic Devices DC Electrical Specifications Recommended Operating Conditions Symbol Parameter Min Max Unit VCCINT VCCIO Supply voltage, internal logic and input buffers 3.0 3.6 V Supply voltage for output drivers 3.3 volt operation 2.5 volt operation Input voltage 3.0 2.3 -0.5 3.6 2.7 5.75 V V V 0 VCCIO V 0 -40 70 85 °C °C 0 -40 90 105 40 40 °C °C ns ns 100 ms VI VO TA TJ tR tF tRVCC Conditions Output voltage Ambient Operating temperature Commercial temperature range Industrial temperature range Ambient Operating temperature Commercial temperature range Industrial temperature range Input signal rise time Input signal fall time VCC rise time 7KA tbl 02 Absolute Maximum Ratings Symbol VCC VI Parameter Conditions Min Max Unit Supply voltage With respect to ground -0.5 4.6 V DC input voltage[1] With respect to ground -2.0 5.8 V -25 25 mA IOUT DC output current, per pin TSTG Storage temperature No bias -65 150 °C TA Ambient temperature Under bias -65 135 °C TJ Junction temperature Fineline BGA, PQFP, and TPFP packages, Under bias 135 °C 7KA tbl 03 Page 83 CL7256A and CL7256AE Laser Processed Logic Devices DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter VIH High-level input Voltage VIL Input LOW Voltage Conditions [1] 3.3-V high-level TTL output Voltage IOH = -8 mA DC, VCCIO = 3.00 V 2.5-V high-level output Voltage 3.3-V high-level TTL output Voltage Max Unit 1.7 5.75 V -0.5 0.8 V 2.4 V VCCIO-0.2 V IOH = -100 µA DC, VCCIO = 2.30 V 2.1 V IOH = -1 mA DC, VCCIO = 2.30 V 2.0 IOH = -2 mA DC, VCCIO = 2.30 V 1.7 3.3-V high-level CMOS output Voltage IOH = -0.1 mA DC, VCCIO = 3.00 V VOH Min 0.45 V 3.3-V high-level CMOS output Voltage IOH = 0.1 mA DC, VCCIO = 3.00 V 0.2 V IOH = 100 µA DC, VCCIO = 2.30 V 0.2 V IOH = 1 mA DC, VCCIO = 2.30 V 0.4 V IOH = 2 mA DC, VCCIO = 2.30 V 0.7 V VOL 2.5-V high-level output Voltage IOH = 8 mA DC, VCCIO = 3.00 V IIN Input Leakage Current VI = VCC or GND -10 10 µA IOZ Output Leakage Current VO = VCC or GND -10 10 µA 7KA tbl 04 Capacitance Symbol Parameter Conditions CIN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 8 pF VOUT = 0 V, f = 1.0 MHz 8 pF 7KA tbl 05 Page 84 CL7256A and CL7256AE Laser Processed Logic Devices AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter Conditions Speed: -4 Min Max Speed: -5 Min Max Speed: -6 Min Max Unit tPD1 Input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns tPD2 I/O input to non-registered output CL = 35 pF 4.5 5.0 6.0 ns tSU Global clock setup time 3.0 3.2 3.7 ns tH Global clock hold time 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 2.5 2.5 2.5 ns tFH Global clock hold time of fast input 0.0 0.0 0.5 ns tCO1 Global clock to output delay tCH Global clock high time 2.0 2.0 3.0 ns tCL Global clock low time 2.0 2.0 3.0 ns tASU Array clock setup time 1.4 1.0 0.8 ns tAH Array clock hold time 0.8 0.8 1.9 ns tACO1 Array clock to output delay tACH Array clock high time 2.0 2.0 3.0 ns tACL Array clock low time 2.0 2.0 3.0 ns tCNT Minimum global clock period fCNT Max. internal global clock frequency tACNT Minimum array clock period fACNT Max. internal array clock frequency CL = 35 pF 1.0 CL = 35 pF 2.8 1.0 4.4 5.2 5.2 192.3 1.0 1.0 5.5 181.8 5.2 192.3 3.0 6.2 6.4 156.3 5.5 181.8 3.3 ns ns MHz 6.4 156.3 ns ns MHz 7KA tbl 06A1 Page 85 CL7256A and CL7256AE Laser Processed Logic Devices AC Electrical Specifications cont. External Timing Parameters Symbol Parameter Speed: -7 Conditions Min Max Speed: -10 Min Max Speed: -12 Min Max Unit tPD1 Input to non-registered output CL = 35 pF 7.5 10.0 12.0 ns tPD2 I/O input to non-registered output CL = 35 pF 7.5 10.0 12.0 ns tSU Global clock setup time 4.9 6.6 7.8 ns tH Global clock hold time 0.0 0.0 0.0 ns tFSU Global clock setup time of fast input 3.0 3.0 3.0 ns tFH Global clock hold time of fast input 0.0 0.0 0.0 ns tCO1 Global clock to output delay tCH Global clock high time 3.0 4.0 5.0 ns tCL Global clock low time 3.0 4.0 5.0 ns tASU Array clock setup time 1.6 2.1 2.4 ns tAH Array clock hold time 2.1 3.4 4.4 ns tACO1 Array clock to output delay tACH Array clock high time 3.0 4.0 5.0 ns tACL Array clock low time 3.0 4.0 5.0 ns tCNT Minimum global clock period fCNT Max. internal global clock frequency tACNT Minimum array clock period fACNT Max. internal array clock frequency CL = 35 pF 1.0 CL = 35 pF 4.5 1.0 7.8 89.3 13.3 75.2 11.2 89.3 7.1 12.5 11.2 8.4 119.0 1.0 10.4 8.4 119.0 5.9 ns ns MHz 13.3 75.2 ns ns MHz 7KA tbl 06A2 Page 86 CL7256A and CL7256AE Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Speed: -7 Conditions Min Max Speed: -10 Min Max Speed: -12 Min Max tiN Input pad and buffer delay 0.4 0.6 0.7 tIO I/O input pad and buffer delay 0.4 0.6 0.7 tFIN Fast input delay 3.3 3.7 4.1 tSEXP Shared expander delay 3.6 4.9 5.9 tPEXP Parallel expander delay 0.8 1.1 1.3 tLAD Logic array delay 3.7 5.0 6.0 tLAC Logic control array delay 3.4 4.6 5.6 tIOE Internal output enable delay 0.0 0.0 0.0 CL = 35 pF 0.6 0.7 0.9 CL = 35 pF 1.1 1.2 0.4 CL = 35 pF 5.6 5.7 5.9 CL = 35 pF 4.0 5.0 5.0 CL = 35 pF 4.5 5.5 5.5 CL = 35 pF 9.0 10.0 10.0 CL = 5 pF[3] 4.0 5.0 5.0 tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tXZ Output buffer disable delay tSU Register setup time 1.3 1.7 2.0 tH Register hold time 2.4 3.8 4.8 tFSU Register setup time of fast input 1.1 1.1 1.1 tFH Register hold time of fast input 1.9 1.9 1.9 tRD Register delay 2.1 2.8 3.3 tCOMB Combinatorial delay 1.5 2.0 2.4 tIC Array clock delay 3.4 4.6 5.6 tEN Register enable time 3.4 4.6 5.6 tGLOB Global control delay 1.4 1.8 2.2 tPRE Register preset time 3.9 5.2 6.2 tCLR Register clear time 3.9 5.2 6.2 Page 87 CL7256A and CL7256AE Laser Processed Logic Devices AC Electrical Specifications cont. Internal Timing Parameters[4] Symbol Parameter Conditions Speed: -7 Min Max Speed: -10 Min Max Speed: -12 Min Max Unit tiN Input pad and buffer delay 0.4 0.6 0.7 ns tIO I/O input pad and buffer delay 0.4 0.6 0.7 ns tFIN Fast input delay 3.3 3.7 4.1 ns tSEXP Shared expander delay 3.6 4.9 5.9 ns tPEXP Parallel expander delay 0.8 1.1 1.3 ns tLAD Logic array delay 3.7 5.0 6.0 ns tLAC Logic control array delay 3.4 4.6 5.6 ns tIOE Internal output enable delay 0.0 0.0 0.0 ns CL = 35 pF 0.6 0.7 0.9 ns CL = 35 pF 1.1 1.2 0.4 ns CL = 35 pF 5.6 5.7 5.9 ns CL = 35 pF 4.0 5.0 5.0 ns CL = 35 pF 4.5 5.5 5.5 ns CL = 35 pF 9.0 10.0 10.0 ns CL = 5 pF[3] 4.0 5.0 5.0 ns tOD1 tOD2 Output buffer and pad delay Slow slew rate = off, VCCIO = 5.0 V Output buffer and pad delay Slow slew rate = off, VCCIO = 3.3 V Output buffer and pad delay tOD3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tZX1 tZX2 Output buffer enable delay Slow slew rate = off, VCCIO = 5.0 V Output buffer enable delay Slow slew rate = off, VCCIO = 3.3 V Output buffer enable delay tZX3 Slow slew rate = on, VCCIO = 5.0 V or 3.3 V tXZ Output buffer disable delay tSU Register setup time 1.3 1.7 2.0 ns tH Register hold time 2.4 3.8 4.8 ns tFSU Register setup time of fast input 1.1 1.1 1.1 ns tFH Register hold time of fast input 1.9 1.9 1.9 ns tRD Register delay 2.1 2.8 3.3 ns tCOMB Combinatorial delay 1.5 2.0 2.4 ns tIC Array clock delay 3.4 4.6 5.6 ns tEN Register enable time 3.4 4.6 5.6 ns tGLOB Global control delay 1.4 1.8 2.2 ns tPRE Register preset time 3.9 5.2 6.2 ns tCLR Register clear time 3.9 5.2 6.2 ns tLIA LIA delay 1.3 1.7 2.0 ns 7KA tbl 07A2 Page 88 CL7256A and CL7256AE Laser Processed Logic Devices AC Test Conditions (A) (B) 464 Ω VCCIO VCCIO OUTPUT Includes jig capacitance All Input Pulses 464 Ω 3.0V 90% 90% OUTPUT 35 pF 250 Ω Includes jig capacitance 5 pF 250 Ω GND 10% 10% ≤ 3ns ≤ 3ns 7K drw 02A Notes to Tables 1. During transitions, inputs may undershoot to -2.0V for periods shorter than 20ns. Otherwise, minimum DC input voltage is 0.3V. 2. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC. 3. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 4. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. Revision History 11 Jan. 1999: Created preliminary document. 31 July 1999: Created full document. 13 Oct. 1999: Corrected typographical error in AC Test Condition diagram (W changed to Ω) also corrected timing in 10ns External Timing Paramiters 1 Dec. 2000: Updated application note reference. Page 89 CL7256A and CL7256AE Laser Processed Logic Devices Ordering Information Part Number CL7256ATC100-12 Temperature Range Commercial Package Type Altera Equivalent -12 EPM7256ATC100-12 CL7256ATC100-10 -10 EPM7256ATC100-10 CL7256ATC100-7 -7 EPM7256ATC100-7 CL7256ATC100-6 -6 N/A CL7256ATC100-5 -5 N/A CL7256ATC100-4 -4 N/A CL7256ATC144-12 100-pin Thin QFP Speed 144-pin Thin QFP -12 EPM7256ATC144-12 CL7256ATC144-10 -10 EPM7256ATC144-10 CL7256ATC144-7 -7 EPM7256ATC144-7 CL7256ATC144-6 -6 N/A CL7256ATC144-5 -5 N/A CL7256ATC144-4 -4 N/A CL7256ATI144-10 Industrial -10 EPM7256ATI144-10 CL7256AQC208-12 Commercial -12 EPM7256AQC208-12 CL7256AQC208-10 -10 EPM7256AQC208-10 CL7256AQC208-7 -7 EPM7256AQC208-7 CL7256AQC208-6 -6 N/A CL7256AQC208-5 -5 N/A CL7256AQC208-4 -4 N/A CL7256AQI208-10 Industrial CL7256AFC256-12 Commercial 208-pin Plastic QFP -10 EPM7256AQI208-10 -12 EPM7256AFC256-12 CL7256AFC256-10 -10 EPM7256AFC256-10 CL7256AFC256-7 -7 EPM7256AFC256-7 CL7256AFC256-6 -6 N/A CL7256AFC256-5 -5 N/A CL7256AFC256-4 -4 N/A CL7256AFI256-10 Industrial 256-pin FBGA -10 EPM7256AFI256-10 7256A tbl 02B Page 90 CL7256A and CL7256AE Laser Processed Logic Devices Ordering Information (cont.) Part Number CL7256AETC100-10 Temperature Range Commercial Package Type Altera Equivalent -10 EPM7256AETC100-10 CL7256AETC100-7 -7 EPM7256AETC100-7 CL7256AETC100-6 -6 EPM7256AETC100-6 CL7256AETC100-5 -5 EPM7256AETC100-5 CL7256AETC100-4 -4 CL7256AETI100-7 Industrial CL7256AEFC100-10 Commercial 100-pin Thin QFP Speed -7 EPM7256AETI100-7 -10 EPM7256AEFC100-10 CL7256AEFC100-7 -7 EPM7256AEFC100-7 CL7256AEFC100-6 -6 EPM7256AEFC100-6 CL7256AEFC100-5 -5 EPM7256AEFC100-5 CL7256AEFC100-4 -4 CL7256AETC144-10 100-pin FBGA N/A 144-pin Thin QFP N/A -10 EPM7256AETC144-10 CL7256AETC144-7 -7 EPM7256AETC144-7 CL7256AETC144-6 -6 EPM7256AETC144-6 CL7256AETC144-5 -5 EPM7256AETC144-5 CL7256AETC144-4 -4 CL7256AETI144-7 Industrial CL7256AEQC208-10 Commercial N/A EPM7256AETI144-7 -10 EPM7256AEQC208-10 CL7256AEQC208-7 -7 EPM7256AEQC208-7 CL7256AEQC208-6 -6 EPM7256AEQC208-6 CL7256AEQC208-5 -5 EPM7256AEQC208-5 CL7256AEQC208-4 -4 CL7256AEQI208-7 Industrial CL7256AEFC256-10 Commercial 208-pin Plastic QFP -7 EPM7256AEQI208-7 -10 EPM7256AEFC256-10 CL7256AEFC256-7 -7 EPM7256AEFC256-7 CL7256AEFC256-6 -6 EPM7256AEFC256-6 CL7256AEFC256-5 -5 EPM7256AEFC256-5 CL7256AEFC256-4 -4 N/A -7 EPM7256AEFI256-7 CL7256AEFI256-7 Industrial 256-pin FBGA N/A 7256A tbl 02B Page 91 CL7256A and CL7256AE Laser Processed Logic Devices Page 92