CPC7591 Line Card Access Switch Features Description • • • • • The CPC7591 is a member of Clare’s next generation Line Card Access Switch (LCAS) family. This monolithic 4-pole solid state switch is available in either a 16-pin SOIC or a 16-pin DFN package. It provides the necessary functions to replace the 2-Form-C electromechanical ringing relay and it’s associated snubber circuitry on traditional analog line cards or contemporary integrated voice and data (IVD) line cards found in Central Office (CO), Access, and PBX equipment. Because this device contains solid state switches for tip and ring line break and for ringing injection/return, it requires only a +5 V supply for operation and TTL logic-level inputs for control. The CPC7591 provides stable start-up conditioning during system power up and for hot plug insertion applications. Once active, the inputs respond to traditional TTL logic levels, enabling the CPC7591 to be used with 3.3V-only logic. • • • • • • • • • TTL logic level inputs for 3.3V logic interfaces Smart logic for power up / hot plug state control Improved switch dv/dt immunity of 500 V/μs Small 16-pin SOIC or 16-pin DFN package DFN package printed-circuit board footprint is 60 percent smaller than the SOIC version, 40 percent smaller than fourth generation EMR solutions. Monolithic IC reliability Low, matched RON Eliminates the need for zero-cross switching Flexible switch timing for transition from ringing mode to idle/talk mode. Clean, bounce-free switching Tertiary protection consisting of integrated current limiting, voltage clamping, and thermal shutdown for SLIC protection 5 V operation with power consumption < 10 mW Intelligent battery monitor Latched logic-level inputs, no external drive circuitry For negative transient voltage protection the CPC7591xA versions include SCRs to provide voltage fold-back protection for the SLIC and subsequent circuitry, while the CPC7591xB versions utilize clamping diodes to the VBAT pin. For positive transient voltage protection all versions provide clamping diodes to the FGND pin. Applications • • • • • • • • • VoIP Gateways Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Pb RoHS 2002/95/EC Ordering Information CPC7591 part numbers are specified as shown here: B - 16-pin SOIC delivered 50/Tube, 1000/Reel M - 16-pin DFN delivered 52/Tube, 1000/Reel CPC7591 x x xx e3 TR - Add for Tape & Reel Version A - With Protection SCR B - Without Protection SCR Figure 1. CPC7591 Block Diagram +5 Vdc 6 TRINGING TLINE Tip 3 X 7 VDD CPC7591 SW3 2 TBAT X SW1 Secondary Protection Ring SLIC 15 RBAT SW2 RLINE 14 X X SW4 VREF 12 RRINGING 300Ω (min.) VBAT 1 FGND SCR Trip Circuit (CPC7591xA) 16 VBAT L A T C H Switch Control Logic 9 DGND 10 11 INRINGING LATCH 8 TSD RINGING DS-CPC7591 - R05 www.clare.com 1 CPC7591 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Switch Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.3 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Voltage and Power Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 4 5 5 6 7 8 8 9 9 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Under Voltage Switch Lock Out Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Hot Plug and Power Up Circuit Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Switch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Make-Before-Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.4 Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 TSD Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 11 11 11 11 11 12 12 13 13 13 13 14 14 14 14 15 3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 16-Pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 16 16 17 17 17 18 18 18 19 19 19 19 2 www.clare.com R05 CPC7591 1. Specifications 1.1 Package Pinout 1.2 Pinout CPC7591 FGND 1 16 VBAT Pin Name TBAT 2 15 RBAT 1 FGND Fault ground. TLINE 3 14 RLINE 2 TBAT Tip lead to the SLIC. 3 TLINE Tip lead of the line side. NC 4 13 NC 4 NC No connection. NC 5 12 RRINGING 5 NC No connection. TRINGING 6 11 LATCH VDD 7 10 INRINGING TSD 8 9 DGND 6 TRINGING Ringing generator return. 7 VDD +5 V supply. 8 TSD Temperature shutdown pin. 9 DGND 10 11 12 R05 Description Digital ground. INRINGING Logic control input. LATCH Data latch enable control input. RRINGING Ringing generator source. 13 NC 14 RLINE Ring lead of the line side. 15 RBAT Ring lead to the SLIC. 16 VBAT Battery supply. www.clare.com No connection. 3 CPC7591 1.3 Absolute Maximum Ratings Parameter +5 V power supply (VDD) 1.4 ESD Rating Minimum Maximum Unit ESD Rating (Human Body Model) 1000 V -0.3 7 V Battery Supply - -85 V DGND to FGND Separation -5 +5 V -0.3 VDD + 0.3 V Logic input to switch output isolation - 320 V Switch open-contact isolation (SW1, SW2, SW3) - 320 V Switch open-contact isolation (SW4) - 465 V Logic input voltage Operating relative humidity 1.5 General Conditions Unless otherwise specified, minimum and maximum values are guaranteed by production testing requirements. Typical values are characteristic of the device at +25°C and are the result of engineering evaluations. They are provided for information purposes only and are not part of the manufacturing testing requirements. 5 95 % Operating temperature -40 +110 °C Storage temperature -40 +150 °C Absolute maximum electrical ratings are at 25°C. Specifications cover the operating temperature range TA = -40°C to +85°C. Also, unless otherwise specified all testing is performed with VDD = 5Vdc, logic low input voltage is 0Vdc and logic high voltage is 5Vdc. Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 4 www.clare.com R05 CPC7591 1.6 Switch Specifications 1.6.1 Break Switches, SW1 and SW2 Parameter Test Conditions Symbol Minimum Typical Maximum Unit 1 μA VSW1 (differential) = TLINE to TBAT VSW2 (differential) = RLINE to RBAT All-Off state. Off-State Leakage Current +25° C, VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85° C, VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V 0.1 ISW - -40° C, VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.3 0.1 ISW(on) = ±10 mA, ±40 mA, RBAT and TBAT = -2 V On Resistance 14.5 - 20.5 28 10.5 - - 0.15 0.8 - 300 80 160 - 400 425 - 2.5 - A - 0.1 - 0.3 1 μA - 0.1 - 500 - V/μs +25° C RON +85° C - -40° C On Resistance Matching Per SW1 & SW2 On Resistance test conditions. ΔRON Ω Ω VSW(on) = ±10V DC current limit +25° C ISW +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Break switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW - mA Logic Inputs = GND Logic input to switch output isolation +25° C, VSW (TLINE, RLINE) = ±320 V +85° C, VSW (TLINE, RLINE) = ±330 V ISW -40° C, VSW (TLINE, RLINE) = ±310 V dv/dt sensitivity R05 100VPP Square Wave, 100Hz (Not production tested - limits are guaranteed by design and quality control sampling audits.) - www.clare.com 5 CPC7591 1.6.2 Ringing Return Switch, SW3 Parameter Test Conditions Symbol Minimum Typical Maximum Unit 1 μA VSW3 (differential) = TLINE to TRINGING All-Off state. Off-State Leakage Current +25° C, VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85° C, VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V 0.1 ISW - -40° C, VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.3 0.1 ISW(on) = ±0 mA, ±10 mA On Resistance +25° C RON +85° C - -40° C 60 - 85 100 45 - Ω VSW (on) = ± 10 V DC current limit +25° C ISW +85° C -40° C Dynamic current limit (t ≤ 0.5 μs) Ringing switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW - 135 70 85 - 210 - 2.5 - mA - A 1 μA - V/μs Logic inputs = GND Logic input to switch output isolation +25° C, VSW (TRINGING, TLINE) = ±320V +85° C, VSW (TRINGING, TLINE) = ±330V 0.1 ISW - -40° C, VSW (TRINGING, TLINE) = ±310 V dv/dt sensitivity 6 100VPP Square Wave, 100Hz (Not production tested - limits are guaranteed by design and quality control sampling audits.) 0.3 0.1 - www.clare.com - 500 R05 CPC7591 1.6.3 Ringing Switch, SW4 Parameter Test Conditions Symbol Minimum Typical Maximum Unit 1 μA VSW4 (differential) = RLINE to RRINGING All-Off state. Off-State Leakage Current +25° C VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V 0.05 +85° C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V ISW - -40° C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V 0.1 0.05 On Resistance ISW (on) = ±70 mA, ±80 mA RON - 10 15 Ω On Voltage ISW (on) = ± 1 mA VON - 1.5 3 V On-State Leakage Current Inputs set for ringing -Measure ringing generator current to ground. IRINGING - 0.1 0.25 mA Steady-State Current* Inputs set for ringing mode. ISW - - 150 mA Surge Current* Ringing switches on, all other switches off. Apply ±1 kV 10x1000 μs pulse with appropriate protection in place. ISW - - 2 A Release Current SW4 transition from on to off. IRINGING - 300 - μA 1 μA - V/μs Logic inputs = GND Logic input to switch output isolation +25° C, VSW (RRINGING, RLINE) = ±320V +85° C, VSW (RRINGING, RLINE) = ±330V 0.1 ISW - -40° CVSW (RRINGING, RLINE) = ±310 V dv/dt sensitivity 100VPP Square Wave, 100Hz (Not production tested - limits are guaranteed by design and quality control sampling audits.) 0.3 0.1 - - 500 *Secondary protection and current limiting must prevent exceeding this parameter. R05 www.clare.com 7 CPC7591 1.7 Digital I/O Electrical Specifications Parameter Test Conditions Symbol Minimum Typical Input voltage, Logic low Input voltage falling VIL 0.8 1.1 Input voltage, Logic high Input voltage rising VIH Maximum Unit Input Characteristics 1.7 2.0 V Input leakage current, INRINGING, Logic high VDD = 5.5 V, VBAT = -75 V, VHI = 2.4V IIH - 0.1 1 μA Input leakage current, INRINGING, Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL - 0.1 1 μA Input leakage current, LATCH Logic high VDD = 4.5 V, VBAT = -75 V, VIH = 2.4V IIH 7 19 - μA LATCH Pull-up Minimum Load VDD = 4.5 V, VBAT = -75 V, IIN = -10 μA Latch input transitions to logic high. Logic = High True Input leakage current, LATCH Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL - 46 125 μA Input leakage current, TSD Logic high VDD = 5.5 V, VBAT = -75 V, VIH = 2.4 IIH 10 16 30 μA Input leakage current, TSD Logic low VDD = 5.5 V, VBAT = -75 V, VIL = 0.4V IIL 10 16 30 μA Output Characteristics Output voltage, TSD Logic high VDD = 5.5 V, VBAT = -75 V, ITSD = 10μA VTSD_off 2.4 VDD - V Output voltage, TSD Logic low VDD = 5.5 V, VBAT = -75 V, ITSD = 1mA VTSD_on - 0 0.4 V Test Conditions Symbol Minimum Typical Maximum Unit VDD - VDD 4.5 5.0 5.5 V VBAT1 - VBAT -19 -48 -72 V 1.8 Voltage and Power Specifications Parameter Voltage Requirements 1 VBAT is used only for internal protection circuitry. If VBAT goes more positive than -10 V, the device will enter the all-off state, and will remain in the all-off state until the battery goes more negative than -15 V Power Specifications Power consumption VDD = 5 V, VBAT = -48 V, Measure IDD and IBAT, Talk and All-Off states P - 5.5 10.5 mW Ringing state P - 6.5 10.5 mW Talk and All-Off states IDD - 1.1 2.0 mA Ringing state IDD - 1.3 2.0 mA VDD = 5V, VBAT = -48 V, All states IBAT - 0.1 10 μA VDD = 5 V, VBAT = -48 V VDD current VBAT current 8 www.clare.com R05 CPC7591 1.9 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum - 2.1 3.0 Unit Protection Diode Bridge Forward Voltage drop, continuous current (50/60 Hz) Apply ± dc current limit of break switches VF Forward Voltage drop, surge current Apply ± dynamic current limit of break switches VF - 5 - - - - * A ITRIG - - mA - mA V Protection SCR (CPC7591xA) Surge current - Trigger current: Current into VBAT pin. SCR activates, +25° C SCR activates, +85° C SCR remains active, +25° C Hold current: Current through protection SCR SCR remains active, +85° C Gate trigger voltage Reverse leakage current VBAT = -48 V 0.5 A, t = 0.5 μs On-state voltage 2.0 A, t = 0.5 μs 45 - 195 110 130 VTBAT or VRBAT VBAT -4 - VBAT -2 V IVBAT - 0.2 1.0 μA VTBAT or VRBAT - - V TTSD_on 110 125 150 °C TTSD_off 10 - 25 °C IHOLD IGATE = ITRIGGER§ 65 -3 -5 Temperature Shutdown Specifications Shutdown activation temperature Shutdown circuit hysteresis Not production tested - limits are guaranteed by design and Quality Control sampling audits. *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. §V BAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 1.10 Truth Table 1 R05 State INRINGING Talk 0 Latch 0 Ringing 1 Latched X 1 All-Off X X TSD Z 1 Break Switches Ringing Switches On Off Off On Unchanged 0 Off Off Z = High Impedance. Because TSD has an internal pull up at this pin, it should be controlled with an open-collector or open-drain type device. www.clare.com 9 CPC7591 2. Functional Description 2.1 Introduction The CPC7591 has three states: • Talk. Line break switches SW1 and SW2 closed, ringing switches SW3 and SW4 open. • Ringing. Ringing switches SW3 and SW4 closed, line break switches SW1 and SW2 open. • All-off. All switches open. See “Truth Table” on page 9 for more information. The CPC7591 offers break-before-make and make-before-break switching from the ringing state to the talk state with simple TTL level logic input control. Solid-state switch construction means no impulse noise is generated when switching during ringing cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via TTL logic-level input so no additional driver circuitry is required. The linear line break switches SW1 and SW2 have exceptionally low RON and excellent matching characteristics. The ringing switch, SW4, has a minimum open contact breakdown voltage of 465 V at +25°C, sufficiently high with proper protection to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator). Integrated into the CPC7591 is an over-voltage clamping circuit, active current limiting, and a thermal shutdown mechanism to provide protection to the SLIC during a fault condition. Positive and negative lightning surge currents are reduced by the current limiting circuitry and hazardous potentials are diverted away from the SLIC via the protection diode bridge or the optional integrated protection SCR. Power-cross potentials are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7591 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the TLINE and RLINE terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is highly recommended. With proper selection of the secondary protector, a line card using the CPC7591 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. 10 The CPC7591 operates from a single +5 V supply only. This gives the device extremely low idle and active power consumption with virtually any range of battery voltage. The battery voltage used by the CPC7591 has a two fold function. For protection purposes it is used as a fault condition current source for the internal integrated protection circuitry. Secondly, it is used as a reference so that in the event of battery voltage loss, the CPC7591 will enter the all-off state. 2.2 Under Voltage Switch Lock Out Circuitry 2.2.1 Introduction Smart logic in the CPC7591 now provides for switch state control during both power up and power loss transitions. An internal detector is used to evaluate the VDD supply to determine when to de-assert the under voltage switch lock out circuitry with a rising VDD and when to assert the under voltage switch lock out circuitry with a falling VDD. Any time unsatisfactory low VDD conditions exist, the lock out circuit overrides user switch control by blocking the information at the external input pins and conditioning internal switch commands to the all-off state. Upon restoration of VDD, the switches will remain in the all-off state until the LATCH input is pulled low. The rising VDD switch lock-out release threshold is internally set to ensure all internal logic is properly biased and functional before accepting external switch commands from the inputs to control the switch states. For a falling VDD event, the lock-out threshold is set to assure proper logic and switch behavior up to the moment the switches are forced off and external inputs are suppressed. To facilitate hot plug insertion and system power up state control, the LATCH pin has an integrated weak pull up resistor to the VDD power rail that will hold a non-driven LATCH pin at a logic high state. This enables board designers to use the CPC7591 with FPGAs and other devices that provide high impedance outputs during power up and logic configuration. The weak pull up allows a fan out of up to 32 when the system’s LATCH control driver has a logic low minimum sink capability of 4mA. www.clare.com R05 CPC7591 2.3 Switch Logic 2.2.2 Hot Plug and Power Up Circuit Design Considerations 2.3.1 Start-up There are six possible start up scenarios that can occur during power up. They are: 1. 2. 3. 4. 5. 6. All inputs defined at power up & LATCH = 0 All inputs defined at power up & LATCH = 1 All inputs defined at power up & LATCH = Z All inputs not defined at power up & LATCH = 0 All inputs not defined at power up & LATCH = 1 All inputs not defined at power up & LATCH = Z Under all of the start up situations listed above the CPC7591 will hold all of it’s switches in the all-off state during power up. When VDD requirements have been satisfied the LCAS will complete it’s start up procedure in one of three conditions. For start up scenario 1 the CPC7591 will transition from the all-off state to the state defined by the inputs when VDD is valid. For start up scenarios 2, 3, 5, and 6 the CPC7591 will power up in the all-off state and remain there until the LATCH pin is pulled low. This allows for an indefinite all-off state for boards inserted into a powered system but are not configured for service or boards that need to wait for other devices to be configured first. Start up scenario 4 will start up with all switches in the all-off state but upon the acceptance of a valid VDD the LCAS will revert to either the talk state or the ringing state and there after may randomly change states based on input pin leakage currents and loading. Because the LCAS state after power up can not be predicted with this start up condition it should never be utilized. On designs that do not wish to individually control the LATCH pins of multiple-port cards it is possible to bus many (or all) of the LATCH pins together to create a single board level input enable control. R05 The CPC7591 uses smart logic to monitor the VDD supply. Any time the VDD is below an internally set threshold, the smart logic places the control logic to the all-off state. An internal pullup on the LATCH pin locks the CPC7591 in the all-off state following start-up until the LATCH pin is pulled down to a logic low. Prior to the assertion of a logic low at the LATCH pin, the switch control inputs must be properly conditioned. 2.3.2 Switch Timing The CPC7591 provides, when switching from the ringing state to the talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the break switches SW1 and SW2 using simple TTL logic-level inputs. The two available techniques are referred to as make-before-break and break-before-make operation. When the switch contacts of SW1 and SW2 are closed (made) before the ringing switch contacts of SW3 and SW4 are opened (broken), this is referred to as make-before-break operation. Break-before-make operation occurs when the ringing contacts of SW3 and SW4 are opened (broken) before the switch contacts of SW1 and SW2 are closed (made). With the CPC7591, make-before-break and break-before-make operations can easily be accomplished by applying the proper sequence of TTL logic-level inputs to the device. 2.3.3 Make-Before-Break Operation To use make-before-break operation, change the logic inputs from the ringing state directly to the talk state. Application of the talk state opens the ringing return switch, SW3, as the break switches SW1 and SW2 close. The ringing switch, SW4, remains closed until the next zero-crossing of the ringing current. While in the make-before-break state, ringing potentials in excess of the CPC7591 protection circuitry thresholds will be diverted away from the SLIC. This operational sequence is shown below in the “Make-Before-Break Ringing to Talk Transition Logic Sequence” on page 12. www.clare.com 11 CPC7591 Make-Before-Break Ringing to Talk Transition Logic Sequence Timing Ringing Return Switch (SW3) Ringing Switch (SW4) State INRINGING Ringing 1 - Off On On MakeBeforeBreak 0 SW4 waiting for next zero-current crossing to turn off. Maximum time is one-half of the ringing cycle. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. On Off On Talk 0 Zero-cross current has occurred On Off Off Latch 0 TSD Break Switches Z 2.3.4 Break-Before-Make Operation Break-before-make ringing switch release timing is performed via the bidirectional TSD interface. As an input, the TSD can disable all of the CPC7591 switches when pulled to a logic low. Although logically disabled, an active (closed) ringing switch (SW4) will remain closed until the next current zero crossing event. This operational sequence is shown below in the “Break-Before-Make Ringing to Talk Transition Logic Sequence” on page 12. 1. Pull TSD to a logic low to end the ringing state. This opens the ringing return switch (SW3) and prevents any other switches from closing. 2. Keep TSD low for at least one-half the duration of the ringing cycle period to allow sufficient time for a zero crossing current event to occur and for the circuit to enter the break before make state. 3. During the TSD low period, clear the INRINGING input for the talk state (logic low). 4. Release TSD allowing the internal pull-up to activate the break switches. When using TSD as an input, the two recommended states are “0” which overrides the logic input pins and forces an all-off state and “Z” which allows normal switch control via the logic input pins. This requires the use of an open-collector or open-drain type buffer. Break-Before-Make Ringing to Talk Transition Logic Sequence State INRINGING Ringing 1 All-off 1 All-off 0 Talk 0 Latch TSD 0 Ringing Return Switch (SW3) Ringing Switch (SW4) - Off On On Hold this state for one-half of the ringing cycle. SW4 waiting for zero current to turn off. Off Off On Zero current has occurred. SW4 has opened Off Off Off Close break switches On Off Off Z 0 Timing Break Switches Z Logic states and explanations are provided in the “Truth Table” on page 9. 2.4 Data Latch The CPC7591 has an integrated transparent data latch. The latch enable operation is controlled by TTL logic input levels at the LATCH pin. Data input to the latch is via the input pin INRINGING, while the output of the data latch are internal nodes used for state control. 12 When the LATCH enable control pin is at logic 0 the data latch is transparent and the INRINGING input data control signal flows directly through the data latch to the state control circuitry. A change in INRINGING input will be reflected by a change in switch state. www.clare.com R05 CPC7591 Whenever the LATCH enable control pin is at logic 1, the data latch is active and data is locked. Subsequent INRINGING input changes will not result in a change to the control logic or affect the existing switch state. The switches will remain in the state they were in when the LATCH pin changes from logic 0 to logic 1 and will not respond to changes in input as long as the LATCH is at logic 1. However, neither the TSD input nor the TSD output control functions are affected by the latch function. Since internal thermal shutdown control and external “All-off” control is not affected by the state of the LATCH enable input, TSD will override state control. 2.5 TSD Pin Description The TSD pin is a bi-directional I/O structure with an internal pull-up current source with a nominal value of 16 μA biased from VDD. As an output, this pin indicates the status of the thermal shutdown circuitry. Typically, during normal operation, this pin will be pulled up to VDD but under fault conditions that create excess thermal loading the CPC7591 will enter thermal shutdown and a logic low will be output. As an input, the TSD pin is utilized to place the CPC7591 into the “All-Off” state by simply pulling the input low. For applications using low-voltage logic devices (lower than VDD), Clare recommends the use of an open-collector or an open-drain type output to control TSD. This avoids sinking the TSD pull up bias current to ground during normal operation when the all-off state is not required. In general, Clare recommends all applications use an open-collector or open-drain type device to drive this pin. 2.6 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for R05 more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zero-cross switching scheme. A minimum impedance of 300 Ω in series with the ringing generator is recommended. 2.7 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7591. Switch state control is powered exclusively by the +5 V supply. As a result, the CPC7591 exhibits extremely low power consumption during active and idle states. Although battery power is not used for switch control, it is required to supply trigger current for the integrated internal protection circuitry SCR during fault conditions. This integrated SCR is designed to activate whenever the voltage at TBAT or RBAT drops 2 to 4 V below the applied voltage on the VBAT pin. Because the battery supply at this pin is required to source trigger current during negative overvoltage fault conditions at tip and ring, it is important that the net supplying this current be a low impedance path for high speed transients such as lightning. This will permit trigger currents to flow enabling the SCR to activate and thereby prevent a fault induced negative overvoltage event at the TBAT or RBAT nodes. 2.8 Battery Voltage Monitor The CPC7591 also uses the VBAT pin to monitor battery voltage. If system battery voltage is lost, the CPC7591 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the system battery voltage goes more positive than –10 V, and remains in the all-off state until the battery voltage goes more negative than –15 V. This battery monitor feature draws a small current from the battery (less than 1 μA typical) and will add slightly to the device’s overall power dissipation. This monitor function performs properly if the CPC7591 and SLIC share a common battery supply origin. Otherwise, if battery is lost to the CPC7591 but not to the SLIC, then the VBAT pin will be internally biased by the potential applied at the TBAT or RBAT pins via the internal protection circuitry SCR trigger current path. www.clare.com 13 CPC7591 2.9 Protection 2.9.1 Diode Bridge/SCR The CPC7591 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the voltage source at VBAT, the SCR conducts and faults are shunted to FGND via the SCR or the diode bridge. In order for the SCR to crowbar (or foldback), the SCR’s on-voltage (see “Protection Circuitry Electrical Specifications” on page 9) must be less than the applied voltage at the VBAT pin. If the VBAT voltage is less negative than the SCR on-voltage, or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current is directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the VBAT reference voltage by two to four volts, steering the fault current to ground. Note: The CPC7591xB does not contain the protection SCR but instead uses diodes to clamp both polarities of a transient fault. These diodes direct the negative potential’s fault current to the VBAT pin. 2.9.2 Current Limiting function If a lightning strike transient occurs when the device is in the talk state, the current is passed along the line to the integrated protection circuitry and restricted by the dynamic current limit response of the active switches. During the talk state when a 1000V 10x1000 μs lightning pulse (GR-1089-CORE) is applied to the line though a properly clamped external protector, the current seen at TLINE or RLINE will be a pulse with a typical magnitude of 2.5 A and a duration less than 0.5 μs. 14 If a power-cross fault occurs with the device in the talk state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit but is limited by the dynamic DC current limit response of the two break switches. The DC current limit specified over temperature is between 80 mA and 425 mA and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a power cross fault condition, the measured current into TLINE or RLINE will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will enter the all-off state. 2.10 Thermal Shutdown The thermal shutdown mechanism activates when the device die temperature reaches a minimum of 110° C, placing the device in the all-off state regardless of logic input. During thermal shutdown events the TSD pin will output a logic low with a nominal 0 V level. A logic high is output from the TSD pin during normal operation with a typical output level equal to VDD. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise and the thermal shutdown mechanism will activate forcing the switches to the all-off state. At this point the current measured into TLINE or RLINE will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the de-activation level of the thermal shutdown circuit. This permits the device to autonomously return to normal operation. If the transient has not passed, current will again flow up to the value allowed by the dynamic DC current limiting of the switches and heating will resume, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector will activate shunting the fault current to ground. www.clare.com R05 CPC7591 2.11 External Protection Elements The CPC7591 requires only over voltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for additional external protection on the SLIC side. The secondary protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7591. A foldback or crowbar type protector is recommended to minimize stresses on the CPC7591. Consult Clare’s application note, AN-100, “Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces” for equations related to the specifications of external secondary protectors, fused resistors and PTCs. R05 www.clare.com 15 CPC7591 3. Manufacturing Information 3.1 Mechanical Dimensions 3.1.1 16-Pin SOIC NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). 10.211 ± 0.254 (0.402 ± 0.010) PIN 16 10.312 ± 0.381 (0.406 ± 0.015) 7.493 ± 0.127 (0.295 ± 0.005) DIMENSIONS mm (inches) PIN 1 1.270 TYP (0.050 TYP) 0.406 ± 0.076 (0.016 ± 0.003) 2.337 ± 0.051 (0.092 ± 0.002) 0.649 ± 0.102 (0.026 ± 0.004) 0.254 MIN / 0.737 MAX X 45° (0.010 MIN / 0.029 MAX X 45°) 2.540 ± 0.152 (0.100 ± 0.006) 0.203 ± 0.102 (0.008 ± 0.004) 0.889 ± 0.178 (0.035 ± 0.007) 0.2311 MIN / 0.3175 MAX (0.0091 MIN / 0.0125 MAX) 3.1.2 16-Pin DFN 7.00 ± 0.25 (0.276 ± 0.01) 6.00 ± 0.25 (0.236 ± 0.01) INDEX AREA TOP VIEW 0.90 ± 0.10 (0.035 ± 0.004) 0.02, + 0.03, - 0.02 (0.0008, + 0.0012, - 0.0008) 1 SIDE VIEW 0.30 ± 0.05 (0.012 ± 0.002) SEATING PLANE 0.20 (0.008) EXPOSED METALLIC PAD 4.25 ± 0.05 (0.167 ± 0.002) Terminal Tip 0.80 (0.032) 16 16 6.00 ± 0.05 (0 236 ± 0 002) www.clare.com 0.55 ± 0.10 (0 022 ± 0 004) R05 CPC7591 3.2 Printed-Circuit Board Layout 3.2.1 16-Pin SOIC 3.2.2 16-Pin DFN 1.27 (0.050) 0.35 (0.014) 1.05 (0.041) 5.80 (0.228) 9.40 (0.370) 2.00 (0.079) 0.80 (0.031) 0.60 (0.024) DIMENSIONS mm (inches) DIMENSIONS mm (inches) NOTE: As the metallic pad on the bottom of the DFN package is connected to the substrate of the die, Clare recommends that no printed circuit board traces or vias be placed under this area to prevent unintentional shorts. R05 www.clare.com 17 CPC7591 3.3 Tape and Reel Packaging 3.3.1 16-Pin SOIC 330.2 Dia (13.00 Dia) B0=10.70 + 0.15 (0.421 + 0.01) Pin 1 Top Cover Tape Thickness 0.102 Max (0.004 Max) W=16.00 + 0.30 (0.630 + 0.010) Top Cover Tape K0=3.20 + 0.15 (0.193 + 0.01) P=12.00 (0.47) K1=2.70 + 0.15 (0.106 + 0.01) Embossed Carrier A0=10.90 + 0.15 (0.429 + 0.010) Dimensions mm (inches) User Direction of Feed NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 Embossment 3.3.2 16-Pin DFN B0=7.24 + 0.10 (0.285 + 0.004) 330.2 Dia (13.00 Dia) Pin 1 Top Cover Tape Thickness 0.102 Max (0.004 Max) K0=1.61 + 0.10 (0.063 + 0.004) Embossed Carrier P=12.00 + 0.10 (0.472 + 0.004) A0=6.24 + 0.10 (0.246 + 0.004) User Direction of Feed Embossment 18 W=16.00 + 0.30 (0.630 + 0.012) Dimensions mm (inches) NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2 www.clare.com R05 CPC7591 3.4.2 Reflow Profile 3.4 Soldering 3.4.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity for this product using IPC/JEDEC standard J-STD-020. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard J-STD-033 per the labeled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the DFN package. For proper assembly, this component must be processed in accordance with the current revision of IPC/JEDEC standard J-STD-020. Failure to follow the recommended guidelines may cause permanent damage to the device resulting in impaired performance and/or a reduced lifetime expectancy. 3.5 Washing Clare does not recommend ultrasonic cleaning of this part. Pb RoHS 2002/95/EC e3 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7591-R05 © Copyright 2009, Clare, Inc. All rights reserved. Printed in USA. 10/14/09 R05 www.clare.com 19