CS3301A
Low-noise, Programmable Gain, Differential Amplifier
Features & Desription
Description
z
Signal Bandwidth: DC to 2 kHz
z
Selectable Gain: x1, x2, x4, x8, x16, x32, x64
The CS3301A is a low-noise differential input, differential output amplifier with programmable gain,
optimized for amplifying signals from low-impedance sensors such as geophones. The gain
settings are binary weighted (x1, x2, x4, x8, x16,
x32, x64) and are selected using simple pin settings. Two sets of external inputs, INA and INB,
simplify system design as inputs from a sensor and
test DAC. An internal 800 Ω termination can also be
selected for noise tests.
z
Differential Inputs, Differential Outputs
•
•
•
•
z
Multiplexed inputs: INA, INB, 800Ω termination
Rough / fine outputs for CS5371A / 72A / 73A
Max signal amplitude: 5 Vpp differential
Low input bias: 1 nA typical
Outstanding Noise Performance
• 8.5 nV/ Hz from 0.1 Hz to 2 kHz
• 0.180 µVp-p between 0.1 Hz and 10 Hz
z
Low Total Harmonic Distortion
• -121 dB THD typical (0.0000891%)
• -112 dB THD maximum (0.0002512%)
z
Low Power Consumption
• Normal operation: 5.5 mA typical
• Power down: 10 µA typical
z
Small 24-pin SSOP Package
z
Bipolar Power Supply Configuration
• VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
VA+
INA+
INB+
Amplifier noise performance is outstanding with a
noise density of 8.5 nV/ Hz over the 0.1 Hz to
2 kHz bandwidth. Distortion performance is also extremely good, typically -121 dB THD at x1 gain. Flat
noise down to 0.1 Hz and low total harmonic distortion make this amplifier ideal for low-frequency,
low-amplitude, differential signals requiring maximum dynamic range.
ORDERING INFORMATION
See page 15.
CLK
VD
+
OUTR+
OUTF+
400 Ω
-
GAIN0
GAIN1
GAIN2
400 Ω
MUX0
MUX1
+
VA-
http://www.cirrus.com
OUTFOUTR-
-
INAINB-
PWDN
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
GND
MAR ‘07
DS757F1
CS3301A
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS .............................................................................. 3
SPECIFIED OPERATING CONDITIONS ....................................................................................... 3
ABSOLUTE MAXIMUM RATINGS ................................................................................................. 3
TEMPERATURE CONDITIONS .................................................................................................... 3
ANALOG CHARACTERISTICS ..................................................................................................... 4
DIGITAL CHARACTERISTICS ...................................................................................................... 7
POWER SUPPLY CHARACTERISTICS ........................................................................................ 8
2. GENERAL DESCRIPTION ............................................................................................................. 9
2.1. Analog Signals .......................................................................................................................... 9
2.2.1. Analog Inputs................................................................................................................ 9
2.3.2. Analog Outputs ............................................................................................................. 9
2.4.3. Differential Signals...................................................................................................... 10
2.5. Digital Signals ......................................................................................................................... 10
2.6.1. Clock Input.................................................................................................................. 10
2.7.2. Gain Selection ............................................................................................................ 10
2.8.3. Mux Selection ............................................................................................................. 10
2.9.4. Power Down Selection................................................................................................ 11
2.10.Power Supplies ..................................................................................................................... 11
2.11.1. Analog Power Supplies............................................................................................... 11
2.12.2. Digital Power Supplies................................................................................................ 11
2.13.Connection Diagram.............................................................................................................. 12
3. PIN DESCRIPTION ....................................................................................................................... 13
4. PACKAGE DIMENSIONS ............................................................................................................. 14
5. ORDERING INFORMATION ........................................................................................................ 15
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................................. 15
7. REVISION HISTORY ................................................................................................................... 16
LIST OF FIGURES
Figure 1. CS3301A Noise Performance .......................................................................................... 4
Figure 2. Digital Input Rise and Fall Times ..................................................................................... 7
Figure 3. Multi-Channel System Architecture.................................................................................. 9
Figure 4. Single-Channel System Architecture ............................................................................. 10
Figure 5. CS3301A Amplifier Connections.................................................................................... 12
Figure 6. CS3301A Pin Assignments ............................................................................................ 13
LIST OF TABLES
Table 1. Digital Selections for Gain and Input Mux Control ............................................................ 7
Table 2. Pin Descriptions ............................................................................................................. 13
2
DS757F1
CS3301A
1.
CHARACTERISTICS AND SPECIFICATIONS
•
Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions.
•
Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
•
GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half.
•
Device is connected as shown in Figure 5 on page 12 unless otherwise noted.
SPECIFIED OPERATING CONDITIONS
Parameter
Symbol
Min
Nom
Max
Unit
± 2%
VA+
2.45
2.50
2.55
V
Negative Analog
(Note 1) ± 2%
VA-
-2.55
-2.50
-2.45
V
Positive Digital
(Note 2) ± 3%
VD
3.20
3.30
3.40
V
Industrial (-IS, -ISZ)
TA
-40
25
85
°C
Bipolar Power Supplies
Positive Analog
Thermal
Ambient Operating Temperature
Notes: 1. VA- must be the most negative voltage to avoid potential SCR latch-up conditions.
2. VD must conform to Digital Supply Differential under Absolute Maximum Ratings.
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Power Supplies
Positive Analog
Negative Analog
Digital
Symbol
Min
Max
Parameter
VA+
VAVD
-0.5
-6.8
-0.5
6.8
0.5
6.8
V
V
V
Analog Supply Differential
[(VA+) - (VA-)]
VADIFF
-
6.8
V
Digital Supply Differential
[(VD) - (VA-)]
VDDIFF
-
6.8
V
IPWR
-
±50
mA
Input Current, Power Supplies
(Note 3)
Input Current, Any Pin Except Supplies
(Note 3)
IIN
-
±10
mA
Output Current
(Note 3)
IOUT
-
±25
mA
PD
-
500
mW
VINA
(VA-) - 0.5
(VA+) + 0.5
V
Digital Input Voltages
VIND
-0.5
(VD) + 0.5
V
Storage Temperature Range
TSTG
-65
150
ºC
Power Dissipation
Analog Input Voltages
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 3. Transient currents up to ±100 mA will not cause SCR latch-up.
TEMPERATURE CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
TA
-40
-
85
ºC
Storage Temperature Range
TSTR
-65
-
150
ºC
Allowable Junction Temperature
TJCT
-
-
125
ºC
Junction to Ambient Thermal Impedance
ΘJA
-
65
-
ºC / W
Ambient Operating Temperature
DS757F1
3
CS3301A
ANALOG CHARACTERISTICS
CS3301A
Parameter
Symbol
Min
Typ
Max
Unit
Noise Performance
Input Voltage Noise
f0 = 0.1 Hz to 10 Hz
VNPP
-
0.18
0.40
µVp-p
Input Voltage Noise Density
f0 = 0.1 Hz to 2 kHz
VND
-
8.5
12.0
nV/ Hz
Input Current Noise Density
(Note 4)
IND
-
100
-
fA/ Hz
THD
-
-121
-120
-120
-120
-120
-119
-116
-112
-
dB
LIN
-
0.0000891
0.0001000
0.0001000
0.0001000
0.0001000
0.0001122
0.0001585
0.0002512
-
%
Distortion Performance
Total Harmonic Distortion (Note 5)
x1
x2
x4
x8
x16
x32
x64
Linearity (Note 5)
x1
x2
x4
x8
x16
x32
x64
Notes: 4. Guaranteed by design and/or characterization.
5. Tested with a full scale input signal of 31.25 Hz.
CS3301A In-Band Noise
CS3301A Wide Band Noise
300
Noise Density (nV/rtHz)
Noise Density (nV/rtHz)
20
15
10
5
0
250
200
150
100
50
0
0
200
400
600
800 1000 1200 1400 1600 1800 2000
0.1
1
10
Frequency (Hz)
100
1000
10000 100000 1E+06
Frequency (Hz)
Figure 1. CS3301A Noise Performance
4
DS757F1
CS3301A
ANALOG CHARACTERISTICS (CONT.)
CS3301A
Parameter
Symbol
Min
Typ
Max
GAIN
x1
-
x64
Unit
Gain
Gain, Differential
Gain, Common Mode
(Note 6)
GAINCM
-
x1
-
Gain Accuracy, Absolute
(Note 7)
GAINABS
-
±1
±2
2x
-0.4
-0.2
0
4x
-
-0.2
-
-
-0.2
-
-
-0.2
-
32x
-
-0.3
-
64x
-
-0.3
-
Gain Accuracy, Relative
(Note 8)
8x
16x
Gain Drift
GAINREL
%
%
(Note 4, 9)
GAINTC
-
5
-
ppm / ºC
Offset Voltage, Input Referred
(Note 10)
OFST
-
±5
±15
µV
Offset After Calibration, Absolute
(Note 11) OFSTCAL
(Note 12) OFSTRNG
-
±1
-
µV
-
100
-
% FS
-
0.1
-
µV / ºC
Offset
Offset Calibration Range
Offset Voltage Drift
(Note 4, 9)
OFSTTC
6. Common mode signals pass unchanged through the differential amplifier architecture and are rejected
by the CS5371A / 72A / 73A modulator CMRR.
7. Absolute gain accuracy tests the matching of x1 gain across multiple CS3301A devices.
8. Relative gain accuracy tests the tracking of x2, x4, x8, x16, x32, x64 gain relative to x1 gain on a single
CS3301A device.
9. Specification is for the parameter over the specified temperature range and is for the CS3301A device
only. It does not include the effects of external components.
10. Offset voltage is tested with the amplifier inputs connected to the internal 800 Ω termination.
11. The absolute offset after calibration specification applies to the effective offset voltage of the CS3301A
output when used with the CS5371A / 72A / 73A modulator and CS5376A / 78 digital filter, and is
measured from the digitally calibrated output codes of the digital filter.
12. The CS3301A offset calibration is performed digitally with the CS5371A / 72A / 73A modulator and
CS5376A / 78 digital filter and includes the full scale signal range. Calibration offsets of greater than
± 5% of full scale will begin to subtract from system dynamic range.
DS757F1
5
CS3301A
ANALOG CHARACTERISTICS (CONT.)
CS3301A
Parameter
Symbol
Min
Typ
Max
Unit
BW
DC
-
2000
Hz
VIN
(VA-)+0.7
(VA-)+0.7
-
(VA+)-1.25
(VA+)-1.75
V
VINFS
-
-
5
2.5
1.25
625
312.5
156.25
78.125
Vp-p
Vp-p
Vp-p
mVp-p
mVp-p
mVp-p
mVp-p
Input Impedance, Differential
ZINDIFF
-
1, 50
-
GΩ, pF
Input Impedance, Common Mode
ZINCM
-
1
-
MΩ
IIN
-
1
2
nA
XT
-
-130
-
dB
CDMR
95
120
-
dB
Full Scale Output, Differential
VOUT
-
-
5
Vp-p
Output Voltage Range (Vcm ± Signal)
VRNG
(VA-)+0.5
-
(VA+)-0.5
V
Analog Input Characteristics
Input Signal Frequencies
Input Voltage Range (Vcm ± Signal)
Full Scale Input, Differential
x1
x2 to x64
x1
x2
x4
x8
x16
x32
x64
Input Bias Current
Crosstalk, Multiplexed Inputs
(Note 4)
Common to Differential Mode Rejection (Note 4, 7, 13)
Analog Output Characteristics
Output Impedance
(Note 14)
ZOUT
-
40
-
Ω
Output Impedance Drift
(Note 14)
ZTC
-
0.24
-
Ω/°C
IOUT
-
-
±25
mA
CL
-
-
1
nF
Output Current
Load Capacitance
Notes: 13. Ratio of input common mode amplitude vs. output differential mode amplitude for a perfectly matched
common mode input signal. Characterized with a 50 Hz, 500 mVpeak common mode sine wave applied
to the analog inputs.
14. Output impedance characteristics are approximate and can vary up to ±30% depending on process
parameters.
6
DS757F1
CS3301A
DIGITAL CHARACTERISTICS
CS3301A
Parameter
Symbol
Min
Typ
Max
Unit
Digital Characteristics
High Level Input Drive Voltage
(Note 15)
VIH
0.6*VD
-
VD
V
Low Level Input Drive Voltage
(Note 15)
VIL
0.0
-
0.8
V
Input Leakage Current
IIN
-
±1
±10
µA
Digital Input Capacitance
CIN
-
9
-
pF
Rise Times, Digital Inputs Except CLK
tRISE
-
-
100
ns
Fall Times, Digital Inputs Except CLK
tFALL
-
-
100
ns
fCLK
2.0
2.048
2.2
MHz
Master Clock Duty Cycle
fDTY
40
-
60
%
Master Clock Rise Time
tRISE
-
-
25
ns
Master Clock Fall Time
tFALL
-
-
25
ns
Master Clock Jitter (In-Band or Aliased In-Band)
JTRIB
-
-
300
ps
Master Clock Jitter (Out-of-Band)
JTROB
-
-
1
ns
Master Clock Specifications
Master Clock Frequency
(Note 16)
Notes: 15. Device is intended to be driven with CMOS logic levels.
16. When CLK is tied to GND, an internal oscillator provides a master clock at approximately 2 MHz. CLK
should be driven for synchronous system operation.
t rise
t fa ll
0 .9 * V D
0 .1 * V D
Figure 2. Digital Input Rise and Fall Times
Input Selection
MUX1
MUX0
Gain Selection
GAIN2
GAIN1
GAIN0
0
0
0
800 Ω termination
0
0
x1
INA only
1
0
x2
0
0
1
INB only
0
1
x4
0
1
0
INA + INB
1
1
x8
0
1
1
x16
1
0
0
x32
1
0
1
x64
1
1
0
reserved
1
1
1
Table 1. Digital Selections for Gain and Input Mux Control
DS757F1
7
CS3301A
POWER SUPPLY CHARACTERISTICS
CS3301A
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Current, Normal
Analog Power Supply Current
(Note 17)
IA
-
5.5
6.8
mA
Digital Power Supply Current
(Note 17)
ID
-
0.2
0.25
mA
Power Supply Current, Power Down (PWDN=1)
Analog Power Supply Current
(Note 17)
IA
-
8
12
µA
Digital Power Supply Current
(Note 17)
ID
-
2
8
µA
PSRR
100
120
-
dB
Power Supply Rejection
Power Supply Rejection Ratio
(Note 4, 18)
Notes: 17. All outputs unloaded. Analog inputs connected to the internal 800 Ω termination. Digital inputs forced to
VD or GND respectively.
18. Power supply rejection characterized with a 50 Hz, 400 mVp-p sine wave applied separately to each
supply.
8
DS757F1
CS3301A
2.
GENERAL DESCRIPTION
The CS3301A is a low-noise chopper-stabilized
CMOS differential input, differential output amplifier for precision analog signals between DC and
2 kHz. It has multiplexed inputs, rough / fine outputs and programmable gains of x1, x2, x4, x8,
x16, x32, and x64.
The amplifier’s performance makes it ideal for
low-frequency, high dynamic range applications
requiring low distortion and minimal power consumption. It’s optimized for use in acquisition systems designed around the CS5371A/72A
single/dual ∆Σ modulators and the CS5376A quad
digital filter or the CS5373A ∆Σ modulator and
CS5378 digital filter.
Figure 3 on page 9 shows the system architecture of
a 4-channel acquisition system using four
CS3301A, two CS5372A, one CS4373A, and one
CS5376A. Figure 4 on page 10 shows the system
Geophone
or
Hydrophone
Sensor
Geophone
or
Hydrophone
Sensor
M
U
X
M
U
X
architecture of a single channel acquisition system
using a CS3301A, CS5373A, and CS5378.
2.1
Analog Signals
2.1.1
Analog Inputs
The amplifier analog inputs are designed for differential sensors. Input multiplexing simplifies system connections by providing separate inputs for a
sensor and test DAC (INA, INB) as well as an internal termination for noise tests. The MUX0,
MUX1 digital pins determine which multiplexed
input is connected to the amplifier.
2.1.2
Analog Outputs
The amplifier analog outputs are separated into
rough charge / fine charge signals to easily connect
to the CS5371A/72A/73A modulator inputs. Each
differential output requires two series resistors and
a differential capacitor to create the modulator antialias RC filter.
CS3301A
CS3302A
CS5371A
CS5372A
AMP
CS3301A
CS3302A
System Telemetry
∆Σ
Modulator
AMP
CS5376A
µController
or
Configuration
EEPROM
Digital Filter
Geophone
or
Hydrophone
Sensor
Geophone
or
Hydrophone
Sensor
M
U
X
M
U
X
CS3301A
CS3302A
CS5371A
CS5372A
AMP
CS3301A
CS3302A
Communication
Interface
∆Σ
Modulator
AMP
CS4373A
Switch
Switch
MUX
MUX
Test
DAC
Figure 3. Multi-Channel System Architecture
DS757F1
9
CS3301A
CS5373A
Differential
Sensor
CS3301A
CS3302A
M
U
X
AMP
CS5378
∆Σ
Modulator
µController
or
Configuration
EEPROM
Digital Filter
System
Telemetry
Test
DAC
Figure 4. Single-Channel System Architecture
2.1.3
Differential Signals
Analog signals into and out of the CS3301A are
differential, consisting of two halves with equal but
opposite magnitude varying about a common mode
voltage.
A full scale 5 Vpp differential signal centered on a
-0.15 V common mode can have:
SIG+ = -0.15 V + 1.25 V = 1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIGFor the reverse case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = 1.1 V
SIG+ is -2.5 V relative to SIGThe total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation
can be done for SIG- relative to SIG+. Note that a
5 Vpp differential signal centered on a -0.15 V
common mode voltage never exceeds 1.1 V and
never drops below -1.4 V on either half of the signal.
By definition, differential voltages are to be measured with respect to the opposite half, not relative
10
to ground. A multimeter differentially measuring
between SIG+ and SIG- in this example would
properly read 1.767 Vrms, or 5 Vpp.
2.2
2.2.1
Digital Signals
Clock Input
The clock signal is used by the chopperstabilization circuitry of the amplifier analog inputs. The CLK pin can be driven by an external
clock source for synchronous operation, or CLK
can be grounded to run from its own internally generated clock signal. The CLK pin is connected to a
clock detect circuit which will disable the internal
clock and use an external clock if one is supplied.
If the internal clock signal is to be used, the CLK
pin should be connected to GND.
2.2.2
Gain Selection
The CS3301A supports gain ranges of x1, x2, x4,
x8, x16, x32, and x64. They are selected using the
GAIN0, GAIN1, and GAIN2 pins as shown in
Table 1 on page 7.
2.2.3
Mux Selection
The analog inputs to the amplifier are multiplexed,
with external signals applied to the INA+, INA- or
INB+, INB- pins. An internal termination is also
available for noise tests. Input mux selection is
DS757F1
CS3301A
made using the MUX0 and MUX1 pins as shown in
Table 1 on page 7.
Although a mux selection is provided to enable the
INA and INB switches simultaneously, signal current should not be driven through them in this
mode. The CS3301A mux switches will maintain
good linearity only with minimal signal currents.
2.2.4
Power Down Selection
A power-down mode is available to shut down the
amplifier when not in use. When enabled, all internal circuitry is disabled, the analog inputs and outputs go high-impedance, and the device enters a
micro-power state. Power down mode is selected
using the PWDN pin, which is active high.
2.3
Power Supplies
2.3.1
Analog Power Supplies
When using bipolar power supplies, the analog signal common mode voltage should be biased to 0 V.
The analog power supplies are recommended to be
bypassed to system ground using 0.1 µF X7R type
capacitors.
The VA- supply is connected to the CMOS substrate and as such must remain the most negative
applied voltage. It is recommended to clamp the
VA- supply to system ground using a reversed biased Schottky diode to prevent possible damage related to mis-matched power supply initialization.
2.3.2
Digital Power Supplies
The digital voltage across the VD and GND pins is
specified for a +3.3 V power supply. The digital
power supply should be bypassed to system ground
using a 0.01 µF X7R type capacitor.
The analog power pins of the CS3301A are specified to run from bipolar ±2.5 V power supplies.
DS757F1
11
CS3301A
2.4
Connection Diagram
Figure 5 on page 12 shows a connection diagram
for the CS3301A amplifier when used with the
CS5372A dual ∆Σ modulator, the CS4373A Test
DAC, and the CS5376A digital filter. The diagram
shows differential sensors and test DAC inputs, and
analog outputs with anti-alias RC components;
power supply connections including recommended
bypassing; and digital control connections back to
the CS5376A GPIO pins.
GPIO (x3)
GPIO (x2)
GPIO
MCLK
3
2
GAIN
MUX
PWDN
To CS5376A
Digital Control
CLK
VA+
VD
VA+
VA+
VD
0.1µF
0.01µF
VD
CS3301A
Differential
Amplifier
0.1µF
0.01µF
VA-
VA+
VA-
0.1µF
VD
GND
INA+
INA-
INB-
INB+
OUTR-
OUTF-
OUTF+
OUTR+
MDATA1
MFLAG1
PWDN1
680
INR+
INF+
680
0.02µF
C0G
680
0.02µF
C0G
INFINR-
Differential
Sensor
MCLK
MSYNC
680
VREF+
CS4373A
Test DAC
CS5372A
∆Σ Modulator
2.5 V
Reference
VREF-
Differential
Sensor
680
INRINF680
0.02µF
C0G
680
OFST
0.02µF
C0G
INF+
INR+
MDATA2
MFLAG2
PWDN2
680
INA+
INA-
INB-
INB+
OUTR-
OUTF-
OUTF+
OUTR+
VA+
VD
VA+
VD
VACS3301A
Differential
Amplifier
0.1µF
0.01µF
VAVA0.1µF
MUX
PWDN
2
3
VA0.1µF
GND
GAIN
GND
CLK
MCLK
GPIO
GPIO (x2)
GPIO (x3)
To CS5376A
Digital Control
Figure 5. CS3301A Amplifier Connections
12
DS757F1
CS3301A
3.
PIN DESCRIPTION
Positive Analog Power Supply
VA+
1
24
MUX0
Input Mux Select
Negative Analog Rough Output
OUTR-
2
23
MUX1
Input Mux Select
Negative Analog Fine Output
OUTF-
3
22
GAIN0
Gain Range Select
Negative Analog Power Supply
VA-
4
21
GAIN1
Gain Range Select
Non-Inverting Input A
INA+
5
20
GAIN2
Gain Range Select
Inverting Input A
INA-
6
19
PWDN
Power Down Mode Enable
Inverting Input B
INB-
7
18
GND
Ground
Non-Inverting Input B
INB+
8
17
TEST1
Test Mode Select
Test Mode Output
TESTOUT
9
16
VD
Positive Digital Power Supply
Positive Analog Fine Output
OUTF+
10
15
GND
Ground
Positive Analog Rough Output
OUTR+
11
14
TEST2
Test Mode Select
Test Mode Select
TEST0
12
13
CLK
Clock Input
Figure 6. CS3301A Pin Assignments
Pin Name
Pin #
I/O
VA+
1
I
Positive analog supply voltage.
VA-
4
I
Negative analog supply voltage.
VD
16
I
Positive digital supply voltage.
15, 18
I
Ground.
INA+, INA-
5, 6
I
Channel A differential analog inputs. Selected via MUX pins.
INB+, INB-
8, 7
I
Channel B differential analog inputs. Selected via MUX pins.
OUTR+, OUTR-
11, 2
O
Rough charge differential analog outputs.
OUTF+, OUTF-
10, 3
O
Fine charge differential analog outputs.
GAIN0, GAIN1,
GAIN2
22, 21,
20
I
Gain range select. See Gain Selection table in Digital Characteristics section.
CLK
13
I
Master clock input. Connect to GND to use internal oscillator.
PWDN
19
I
Power down mode enable. Active high.
24, 23
I
Analog input select. See Input Selection table in Digital Characteristics section.
GND
MUX0, MUX1
TEST0
TEST1, TEST2
TESTOUT
Pin Description
12
I
17, 14
I
Test mode select, factory use only. Connect to VA- during normal operation.
Test mode select, factory use only. Connect to GND during normal operation.
9
O
Test mode output, factory use only. No connect during normal operation.
Table 2. Pin Descriptions
DS757F1
13
CS3301A
4.
PACKAGE DIMENSIONS
24 PIN SSOP PACKAGE DRAWING
N
D
E11
A2
E
b2
e
SIDE VIEW
A
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
INCHES
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.024
0.025
0°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.027
0.040
8°
MILLIMETERS
MIN
MAX
-2.13
0.05
0.25
1.62
1.88
0.22
0.38
7.90
8.50
7.40
8.20
5.00
5.60
0.61
0.69
0.63
1.03
0°
8°
NOTE
2,3
1
1
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
14
DS757F1
CS3301A
5.
ORDERING INFORMATION
Model
CS3301A-IS
CS3301A-ISZ (lead free)
6.
Temperature
Package
-40 to +85 °C
24-pin SSOP
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS3301A-IS
240 °C
2
365 Days
CS3301A-ISZ (lead free)
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS757F1
15
CS3301A
7.
REVISION HISTORY
Revision
Date
PP1
FEB 2007
Preliminary release.
Changes
F1
MAR 2007
Updated to final for QPL (Quality Process Level).
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
16
DS757F1