CY24204 MediaClock™ DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop (PLL) • Internal PLL with up to 400-MHz internal operation • Low jitter, high-accuracy outputs • Meets critical timing requirements in complex system designs • VCXO with Analog Adjust • Large ±150-ppm range, better linearity • 3.3V operation • Enables application compatibility Part Number Outputs Input Frequency Output Frequency Range CY24204-3 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable) CY24204-4 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased VCXO pull range) CY24204-5 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased output drive strength) Pin Configurations Block Diagram 16-pin TSSOP OSC. Q Φ VCO XOUT VCXO OUTPUT MULTIPLEXER AND DIVIDERS P CLK1 CLK2 PLL REFCLK1 REFCLK2 (-3,-4,-5) FS0 XIN VDD 1 16 XOUT 2 15 14 13 OE FS1 VSS 12 CLK1 AVDD 3 VCXO 4 AVSS 5 VSSL 6 REFCLK2 7 REFCLK1 8 24204-,3,4,5 XIN 11 VDDL 10 FS0 9 CLK2 FS1 OE VDDL VDD Cypress Semiconductor Corporation Document #: 38-07450 Rev. *C AVDD • AVSS VSS VSSL 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY24204 Frequency Select Options OE FS1 FS0 CLK1/CLK2[1] REFCLK 1/2 Unit 0 0 0 off 27 MHz 0 0 1 off 27 MHz 0 1 0 off 27 MHz 0 1 1 off 27 MHz 1 0 0 27 27 MHz 1 0 1 27.027 27 MHz 1 1 0 74.250 27 MHz 1 1 1 74.17582418 27 MHz Pin Description Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. VCXO 4 Input Analog Control for VCXO. AVSS 5 Analog Ground. VSSL 6 CLK Ground. REFCLK2 7 Reference Clock Output. REFCLK1 8 Reference Clock Output. CLK1 9 27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). FS0 10 Frequency Select 0, Weak Internal Pull-up. VDDL 11 CLK Voltage Supply. CLK2 12 27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). VSS 13 Ground. FS1 14 Frequency Select 1, Weak Internal Pull-up. OE 15 Output Enable, Weak Internal Pull-up. XOUT 16 Reference Crystal Output. Note: 1. “off” = output is driven HIGH. Document #: 38-07450 Rev. *C Page 2 of 6 CY24204 Absolute Maximum Conditions Storage Temperature (Non-Condensing).... –55°C to +125°C Junction Temperature ................................. –40°C to +125°C (Above which the useful life may be impaired. For user guidelines, not tested.) Data Retention @ Tj=125°C..................................> 10 years Supply Voltage (VDD, AVDDL, VDDL)..................–0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage...................................... –0.5V to VDD + 0.5 ESD (Human Body Model) MIL-STD-883.................... 2000V Pullable Crystal Specifications Parameter Description Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut – 27.0 – MHz – 14 – pF 25 Ω FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode – R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 fF Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.135 3.3 3.465 V VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms DC Electrical Specifications Parameter[2] Min. Typ. Max. Unit IOH1 Output High Current for -3,-4, Name VOH = VDD – 0.5, VDD/VDDL = 3.3V Description 12 24 – mA IOL1 Output Low Current for -3,-4 VOL = 0.5, VDD/VDDL = 3.3V 12 24 – mA IOH2 Output High Current for -5 VOH = VDD – 0.5, VDD/VDDL = 3.3V 18 26 – mA IOL2 Output Low Current for -5 VOL = 0.5, VDD/VDDL = 3.3V 18 26 – mA VIH Input High Voltage 0.7 – – VDD VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 VDD IVDD Supply Current AVDD/VDD Current – – 25 mA IVDDL Supply Current VDDL Current (VDDL = 3.47V) – – 20 mA CIN Input Capacitance – – 7 pF f∆XO VCXO pullability range Nominal pullability for -1,-2,-3,-5,-6 f∆XO VCXO pullability range Extended pullability for -4 VVCXO VCXO input range RUP Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured at VIN = 0V CMOS levels, 70% of VDD ±150 – – ppm – ±200 – ppm 0 – VDD V – 100 150 kΩ Note: 2. Not 100% tested. Document #: 38-07450 Rev. *C Page 3 of 6 CY24204 AC Electrical Specifications Parameter[2] Name Description Min. Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Typ. Max. Unit DC Output Duty Cycle 45 50 55 % ER1 Rising Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns EF1 Falling Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns ER2 Rising Edge Rate for -5 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 1.0 1.8 – V/ns EF2 Falling Edge Rate for -5 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 1.0 1.8 – V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 120 – ps t10 PLL Lock Time – – 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Document #: 38-07450 Rev. *C Page 4 of 6 CY24204 Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24204ZC-3 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-3T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-4 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-4T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-5 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZC-5T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-3 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-3T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-4 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-4T Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-5 Z16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-5T Z16 16-Pin TSSOP Commercial 3.3V Standard Lead-free Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05gms 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07450 Rev. *C Page 5 of 6 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24204 Document History Page Document Title: CY24204 MediaClock™ DTV, STB Clock Generator Document Number: 38-07450 REV. ECN NO. Issue Date Orig. of Change ** 123842 04/10/03 CKN *A 128775 09/0803 IJA Description of Change New Data Sheet Added -4 and -5 parts *B 214080 See ECN RGL Added -6 part *C 310573 See ECN RGL Removed -1,-2 and -6 parts Added Lead-free devices for -3, -4, and -5 parts Document #: 38-07450 Rev. *C Page 6 of 6