PRELIMINARY CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Features Benefits • Compliant with Intel CK-Titan and CK-408 clock synthesizer/driver specifications Supports next generation Pentium processors using differential clock drivers • Multiple output clocks at different frequencies Motherboard clock generator — Two pairs of differential CPU outputs, up to 200 MHz — Support multiple CPUs and a chipset — Nine synchronous PCI clocks, three free-running — Support for PCI slots and chipset — Six 3V66 clocks — Supports AGP, DRCG reference, and Hub Link — Two 48-MHz clocks — Supports USB host and graphic controllers — One reference clock at 14.318 MHz — Supports ISA slots and I/O chip — One VCH clock • Spread Spectrum clocking (down spread) Enables reduction of EMI and overall system cost • Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) Enables ACPI-compliant designs • Two select inputs (Mode select & IC Frequency Select) Supports up to four CPU clock frequencies • 48-pin TSSOP package Widely available, standard package enables lower cost Logic Block Diagram Pin Configurations TSSOP Top View X1 X2 XTAL OSC VDD_REF PWR REF PLL Ref Freq PLL 1 S1:2 PWR_GD# CPU_STOP# Divider Network PWR Gate Stop Clock Control VDD_CPU CPU1:2 1 48 VDD_REF 2 47 REF0 GND_REF 3 46 S1 PCI_F0 4 45 CPU_STOP# PCI_F1 5 44 VDD_CPU PCI_F2 6 43 CPU1 GND_PCI 7 42 CPU#1 PCI0 8 41 GND_CPU PCI1 9 40 VDD_CPU PCI2 10 39 CPU2 VDD_PCI 11 38 CPU#2 PCI3 37 IREF PCI4 12 13 36 S2 PCI5 14 35 USB VDD_3V66 GND_3V66 15 34 DOT 16 33 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 17 32 VDD_48 MHz GND_48 MHz 18 31 19 30 66IN/3V66_5 20 29 PCI_STOP# 3V66_0 PWR_DWN# 21 28 VDD_3V66 VDD_CORE 22 27 GND_CORE PWR_GD# 23 26 GND_3V66 SCLK 24 25 SDATA CPU#1:2 VDD_PCI PCI_F0:2 PWR Stop Clock Control PCI_STOP# /2 PWR_DWN# PCI0:5 VDD_3V66 PWR 3V66_0:1 3V66_2:4/ 66BUFF0:2 PWR 3V66_5/ 66IN PLL 2 VDD_48MHz PWR USB (48MHz) DOT (48MHz) CY28322-2 XTAL_IN XTAL_OUT 3V66_1/VCH VCH_CLK/ 3V66_1 SDATA SCLK SMBus Logic Cypress Semiconductor Corporation Document #: 38-07145 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY28322-2 PRELIMINARY Pin Summary Pin Name Pin Number Pin Description REF0 47 3.3V 14.318-MHz clock output XTAL_IN 1 14.318-MHz crystal input XTAL_OUT 2 14.318-MHz crystal input CPU, CPU# [1:2] 43, 39, 42, 38 Differential CPU clock outputs 3V66_0 29 3.3V 66-MHz clock output 3V66_1/VCH 31 3.3V selectable through SMBus to be 66 MHz or 48 MHz 66IN/3V66_5 20 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO 66BUFF [2:0] /3V66 [4:2] 17, 18, 19 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO PCI_F [0:2] 4, 5, 6 33 MHz clocks divided down from 66Input or divided down from 3V66 PCI [0:5] 8, 9, 10, 12, 13, 14 PCI clock outputs divided down from 66Input or divided down from 3V66 USB 35 Fixed 48-MHz clock output DOT 34 Fixed 48-MHz clock output S2 36 Special 3.3V 3-level input for Mode selection S1 46 3.3V LVTTL inputs for CPU frequency selection IREF 37 A precision resistor is attached to this pin which is connected to the internal current reference PWR_DWN# 21 3.3V LVTTL input for Power_Down# (active LOW) PCI_STOP# 30 3.3V LVTTL input for PCI_STOP# (active LOW) CPU_STOP# 45 3.3V LVTTL input for CPU_STOP# (active LOW) PWRGD# 24 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SDATA 25 SMBus compatible SDATA SCLK 26 SMBus compatible Sclk VDD_PCI, VDD_3V66, VDD_CPU,VDD_REF 11, 15, 28, 40, 44, 3.3V power supply for outputs 48 VDD_48 MHz 33 3.3V power supply for 48 MHz VDD_CORE 22 3.3V power supply for PLL GND_REF, GND_PCI, 3, 7, 16, 27, 32, 41 Ground for outputs GND_3V66, GND_IREF, GND_CPU GND_CORE 23 Ground for PLL Function Table[1] S2 1 1 0 0 Mid Mid S1 0 1 0 1 0 1 CPU (MHz) 100 MHz 133 MHz 100 MHz 133 MHz TCLK/2 Reserved 3V66[0:1] (MHz) 66 MHz 66 MHz 66 MHz 66 MHz TCLK/4 Reserved 66BUFF[0:2]/3 V66[2:4] (MHz) 66IN 66IN 66 MHz 66 MHz TCLK/4 Reserved 66IN/3V66_5 (MHz) 66 MHz Input 66 MHz Input 66 MHz 66 MHz TCLK/4 Reserved PCI_F/PCI (MHz) 66IN/2 66IN/2 33 MHz 33 MHz TCLK/8 Reserved REF0(MHz) 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz TCLK Reserved USB/DOT (MHz) 48 MHz 48 MHz 48 MHz 48 MHz TCLK/2 Reserved Notes 2, 3, 4 2, 3, 4 2, 3, 4 2, 3, 4 7, 8, 5 – Notes: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation 3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. 5. Mid is defined a voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V. 6. Required for DC output impedance verification. 7. These modes are to use the same internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock margining. 8. All parameters specified with loaded outputs. Document #: 38-07145 Rev. *B Page 2 of 17 CY28322-2 PRELIMINARY Clock Driver Impedances Impedance Buffer VDD Range Min. Ω Buffer Type CPU, CPU# Typ. Ω Type X1 Max. Ω 50 REF 3.135–3.465 Type 3 20 40 60 PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55 USB 3.135–3.465 Type 3A 12 30 55 DOT 3.135–3.465 Type 3B 12 30 55 Clock Enable Configuration PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI USB/DOT VCOS/ OSC OFF 0 X X IREF*2 FLOAT LOW LOW LOW LOW LOW 1 0 0 IREF*2 FLOAT ON ON ON OFF ON ON 1 0 1 IREF*2 FLOAT ON ON ON ON ON ON 1 1 0 ON ON ON ON ON OFF ON ON 1 1 1 ON ON ON ON ON ON ON ON Serial Data Interface (SMBus) ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. To enhance the flexibility and function of the clock synthesizer, a two signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. CY28322-2 supports both block read and block write operations. A block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the Start Slave Address R/W Bit 1 1 0 1 0 0 1 0 0/1 A Command Code 00000000 1 bit 1 8 bits 7 bits 1 A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. A Byte Count = A Data Byte 0 A N 1 8 bits 1 8 bits 1 ... Data Byte N-1 A Stop Bit 8 bits 1 1 bit From Master to Slave From Slave to Master Document #: 38-07145 Rev. *B Figure 1. An Example of a Block Write Page 3 of 17 PRELIMINARY CY28322-2 Data Byte Configuration Map Data Byte 0: Control Register (0 = Enable, 1 = Disable) Bit Bit 7 Affected Pin# Name 4, 5, 6, 10, PCI [0:6] 11, 12, 13, CPU[2:1] 16, 17, 18, 3V66[1:0] 33, 35 Description Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Bit 6 – TBD TBD Bit 5 31 3V66_1/VCH VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz Bit 4 39, 43, 38, CPU [2:1] 42 CPU# [2:1] CPU_STOP# Reflects the current value of the external CPU_STOP# pin Bit 3 8, 9, 10, 11, PCI [5:0] 12, 13, 14, PCI_STOP# (Does not affect PCI_F [2:0] pins) Type Power-on Default R/W 0 R 0 R/W 0 R N/A R/W N/A Bit 2 – – S2–Reflects the value of the S2 pin sampled on power-up R N/A Bit 1 – – S1–Reflects the value of the S1 pin sampled on power-up R N/A Bit 0 – – Reserved R 1 Type Power-on Default R N/A Data Byte 1 Bit Pin# Bit 7 – Bit 6 Name Description N/A CPU Mult0 Value 43,39, CPU1:2 Three-state CPU1:2 during power-down 0 = Normal; 1 = Three-stated R/W 0 Bit 5 38, 39 CPU2 CPU2# Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running R/W 0 Bit 4 42, 43 CPU1 CPU1# Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running R/W 0 Bit 3 – Reserved Reserved R/W 0 Bit 2 38, 39 CPU2 CPU2# CPU2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 42, 43 CPU1 CPU1# CPU1Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 – Reserved Reserved R/W 1 Type Power-on Default Data Byte 2 Bit Pin# Bit 7 Name Pin Description N/A N/A R 0 Bit 6 14 PCI5 PCI5 Output Enable 1 = Enabled, 0 = Disabled R/W 1 Bit 5 13 PCI4 PCI4 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 12 PCI3 PCI3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 10 PCI2 PCI2Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 2 9 PCI1 PCI1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 8 PCI0 PCI0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Reserved Write to”0” R/W 1 Bit 0 Document #: 38-07145 Rev. *B Page 4 of 17 CY28322-2 PRELIMINARY Data Byte 3 Bit Pin# Name Pin Description Type Power-on Default 1 Bit 7 34 DOT DOT 48-MHz Output Enable R/W Bit 6 35 USB USB 48-MHz Output Enable R/W 1 Bit 5 6 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 4 5 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 3 4 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 2 6 PCI_F2 PCI_F2 Output Enable R/W 1 Bit 1 5 PCI_F1 PCI_F1Output Enable R/W 1 Bit 0 4 PCI_F0 PCI_F0 Output Enable R/W 1 Type Power-on Default Data Byte 4 Bit Pin# Name Pin Description Bit 7 – TBD N/A R 0 Bit 6 – TBD N/A R 0 Bit 5 29 3V66_0 3V66_0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 31 3V66_1/VCH 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 20 66IN/3V66_5 3V66_5 Output Enable 1 = Enable; 0 = Disable Note. This bit should be used when pin 24 is configured as 3v66_5 output. Do not clear this bit when pin 24 is configured as 66IN input. R/W 1 Bit 2 19 66BUFF2 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 18 66BUFF1 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 17 66BUFF0 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Type Power-on Default Data Byte 5 Bit Pin# Name Pin Description Bit 7 N/A N/A R 0 Bit 6 N/A N/A R 0 Bit 5 66BUFF [2:0] Tpd 66IN to 66BUFF propagation delay control R/W 0 Bit 4 66BUFF [2:0] R/W 0 R/W 0 R/W 0 Bit 3 DOT Bit 2 DOT Bit 1 USB Bit 0 USB DOT edge rate control USB edge rate control R/W 0 R/W 0 Byte 6: Vendor ID Bit Description Type Power-on Default Bit 7 Revision Code Bit 3 R 0 Bit 6 Revision Code Bit 2 R 0 Bit 5 Revision Code Bit 1 R 0 Document #: 38-07145 Rev. *B Page 5 of 17 CY28322-2 PRELIMINARY Byte 6: Vendor ID (continued) Bit Description Type Power-on Default Bit 4 Revision Code Bit 0 R 0 Bit 3 Vendor ID Bit 3 R 1 Bit 2 Vendor ID Bit 2 R 0 Bit 1 Vendor ID Bit 1 R 0 Bit 0 Vendor ID Bit 0 R 0 Document #: 38-07145 Rev. *B Page 6 of 17 CY28322-2 PRELIMINARY Storage Temperature (Non-condensing) .... –65°C to +150°C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ...................... +260°C Junction Temperature ............................................... +150°C Supply Voltage ..................................................–0.5 to +7.0V Package Power Dissipation...............................................1Ω Input Voltage .............................................. –0.5V to VDD+0.5 Static Discharge Voltage ........................................................ (per MIL-STD-883, Method 3015) ............................ > 2000V Operating Conditions[9] Over which Electrical Parameters are Guaranteed Parameter Description Min. Max. Unit V VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, 3.3V Supply Voltages 3.135 3.465 VDD_48 MHz 48-MHz Supply Voltage 2.85 3.465 V TA Operating Temperature, Ambient 0 70 °C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage USB, REF, 3V66 IOH = –1 mA 2.4 V PCI IOH = –1 mA 2.4 V USB, REF, 3V66 IOL = 1 mA 0.4 V PCI IOL = 1 mA 0.55 V VOL Low-level Output Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 2.0 V 0.8 V IIH Input High Current 0 < VIN < VDD –5 5 mA IIL Input Low Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH =6*IRef Configuration Type X1, VOH = 0.65V REF, DOT, USB Type 3, VOH = 1.00V 12.9 Type X1, VOH = 0.74V 14.9 –29 Type 3, VOH = 3.135V 3V66, DOT, PCI Type 5, VOH = 1.00V –23 –33 Type 5, VOH = 3.135V IOL Low-level Output Current REF, DOT, USB Type 3, VOL = 1.95V –33 29 Type 3, VOL = 0.4V 3V66, PCI Type 5, VOL =1.95 V Type 5, VOL = 0.4V IOZ Output Leakage Current IDD3 mA 27 30 38 10 mA 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 360 mA IDDPD3 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA (Byte1, Bit [6] = 0) 25 mA IDDPD3 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA (Byte1, Bit [6] = 0) 45 mA IDDPD3 3.3V Shutdown Current VDD_CORE/VDD3.3 = 3.465V (Byte1, Bit [6] = 1) 1.5 mA Document #: 38-07145 Rev. *B Three-state mA Page 7 of 17 CY28322-2 PRELIMINARY - Switching Characteristics[8] Over the Operating Range Parameter Output Description Test Conditions Min. Max. Unit t1 All Output Duty Cycle[9] Measured at 1.5V 45 55 % t3 USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 ns t3 PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t5 3V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66, PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V 3.5 ns t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps 1.5 CPU 1.0V Switching Characteristics t2 CPU Rise Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps 325 mV CPU Rise/Fall Matching Measured with test loads [11] [12] 0.92 1.45 V Voh CPU High-level Output Voltage including overshoot Measured with test loads Vol CPU Low-level Output Voltage including undershoot Measured with test loads[12] –0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[12] 0.51 0.76 V Notes: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 10. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 11. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 12. The 1.0V test load is shown on test circuit page. Document #: 38-07145 Rev. *B Page 8 of 17 CY28322-2 PRELIMINARY Definition and Application of PWRGD# Signal Vtt VRM8.5 CPU PWRGD# BSEL0 BSEL1 3.3V 3.3V 3.3V NPN PWRGD# CLOCK S0 10K 10K GMCH GENERATOR S1 Document #: 38-07145 Rev. *B 10K 10K Page 9 of 17 PRELIMINARY CY28322-2 Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t5 Document #: 38-07145 Rev. *B Page 10 of 17 CY28322-2 PRELIMINARY Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t6 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK Document #: 38-07145 Rev. *B Page 11 of 17 CY28322-2 PRELIMINARY PWRDWN# Assertion 66BUFF PCI Power-down Rest of Generator PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 UNDEF 66IN USB REF Note: PCI_STOP# asserted LOW PWRDWN# Deassertion <3 ms 10-30 µs min. 100-200 µs max. 66BUFF1/GMCH 66BUFF0,2 PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: PCI_STOP# asserted LOW Document #: 38-07145 Rev. *B Page 12 of 17 CY28322-2 PRELIMINARY PWRGD# Timing Diagrams GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM Possible glitch while Clock VCC is coming up. Will be gone in 0.2–0.3 mS delay. PWRGD# FROM NPN VCC CPU CORE PWRGD# 0.2 -- 0.3 ms Wait for delay PWRGD# VCC W320 CLOCK GEN State 1 State 0 CLOCK STATE State 2 Sample BSELS State 3 OFF ON CLOCK VCO OFF ON CLOCK OUTPUTS Figure 2. CPU Power BEFORE Clock Power GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM VCC CPU CORE PWRGD# 0.2 – 0.3 ms delay VCC W320 CLOCK GEN CLOCK STATE State 0 State 1 Wait for PWRGD# Sample BSELS State 2 State 3 OFF ON CLOCK VCO OFF ON LOCK OUTPUTS Figure 3. CPU Power AFTER Clock Power Document #: 38-07145 Rev. *B Page 13 of 17 CY28322-2 PRELIMINARY Layout Example +3.3V Supply FB VDDQ3 µF 0.005 µF G C1 G 1 2 3 4 5 6 7 8 9 G G G G G 11 V 12 G 13 14 15 V 16 G 17 18 19 G 20 21 GCore 22 V 23 G 24 G G V G CY28322-2 G G V 10 G G V G G G *Option A GG G V G G 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 G G G VDDQ3 8Ω C5 G *Option B G C6 G FB = Dale ILB1206–300 or 2TDKACB2012L–120 or 2 Murata BLM21B601S Ferrite bead Ceramic Caps C1 = 10–22 µF G = VIA to GND plane layer C2 = 0.005 µF C5 = 0.1 µF C6 = 10 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors. * If on board video uses 48-MHz or Dot clock add the Option B 8Ω series resistor All Bypass cap’s on VDD pin = 0.1 µF Low ESR Document #: 38-07145 Rev. *B Page 14 of 17 CY28322-2 PRELIMINARY Test Circuit VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 3, 7, 16, 27, 32, 41 1.0V Test Load 33 11, 15, 28, 40, 44, 48 2 pF Ref,USB Outputs Test Node CY28322-2 33 OUTPUTS 20 pF Test Nodes 475 CPU 2 pF PCI,3V66 Outputs Test Node 30 pF 63.4 63.4 1.0V Amplitude Ordering Information Ordering Code CY28322ZC-2 Document #: 38-07145 Rev. *B Package Type 48-pin TSSOP Operating Range Commercial Page 15 of 17 PRELIMINARY CY28322-2 Package Diagram 48-pin Thin Shrink Small Outline Package Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07145 Rev. *B Page 16 of 17 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28322-2 PRELIMINARY Document Title: CY28322-2 133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs Document Number: 38-07145 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 112664 03/01/02 IKA New Data Sheet *A 114703 04/29/02 INA Corrections on some PIN numbers. *B 122796 12/14/02 RBI Add Power up Requirements to Operating Conditions Information Document #: 38-07145 Rev. *B Page 17 of 17