CY62256 256K (32K x 8) Static RAM Functional Description[1] Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C • • • • • • • • • — Automotive: –40°C to 125°C High speed: 55 ns and 70 ns Voltage range: 4.5V–5.5V operation Low active power (70 ns, LL version, Com’l and Ind’l) — 275 mW (max.) Low standby power (70 ns, LL version, Com’l and Ind’l) — 28 µW (max.) Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a standard 450-mil-wide (300-mil body width) 28-lead narrow SOIC, 28-lead TSOP-1, 28-lead reverse TSOP-1, and 600-mil 28-lead PDIP packages The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. Logic Block Diagram I/O0 INPUTBUFFER I/O1 512 x 512 ARRAY I/O2 SENSE AMPS ROW DECODER A10 A9 A8 A7 A6 A5 A4 A3 A2 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 A12 A11 A1 A0 A13 A14 OE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05248 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 25, 2004 CY62256 Product Portfolio Power Dissipation VCC Range (V) Product CY62256 Commercial CY62256L Com’l / Ind’l CY62256LL Commercial CY62256LL Industrial CY62256LL Automotive Min. Typ.[2] Max. 4.5 5.0 5.5 Operating, ICC (mA) Standby, ISB2 (µA) Speed (ns) Typ.[2] Max. Typ.[2] 70 28 55 1 5 55/70 25 50 2 50 Max. 70 25 50 0.1 5 55/70 25 50 0.1 10 55 25 50 0.1 15 Pin Configurations Narrow SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DIP Top View VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 8 9 5 4 3 2 10 11 12 13 14 15 16 17 18 1 28 27 26 25 24 23 22 TSOP I Reverse Pinout Top View (not to scale) 19 20 21 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0 Pin Definitions Pin Number Type Description 1-10, 21, 23-26 Input A0-A14. Address Inputs 11-13, 15-19, Input/Output I/O0-I/O7. Data lines. Used as input or output lines depending on operation 27 Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted 20 Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip 22 Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins 14 Ground GND. Ground for the device 28 Power Supply Vcc. Power supply for the device Notes: 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested. Document #: 38-05248 Rev. *C Page 2 of 12 CY62256 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied..............................................-55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V Range Ambient Temperature (TA)[4] VCC Commercial 0°C to +70°C 5V ± 10% Industrial –40°C to +85°C 5V ± 10% Automotive –40°C to +125°C 5V ± 10% [3] DC Input Voltage .................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range CY62256−55 Parameter Description Min. Typ.[2] Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage 2.4 Input LOW Voltage Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current GND < VI < VCC Max. 2.4 2.2 VIL Unit V 0.4 V VCC +0.5V V VCC +0.5V 2.2 –0.5 0.8 –0.5 0.8 V –0.5 +0.5 –0.5 +0.5 µA +0.5 –0.5 +0.5 µA 28 55 28 55 mA 25 50 25 50 mA –0.5 VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC L LL ISB2 Min. Typ.[2] 0.4 IIX ISB1 CY62256−70 Max. 25 50 25 50 mA 0.5 2 0.5 2 mA L 0.4 0.6 0.4 0.6 mA LL 0.3 0.5 0.3 0.5 mA Automatic CE Power-down Current— TTL Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power-down Current— CMOS Inputs Max. VCC, CE > VCC − 0.3V VIN > VCC − 0.3V, or VIN < L 0.3V, f = 0 LL 1 5 1 5 mA 2 50 2 50 µA 0.1 5 0.1 5 µA LL - Ind’l 0.1 10 0.1 10 µA LL Auto 0.1 15 µA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF Notes: 3. VIL (min.) = −2.0V for pulse durations of less than 20 ns. 4. TA is the “Instant-On” case temperature. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05248 Rev. *C Page 3 of 12 CY62256 Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Symbol DIP SOIC TSOP RTSOP Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 75.61 76.56 93.89 93.89 °C/W ΘJC 43.12 36.07 24.64 24.64 °C/W Thermal Resistance (Junction to Case)[5] AC Test Loads and Waveforms R1 1800 Ω R1 1800 Ω 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 990Ω 100 pF INCLUDING JIG AND SCOPE 3.0V R2 990Ω 5 pF INCLUDING JIG AND SCOPE (a) GND 90% 10% 90% 10% < 5 ns < 5 ns (b) Equivalent to: THÉVENIN EQUIVALENT 639Ω OUTPUT 1.77V Data Retention Characteristics Parameter Conditions[6] Description VDR VCC for Data Retention ICCDR Data Retention Current Max. 2.0 Unit V VCC = 3.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V, or VIN < 0.3V 2 50 µA 0.1 5 µA LL - Ind’l 0.1 10 µA LL - Auto 0.1 10 µA L LL tCDR[5] tR[5] Typ.[2] Min. Chip Deselect to Data Retention Time Operation Recovery Time 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes: 6. No input may exceed VCC + 0.5V. Document #: 38-05248 Rev. *C Page 4 of 12 CY62256 Switching Characteristics Over the Operating Range[7] CY62256−55 Parameter Description Min. Max. CY62256−70 Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low-Z[8] tHZOE OE HIGH to High-Z[8, 9] tLZCE CE LOW to Low-Z[8] 5 tHZCE CE HIGH to CE LOW to Power-up tPD CE HIGH to Power-down ns 70 5 55 35 5 20 5 25 20 ns ns ns 25 0 55 ns ns 5 0 ns ns 70 25 5 High-Z[8, 9] tPU 70 55 ns ns 70 ns Write Cycle[10, 11] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[8, 9] tLZWE WE HIGH to Low-Z[8] 20 5 25 5 ns ns Switching Waveforms Read Cycle No. 1 [12, 13] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. Document #: 38-05248 Rev. *C Page 5 of 12 CY62256 Switching Waveforms (continued) Read Cycle No. 2 [13, 14] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% Write Cycle No. 1 (WE Controlled) ISB [10, 15, 16] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 17 tHD DATAIN VALID tHZOE Write Cycle No. 2 (CE Controlled) [10, 15, 16] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAIN VALID Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05248 Rev. *C Page 6 of 12 CY62256 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [11, 16] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O NOTE 17 tHZWE Document #: 38-05248 Rev. *C tHD DATAIN VALID tLZWE Page 7 of 12 CY62256 Typical DC and AC Characteristics 1.4 1.2 0.6 VIN =5.0V TA =25°C 0.4 0.2 0.8 0.6 VCC =5.0V VIN =5.0V 0.4 0.2 ISB 0.0 4.0 2.0 1.0 ISB2 µA 0.8 4.5 5.0 5.5 0.0 −55 6.0 SUPPLY VOLTAGE (V) 1.4 AA 1.3 NORMALIZED t NORMALIZED t AA 1.6 1.2 TA =25°C 1.0 0.9 5.0 5.5 VCC =5.0V VIN =5.0V 0.0 -0.5 −55 125 6.0 1.2 1.0 VCC =5.0V 0.6 −55 25 125 OUTPUT SOURCE CURRENT (mA) 105 140 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 25 AMBIENT TEMPERATURE (°C) 0.8 4.5 1.0 0.5 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.4 1.1 25 ISB 1.5 AMBIENT TEMPERATURE (°C) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 0.8 4.0 2.5 OUTPUT SINK CURRENT (mA) 1.0 3.0 ICC 1.2 ICC NORMALIZED I CC NORMALIZED I,CC I SB 1.4 STANDBY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document #: 38-05248 Rev. *C Page 8 of 12 CY62256 Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 2.0 1.5 1.0 0.0 0.0 20.0 15.0 VCC =4.5V TA =25°C 10.0 5.0 0.5 1.0 2.0 3.0 4.0 5.0 0.0 NORMALIZED I CC vs.CYCLE TIME 1.25 NORMALIZED ICC 3.0 DELTA tAA (ns) NORMALIZED I PO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 0 SUPPLY VOLTAGE (V) 200 400 600 800 1000 1.00 VCC =5.0V TA =25°C VIN =0.5V 0.75 0.50 10 CAPACITANCE (pF) 20 30 40 CYCLE FREQUENCY (MHz) Truth Table CE WE OE Inputs/Outputs Mode Power H X X High-Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High-Z Output Disabled Active (ICC) Ordering Information Speed (ns) 55 Ordering Code CY62256LL−55SNI CY62256LL−55ZI CY62256LL−55SNE CY62256LL−55ZE 70 Package Name SN28 Z28 SN28 Z28 Package Type 28-lead (300-Mil Narrow Body) Narrow SOIC Operating Range Industrial 28-lead Thin Small Outline Package 28-lead (300-Mil Narrow Body) Narrow SOIC Automotive 28-lead Thin Small Outline Package CY62256LL−55ZRE ZR28 28-lead Reverse Thin Small Outline Package CY62256−70SNC SN28 28-lead (300-Mil Narrow Body) Narrow SOIC Commercial CY62256L−70SNC CY62256LL−70SNC CY62256L–70SNI Industrial CY62256LL−70SNI CY62256LL−70ZC Z28 CY62256LL−70ZI Z28 CY62256−70PC P15 CY62256L−70PC P15 CY62256LL−70PC P15 CY62256LL−70ZRI ZR28 Document #: 38-05248 Rev. *C 28-lead Thin Small Outline Package Commercial 28-lead (600-Mil) Molded DIP Commercial Industrial 28-lead Reverse Thin Small Outline Package Industrial Page 9 of 12 CY62256 Package Diagrams 28-lead (600-mil) Molded DIP P15 51-85017-A 28-lead (300-mil) SNC (Narrow Body) SN28 51-85092-*B Document #: 38-05248 Rev. *C Page 10 of 12 CY62256 Package Diagrams (continued) 28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28 51-85071-*G 28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28 51-85074-*F All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05248 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62256 Document Title: CY62256 256K (32K x 8) Static RAM Document Number: 38-05248 REV. ECN NO. Issue Date Orig. of Change ** 113454 03/06/02 MGN Change from Spec number: 38-00455 to 38-05248 Remove obsolete parts from ordering info, standardize format *A 115227 05/23/02 GBI Changed SN Package Diagram *B 116506 09/04/02 GBI Added footnote 1. Corrected package description in Ordering Information table *C 238448 See ECN AJU Added Automotive product information Document #: 38-05248 Rev. *C Description of Change Page 12 of 12