CY7C199 32K x 8 Static RAM Features Functional Description • High speed The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. — 12 ns • Fast tDOE • CMOS for optimum speed/power • Low active power — 495 mW (Max, “L” version) • Low standby power — 0.275 mW (Max, “L” version) • 2V data retention (“L” version only) • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • Available in pb-free 28-pin TSOP I and 28-pin (300-Mil) Molded DIP An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. Pin Configurations Logic Block Diagram DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND I/O0 INPUT BUFFER I/O1 ROW DECODER I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 32K x 8 ARRAY I/O3 I/O4 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 A 14 A 12 A 13 A 11 A 10 OE OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TSOP I Top View (not to scale) A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12 Selection Guide –12 12 160 Maximum Access Time Maximum Operating Current L Maximum CMOS Standby Current 10 L Cypress Semiconductor Corporation Document #: 38-05160 Rev. *B • 198 Champion Court • –15 15 155 90 10 0.05 –20 20 150 Unit ns mA 10 mA San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 CY7C199 Maximum Ratings DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. –55°C to +125°C Latch-up Current.................................................... > 200 mA Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V Operating Range Range Commercial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range [3] -12 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH=–4.0 mA VCC = Min., IOL=8.0 mA Min. -15 Max. 2.4 Min. -20 Max. 2.4 Min. Max. 2.4 Unit V VOL Output LOW Voltage 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3V 2.2 VCC + 0.3V 2.2 VCC + 0.3V V VIL Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 V –5 +5 –5 +5 –5 +5 µA –5 +5 –5 +5 –5 +5 µA 150 mA 0.4 IIX Input Leakage Current IOZ Output Leakage Current GND < VO < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Automatic CE Power-down Current— TTL Inputs Max. VCC, CE > VIH, Com’l VIN > VIH or L VIN < VIL, f = fMAX 30 Automatic CE Power-down Current— CMOS Inputs Max. VCC, Com’l CE > VCC – 0.3V L VIN > VCC – 0.3V or VIN < 0.3V, f = 0 10 ISB1 ISB2 GND < VI < VCC Com’l 160 L 0.4 155 90 30 mA 30 5 10 0.05 mA mA 10 mA mA Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. Document #: 38-05160 Rev. *B Page 2 of 11 CY7C199 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 8 pF AC Test Loads and Waveforms[5] R1 481Ω R1 481Ω 5V 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255 Ω 30 pF INCLUDING JIG AND SCOPE Equivalent to: 3.0V (a) R2 255Ω 5 pF INCLUDING JIG AND SCOPE 10% 90% 10% 90% GND ≤tr ≤tr (b) THÉVENIN EQUIVALENT 167 Ω OUTPUT 1.73V Data Retention Characteristics Over the Operating Range (L-version only) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] tR [5] Conditions[6] Min. Max. 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, Chip Deselect to Data Retention Time V > V – 0.3V or V < 0.3V IN CC IN Operation Recovery Time Unit V 10 µA 0 ns 200 µs Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V tCDR 3.0V tR CE Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds. 6. No input may exceed VCC + 0.5V. Document #: 38-05160 Rev. *B Page 3 of 11 CY7C199 Switching Characteristics Over the Operating Range [3,7] -12 Parameter Description Min. -15 Max. Min. -20 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 12 15 20 ns tDOE OE LOW to Data Valid 5 7 9 ns [8] tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z[8, 9] [8] tLZCE CE LOW to Low-Z CE HIGH to tPU CE LOW to Power-up tPD CE HIGH to Power-down Write 12 3 20 15 3 0 3 3 0 12 ns 9 7 ns ns 9 0 15 ns ns 0 3 0 20 7 5 ns 3 0 5 High-Z[8, 9] tHZCE 15 ns ns 20 ns Cycle[10, 11] tWC Write Cycle Time 12 15 20 ns tSCE CE LOW to Write End 9 10 15 ns tAW Address Set-up to Write End 9 10 15 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 8 9 15 ns tSD Data Set-up to Write End 8 9 10 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[9] tLZWE Low-Z[8] WE HIGH to 0 7 3 0 7 3 ns 10 3 ns ns Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05160 Rev. *B Page 4 of 11 CY7C199 Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [13, 14] tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE tHZCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05160 Rev. *B Page 5 of 11 CY7C199 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[10, 15, 16] tWC ADDRESS CE tAW WE tHA tSA tPWE OE tSD tHD DATAIN VALID DATA I/O tHZOE Write Cycle No. 2 (CE Controlled)[10, 15, 16] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05160 Rev. *B Page 6 of 11 CY7C199 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW)[11, 16] tWC ADDRESS CE tAW tHA tSA WE tSD DATA I/O tHD DATAIN VALID tLZWE tHZWE NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC,I SB 1.2 ICC 1.0 0.8 0.6 VIN =5.0V TA =25°C 0.4 0.2 1.2 1.0 0.8 0.6 VCC =5.0V VIN =5.0V 0.4 0.2 ISB 0.0 4.0 ICC 4.5 5.0 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 1.4 NORMALIZED t AA 1.3 NORMALIZEDAAt 125 1.2 1.1 TA =25°C 1.0 1.4 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Document #: 38-05160 Rev. *B OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.8 4.0 25 6.0 0.6 –55 25 125 AMBIENT TEMPERATURE (°C) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED ICC,I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Page 7 of 11 CY7C199 Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 2.0 1.5 1.0 20.0 15.0 VCC =4.5V TA =25°C 10.0 VCC =5.0V TA =25°C VIN =0.5V 1.00 0.75 5.0 0.5 0.0 0.0 NORMALIZED I CC vs. CYCLE TIME 1.25 NORMALIZED I CC 3.0 DELTA t AA (ns) NORMALIZED I PO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.0 2.0 3.0 4.0 5.0 0.0 0 200 SUPPLY VOLTAGE (V) 400 600 800 1000 0.50 10 CAPACITANCE (pF) 20 30 40 CYCLE FREQUENCY (MHz) Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output disabled Active (ICC) Ordering Information Speed (ns) 12 15 20 Ordering Code CY7C199-12ZXC CY7C199-15ZXC CY7C199L-15ZXC CY7C199-20PXC Document #: 38-05160 Rev. *B Package Diagram 51-85071 51-85071 Package Type 28-pin TSOP I (Pb-free) 28-pin TSOP I (Pb-free) Operating Range Commercial Commercial 51-85014 28-pin (300-Mil) Molded DIP (Pb-free) Commercial Page 8 of 11 CY7C199 Package Diagrams 28-pin (300-Mil) PDIP (51-85014) SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 0.260[6.60] 0.295[7.49] 15 PACKAGE WEIGHT: 2.15 gms 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] 0.009[0.23] 0.012[0.30] 0.055[1.39] 0.065[1.65] 0.310[7.87] 0.385[9.78] 0.015[0.38] 0.020[0.50] LEAD END OPTION 3° MIN. SEE LEAD END OPTION 51-85014-*D (LEAD #1, 14, 15 & 28) Document #: 38-05160 Rev. *B Page 9 of 11 CY7C199 Package Diagrams (continued) 28-pin TSOP Type 1 (8x13.4 mm) (51-85071) 51-85071-*G All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05160 Rev. *B Page 10 of 11 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C199 Document History Page Document Title: CY7C199 32K x 8 Static RAM Document Number: 38-05160 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109971 10/28/01 SZV Change from Spec number: 38-00239 to 38-05160 *A 121730 01/09/02 DFP Updated Product Offering table *B 492500 See ECN NXR Removed 8 ns, 10 ns, 25 ns , 35 ns, 45 ns speed bins Removed 28-Lead (300-Mil) CerDIP, 28-Pin Rectangular Leadless Chip Carrier, 28-Lead Molded SOIC, 28-Lead Molded SOJ packages from product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics Table Updated Ordering Information Table Document #: 38-05160 Rev. *B Page 11 of 11