CYPRESS CY7C1480BV25

CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
2.5V core power supply
■
2.5V IO operation
■
Fast clock-to-output time
❐ 3.0 ns (for 250 MHz device)
■
Provide high performance 3-1-1-1 access rate
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1]
SRAM integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1480BV25, CY7C1482BV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) is active. Subsequent burst addresses
can be internally generated as controlled by the Advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed Write cycle. This part supports Byte Write
operations (see “Pin Definitions” on page 7 and “Truth Table” on
page 10 for further details). Write cycles can be one to two or four
bytes wide, as controlled by the byte write control inputs. When
it is active LOW, GW writes all bytes.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
3.0
3.0
3.4
ns
Maximum Operating Current
450
450
400
mA
Maximum CMOS Standby Current
120
120
120
mA
Note
1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-15143 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 29, 2008
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Logic Block Diagram – CY7C1480BV25 (2M x 36)
A 0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1482BV25 (4M x 18)
A0, A1, A
ADDRESS
REGISTER
2
MODE
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
MEMORY
ARRAY
BW A
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
E
BWE
GW
CE 1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 001-15143 Rev. *D
Page 2 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Logic Block Diagram – CY7C1486BV25 (1M x 72)
ADDRESS
REGISTER
A 0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BW H
DQ H , DQP H
WRITE DRIVER
DQ H , DQP H
WRITE DRIVER
BW G
DQ F, DQP F
WRITE DRIVER
DQ G , DQP G
WRITE DRIVER
BW F
DQ F, DQP F
WRITE DRIVER
DQ F, DQP F
WRITE DRIVER
BW E
DQ E , DQP E
WRITE DRIVER
E , DQP
DQ
BYTE
“a” E
WRITE DRIVER
BW D
DQ D , DQP D
WRITE DRIVER
DQ D , DQP D
WRITE DRIVER
BW C
DQ C, DQP C
WRITE DRIVER
DQ C, DQP C
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQ B , DQP B
WRITE DRIVER
DQ B , DQP B
WRITE DRIVER
OUTPUT
BUFFERS
E
DQ A , DQP A
WRITE DRIVER
DQ A , DQP A
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
SLEEP
CONTROL
Document #: 001-15143 Rev. *D
Page 3 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1482BV25
(4M x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 001-15143 Rev. *D
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
CY7C1480BV25
(2M x 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-Pin TQFP Pinout
Page 4 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations
(continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1480BV25 (2M x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
CE3
BWE
ADSC
ADV
A
NC
CE1
BWC
BWB
A
CE2
BWD
BWA
CLK
GW
ADSP
A
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VDD
OE
VSS
VDD
NC/576M
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
NC/144M
DQPC
DQC
A
A0
CY7C1482BV25 (4M x 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
CE2
BWB
NC
CE3
CLK
ADV
ADSP
A
BWA
ADSC
OE
A
NC
BWE
GW
VSS
VDD
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VSS
VSS
VDDQ
NC/1G
NC
R
NC/576M
NC/144M
A
NC
NC
NC
DQB
VDDQ
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
NC
DQB
DQB
VDD
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
DQB
NC
NC
VDDQ
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
VDDQ
A
DQPA
DQA
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document #: 001-15143 Rev. *D
Page 5 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Pin Configurations
(continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1486BV25 (1M × 72)
1
2
3
4
5
6
A
DQG
DQG
A
CE2
B
DQG
DQG
BWSC
BWSG NC/288M
C
DQG
DQG
BWSH
BWSD NC/144M CE1
D
DQG
DQG
VSS
NC
NC/1G
OE
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
F
DQC
DQC
VSS
VSS
VSS
G
DQC
DQC
VDDQ
VDDQ
H
DQC
DQC
VSS
J
DQC
DQC
K
NC
L
ADSP ADSC
7
ADV
8
9
10
11
CE3
A
DQB
DQB
BWSB
BWSF
DQB
DQB
NC/576M BWSE
BWSA
DQB
DQB
NC
VSS
DQB
DQB
VDD
VDDQ
VDDQ
DQPF
DQPB
NC
VSS
VSS
VSS
DQF
DQF
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
A
A
A
A
A
A
A
DQE
DQE
V
DQD
DQD
A
A
A
A1
A
A
A
DQE
DQE
W
DQD
DQD
TMS
TDI
TCK
DQE
DQE
Document #: 001-15143 Rev. *D
A
BWE
A0
A
GW
A
TDO
DQPA
DQPE
Page 6 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 1. Pin Definitions
Pin Name
IO
Description
A0, A1, A
InputSynchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:
A0 are fed to the two-bit counter.
BWA, BWB, BWC,
BWD, BWE, BWF,
BWG, BWH
InputSynchronous
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).
BWE
InputSynchronous
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
CLK
InputClock
Clock Input. Captures all synchronous inputs to the device. Also increments the burst counter
when ADV is asserted LOW during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
CE2
InputSynchronous
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external
address is loaded.
CE3
InputSynchronous
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
OE
InputAsynchronous
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
InputSynchronous
Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin must be LOW
or left floating. ZZ pin has an internal pull down.
DQs, DQPs
IOSynchronous
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.
VDD
Power Supply
Power Supply Inputs to the Core of the Device.
VSS
VSSQ[2]
VDDQ
Ground
IO Ground
Ground for the Core of the Device.
Ground for the IO Circuitry.
IO Power Supply Power Supply for the IO Circuitry.
Note
2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
Document #: 001-15143 Rev. *D
Page 7 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 1. Pin Definitions (continued)
Pin Name
MODE
TDO
IO
Description
Input Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or
left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
JTAG Serial
Output
Synchronous
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, this pin must be disconnected. This pin is not available on TQFP packages.
TDI
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TMS
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be disconnected or connected to VDD. This pin is not available on
TQFP packages.
TCK
JTAG Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
supports secondary cache in systems using either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
Document #: 001-15143 Rev. *D
propagate through the output register and onto the data bus
within 3.0 ns (250-MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the BWE and BWX signals control the write operation.
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
provides Byte Write capability that is described in the “Truth
Table for Read/Write” on page 11. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BWX) input,
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remain unaltered. A synchronous
self-timed write mechanism is provided to simplify the write
operations.
Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is
a common IO device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE.
Page 8 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BWX) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered write accesses need a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The ZZ input pin is asynchronous. Asserting ZZ places the
SRAM in a power conservation “sleep” mode. Two clock cycles
are required to enter into or exit from this “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the “sleep” mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the “sleep” mode. CE1, CE2, CE3,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is
a common IO device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE.
Burst Sequences
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed to
support processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Table 2. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
00
11
10
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
10
01
00
Table 3. Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep Mode Standby Current
ZZ > VDD – 0.2V
120
mA
tZZS
Device Operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ Recovery Time
ZZ < 0.2V
tZZI
ZZ Active to Sleep Current
This parameter is sampled
tRZZI
ZZ Inactive to Exit Sleep Current
This parameter is sampled
Document #: 001-15143 Rev. *D
2tCYC
ns
2tCYC
0
ns
ns
Page 9 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 4. Truth Table
The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows.[3, 4, 5, 6, 7]
Operation
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
WRITE
OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
L-H
Tri-State
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H
Tri-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
Tri-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
Tri-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
Tri-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
Tri-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Notes
3. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a do not care for
the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document #: 001-15143 Rev. *D
Page 10 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 5. Truth Table for Read/Write
The read-write truth table for the CY7C1480BV25 follows.[5]
Function (CY7C1480BV25)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
H
L
H
H
H
L
Write Byte B – (DQB and DQPB)
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Table 6. Truth Table for Read/Write
The read-write truth table for the CY7C1482BV25 follows.[5]
Function (CY7C1482BV25)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)
H
L
H
L
Write Byte B – (DQB and DQPB)
H
L
L
H
Write Bytes B, A
H
L
L
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Table 7. Truth Table for Read/Write
The read-write truth table for the CY7C1486BV25 follows.[8]
Function (CY7C1486BV25)
GW
BWE
BWX
Read
H
H
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)
H
L
L
Write All Bytes
H
L
All BW = L
Write All Bytes
L
X
X
Note
8. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be
enabled at the same time for a supplied write.
Document #: 001-15143 Rev. *D
Page 11 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incorporates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V IO logic levels.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The
CY7C1480BV25/CY7C1482BV25/CY7C1486BV25
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram.
TDI is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant
bit (MSB) of any register. (See TAP Controller Block Diagram.)
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull up resistor. TDO must be left unconnected.
At power up, the device comes up in a reset state, which does
not interfere with the operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine. The output changes on the falling
edge of TCK. TDO is connected to the least significant bit (LSB)
of any register. (See TAP Controller State Diagram.)
Figure 3. TAP Controller Block Diagram
Figure 2. TAP Controller State Diagram
0
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
Bypass Register
0
2 1 0
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
1
TDI
0
1
CAPTURE-DR
Selection
Circuitry
0
x . . . . . 2 1 0
SHIFT-IR
1
0
Boundary Scan Register
1
EXIT1-DR
1
EXIT1-IR
0
1
0
TCK
PAUSE-DR
0
PAUSE-IR
0
TM S
1
0
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
TDO
Identification Register
0
SHIFT-DR
Selection
Circuitry
31 30 29 . . . 2 1 0
CAPTURE-IR
0
Instruction Register
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document #: 001-15143 Rev. *D
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction register. Data is
serially loaded into the TDI ball on the rising edge of TCK. Data
is output on the TDO ball on the falling edge of TCK.
Page 12 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the “TAP Controller Block Diagram”
on page 12. At power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register, and the x18 configuration has a 54-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller moves to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the IO ring.
rather, it performs a capture of the IO ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction that is executed
whenever the instruction register is loaded with all zeros.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is in a test logic reset
state.
SAMPLE Z
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High-Z
state.
Identification (ID) Register
SAMPLE/PRELOAD
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 15.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
TAP Instruction Set
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured. Repeatable
results may not be possible.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 16. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
Document #: 001-15143 Rev. *D
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
Page 13 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
BYPASS
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Figure 4. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Description
Min
Max
Unit
20
MHz
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH Time
20
ns
tTL
TCK Clock LOW Time
20
ns
50
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 001-15143 Rev. *D
Page 14 of 31
[+] Feedback
CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
2.5V TAP AC Test Conditions
Figure 5. 2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall time .....................................................1 ns
50Ω
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
TDO
Test load termination supply voltage ............................ 1.25V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = –1.0 mA, VDDQ = 2.5V
1.7
V
VOH2
Output HIGH Voltage
IOH = –100 μA, VDDQ = 2.5V
2.1
V
VOL1
Output LOW Voltage
IOL = 1.0 mA, VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA, VDDQ = 2.5V
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
–5
5
μA
Table 8. Identification Register Definitions
CY7C1480BV25
(2M x36)
CY7C1482BV25
(4M x 18)
CY7C1486BV25
(1M x72)
Description
000
000
000
Describes the version number
Device Depth (28:24)
01011
01011
01011
Reserved for internal use
Architecture/Memory
Type(23:18)
000000
000000
000000
Defines memory type and
architecture
Defines width and density
Instruction Field
Revision Number (31:29)
Bus Width/Density(17:12)
100100
010100
110100
Cypress JEDEC ID Code
(11:1)
00000110100
00000110100
00000110100
Enables unique identification of
SRAM vendor
1
1
1
Indicates the presence of an ID
register
ID Register Presence
Indicator (0)
Table 9. Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order – 165FBGA
73
54
-
-
-
112
Boundary Scan Order – 209BGA
Note
11. All voltages refer to VSS (GND).
Document #: 001-15143 Rev. *D
Page 15 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Table 10. Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the IO ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
010
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Table 11. Boundary Scan Exit Order (2M x 36)
Bit #
165-Ball ID
Bit #
165-Ball ID
Bit #
1
2
165-Ball ID
Bit #
165-Ball ID
C1
21
R3
D1
22
P2
41
L10
61
B8
42
K11
62
A7
3
E1
23
R4
43
J11
63
B7
4
D2
24
P6
44
K10
64
B6
5
E2
25
R6
45
J10
65
A6
6
F1
26
N6
46
H11
66
B5
7
G1
27
P11
47
G11
67
A5
8
F2
28
R8
48
F11
68
A4
9
G2
29
P3
49
E11
69
B4
10
J1
30
P4
50
D10
70
B3
11
K1
31
P8
51
D11
71
A3
12
L1
32
P9
52
C11
72
A2
73
B2
13
J2
33
P10
53
G10
14
M1
34
R9
54
F10
15
N1
35
R10
55
E10
16
K2
36
R11
56
A10
17
L2
37
N11
57
B10
18
M2
38
M11
58
A9
19
R1
39
L11
59
B9
20
R2
40
M10
60
A8
Document #: 001-15143 Rev. *D
Page 16 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Boundary Scan Exit Order (4M x 18)
Bit #
165-Ball ID
Bit #
165-Ball ID
Bit #
165-Ball ID
1
D2
19
R8
37
C11
2
E2
20
P3
38
A11
3
F2
21
P4
39
A10
4
G2
22
P8
40
B10
5
J1
23
P9
41
A9
6
K1
24
P10
42
B9
7
L1
25
R9
43
A8
8
M1
26
R10
44
B8
9
N1
27
R11
45
A7
10
R1
28
M10
46
B7
11
R2
29
L10
47
B6
12
R3
30
K10
48
A6
13
P2
31
J10
49
B5
14
R4
32
H11
50
A4
15
P6
33
G11
51
B3
16
R6
34
F11
52
A3
17
N6
35
E11
53
A2
18
P11
36
D11
54
B2
Document #: 001-15143 Rev. *D
Page 17 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Boundary Scan Exit Order (1M x 72)
Bit #
209-Ball ID
Bit #
209-Ball ID
Bit #
209-Ball ID
Bit #
209-Ball ID
1
A1
29
T1
57
V10
85
C11
2
A2
30
T2
58
U11
86
C10
3
B1
31
U1
59
U10
87
B11
4
B2
32
U2
60
T11
88
B10
5
C1
33
V1
61
T10
89
A11
A10
6
C2
34
V2
62
R11
90
7
D1
35
W1
63
R10
91
A9
8
D2
36
W2
64
P11
92
U8
9
E1
37
T6
65
P10
93
A7
10
E2
38
V3
66
N11
94
A5
11
F1
39
V4
67
N10
95
A6
D6
12
F2
40
U4
68
M11
96
13
G1
41
W5
69
M10
97
B6
14
G2
42
V6
70
L11
98
D7
15
H1
43
W6
71
L10
99
K3
16
H2
44
U3
72
P6
100
A8
17
J1
45
U9
73
J11
101
B4
18
J2
46
V5
74
J10
102
B3
19
L1
47
U5
75
H11
103
C3
20
L2
48
U6
76
H10
104
C4
21
M1
49
W7
77
G11
105
C8
22
M2
50
V7
78
G10
106
C9
23
N1
51
U7
79
F11
107
B9
24
N2
52
V8
80
F10
108
B8
25
P1
53
V9
81
E10
109
A4
26
P2
54
W11
82
E11
110
C6
27
R2
55
W10
83
D11
111
B7
28
R1
56
V11
84
D10
112
A3
Document #: 001-15143 Rev. *D
Page 18 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND ........–0.3V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.3V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State ........................................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
2.5V –5%/+5% 2.5V–5% to
VDD
Electrical Characteristics
Over the Operating Range[12, 13]
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
IO Supply Voltage
VOH
Output HIGH Voltage
For 2.5V IO, IOH = –1.0 mA
VOL
Output LOW Voltage
For 2.5V IO, IOL = 1.0 mA
For 2.5V IO
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
2.0
V
0.4
V
V
VIH
Input HIGH
Voltage[12]
For 2.5V IO
1.7
VDD + 0.3V
VIL
Input LOW Voltage[12]
For 2.5V IO
–0.3
0.7
V
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
–5
5
μA
Input Current of MODE
Input = VSS
–30
Input = VDD
Input Current of ZZ
5
Input = VSS
30
μA
5
μA
4.0-ns cycle, 250 MHz
450
mA
5.0-ns cycle, 200 MHz
450
mA
Input = VDD
IDD
[14]
μA
μA
–5
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IOZ
μA
–5
VDD Operating Supply
Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
400
mA
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
200
mA
5.0-ns cycle, 200 MHz
200
mA
6.0-ns cycle, 167 MHz
200
mA
ISB2
Automatic CE
Power Down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f=0
All speeds
120
mA
ISB3
Automatic CE
Power Down
Current—CMOS Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
200
mA
5.0-ns cycle, 200 MHz
200
mA
6.0-ns cycle, 167 MHz
200
mA
Automatic CE
Power Down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speeds
135
mA
ISB1
ISB4
Notes
12. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2).Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2).
13. Power up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
14. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15143 Rev. *D
Page 19 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
CADDRESS
Address Input Capacitance
Test Conditions
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package
Unit
TA = 25°C, f = 1 MHz,
VDD = 2.5V
VDDQ = 2.5V
6
6
6
pF
5
5
5
pF
8
8
8
pF
CDATA
Data Input Capacitance
CCTRL
Control Input Capacitance
CCLK
Clock Input Capacitance
6
6
6
pF
CIO
Input/Output Capacitance
5
5
5
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Test Conditions
100 TQFP
Max
165 FBGA
Max
209 FBGA
Max
Unit
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
24.63
16.3
15.2
°C/W
2.28
2.1
1.7
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 1583Ω
≤ 1 ns
≤ 1 ns
VL = 1.25V
(a)
Document #: 001-15143 Rev. *D
INCLUDING
JIG AND
SCOPE
(b)
(c)
Page 20 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and
Waveforms” on page 20 unless otherwise noted.
Parameter
tPOWER
Description
VDD(Typical) to the first access[15]
250 MHz
Min
Max
200 MHz
Min
Max
167 MHz
Min
Max
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
tCH
Clock HIGH
2.0
2.0
2.4
ns
tCL
Clock LOW
2.0
2.0
2.4
ns
Output Times
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.3
1.3
1.5
ns
tCLZ
Clock to
Low-Z[16, 17, 18]
1.3
1.3
1.5
ns
tCHZ
Clock to
High-Z[16, 17, 18]
3.0
3.0
3.4
ns
tOEV
OE LOW to Output Valid
3.0
3.0
3.4
ns
tOELZ
tOEHZ
OE LOW to Output
Low-Z[16, 17, 18]
OE HIGH to Output
High-Z[16, 17, 18]
3.0
0
3.0
0
3.0
3.4
0
3.0
ns
ns
3.4
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.4
1.4
1.5
ns
tADS
ADSC, ADSP Setup Before CLK Rise
1.4
1.4
1.5
ns
tADVS
ADV Setup Before CLK Rise
1.4
1.4
1.5
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.4
1.4
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.4
1.4
1.5
ns
tCES
Chip Enable Setup Before CLK Rise
1.4
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.4
0.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.4
0.4
0.5
ns
tADVH
ADV Hold After CLK Rise
0.4
0.4
0.5
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.4
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.4
0.4
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.4
0.4
0.5
ns
Hold Times
Notes
15. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated.
16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV
from steady-state voltage.
17. At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document #: 001-15143 Rev. *D
Page 21 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms
Timing for the read cycle is shown in Figure 6.[19]
Figure 6. Read Cycle Timing
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document #: 001-15143 Rev. *D
Page 22 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for the write cycle is shown in Figure 7.[19, 20]
Figure 7. Write Cycle Timing
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document #: 001-15143 Rev. *D
Page 23 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for the read-write cycle is shown in Figure 8.[19, 21, 22]
Figure 8. Read/Write Cycle Timing
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE, BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A5)
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
22. GW is HIGH.
Document #: 001-15143 Rev. *D
Page 24 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Switching Waveforms (continued)
Timing for ZZ mode is shown in Figure 9.[23, 24]
Figure 9. ZZ Mode Timing
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
23. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 001-15143 Rev. *D
Page 25 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
167
Ordering Code
CY7C1480BV25-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1482BV25-167AXC
CY7C1480BV25-167BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-167BZC
CY7C1480BV25-167BZXC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-167BZXC
CY7C1486BV25-167BGC
CY7C1486BV25-167BGXC
CY7C1480BV25-167AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
CY7C1482BV25-167AXI
CY7C1480BV25-167BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-167BZI
CY7C1480BV25-167BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-167BZXI
CY7C1486BV25-167BGI
CY7C1486BV25-167BGXI
200
CY7C1480BV25-200AXC
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
CY7C1482BV25-200AXC
CY7C1480BV25-200BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-200BZC
CY7C1480BV25-200BZXC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-200BZXC
CY7C1486BV25-200BGC
CY7C1486BV25-200BGXC
CY7C1480BV25-200AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
CY7C1482BV25-200AXI
CY7C1480BV25-200BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-200BZI
CY7C1480BV25-200BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1482BV25-200BZXI
CY7C1486BV25-200BGI
CY7C1486BV25-200BGXI
Document #: 001-15143 Rev. *D
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
Page 26 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
250
Ordering Code
CY7C1480BV25-250AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Operating
Range
Commercial
CY7C1482BV25-250AXC
CY7C1480BV25-250BZC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-250BZC
CY7C1480BV25-250BZXC
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1482BV25-250BZXC
CY7C1486BV25-250BGC
CY7C1486BV25-250BGXC
CY7C1480BV25-250AXI
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1482BV25-250AXI
CY7C1480BV25-250BZI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1482BV25-250BZI
CY7C1480BV25-250BZXI
51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1482BV25-250BZXI
CY7C1486BV25-250BGI
CY7C1486BV25-250BGXI
Document #: 001-15143 Rev. *D
51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
Page 27 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams
Figure 10. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 001-15143 Rev. *D
A
51-85050-*B
Page 28 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams
(continued)
Figure 11. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
SEATING PLANE
Document #: 001-15143 Rev. *D
1.40 MAX.
0.36
C
51-85165-*A
Page 29 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Package Diagrams
(continued)
Figure 12. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
Document #: 001-15143 Rev. *D
Page 30 of 31
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CY7C1480BV25
CY7C1482BV25, CY7C1486BV25
Document History Page
Document Title: CY7C1480BV25/CY7C1482BV25/CY7C1486BV25, 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Document Number: 001-15143
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
1024385
See ECN
*A
1562944
See ECN
VKN/KKVTMP New Data Sheet
VKN/AESA
Removed 1.8V IO offering from the data sheet
*B
1897447
See ECN
VKN/AESA
Added footnote 14 related to IDD
*C
2082487
See ECN
VKN
*D
2159486
See ECN
VKN/PYRS
Converted from preliminary to final
Minor Change-Moved to the external web
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15143 Rev. *D
Revised February 29, 2008
Page 31 of 31
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective holders.
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