CY7C1444AV33 CY7C1445AV33 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) • Depth expansion without wait state • 3.3V core power supply • 2.5V/3.3V I/O power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1M x 36/2M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth- expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • CY7C1444AV33, CY7C1445AV33 available in JEDEC-standard lead-free 100-pin TQFP package and lead-free and non-lead-free 165-ball FBGA package • IEEE 1149.1 JTAG-compatible Boundary Scan • “ZZ” Sleep Mode Option Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1444AV33/CY7C1445AV33 operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 3.2 3.4 ns Maximum Operating Current 475 425 375 mA Maximum CMOS Standby Current 120 120 120 mA Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05352 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 22, 2006 [+] Feedback CY7C1444AV33 CY7C1445AV33 1 Logic Block Diagram – CY7C1444AV33 (1M x 36) ADDRESS REGISTER A0,A1,A 2 A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC CLR Q0 ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQD,DQPD BYTE WRITE DRIVER BWC DQc,DQPC BYTE WRITE REGISTER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE REGISTER DQB,DQPB BYTE WRITE DRIVER BWB GW CE1 CE2 CE3 OE ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD E DQA,DQPA BYTE WRITE DRIVER DQA,DQPA BYTE WRITE REGISTER BWA BWE MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1445AV33 (2M x 18) A0, A1, A ADDRESS REGISTER 2 MODE ADV CLK A[1:0] Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP BWB BWA BWE GW CE1 CE2 CE3 DQB , DQPB BYTE WRITE DRIVER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BYTE WRITE DRIVER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs, DQPA DQPB E INPUT REGISTERS OE ZZ SLEEP CONTROL Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Pin Configurations (continued) NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1445AV33 (2M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05352 Rev. *E A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA MODE A A A A A1 A0 NC/72M A VSS VDD CY7C1444AV33 (1M X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC/72M A VSS VDD A A A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP Pinout Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1444AV33 (1M x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M A CE1 BWC BWB CE3 BWE ADSC ADV A NC R NC/144M A CE2 BWD BWA CLK NC/576M VDDQ VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD A NC DQC GW VSS VSS ADSP DQPC DQC VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC/72M A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A CY7C1445AV33 (2M x 18) 1 2 A B C D E F G H J K L M N P NC/288M A NC/144M R 3 4 5 BWB CE3 A CE1 CE2 NC 6 NC BWA NC NC NC DQB VDDQ VDDQ VSS VDD NC DQB VDDQ NC DQB NC NC DQB DQB NC NC DQB 7 8 9 10 11 A CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC/1G NC DQPA DQA VDD VSS VSS VSS VDD VDDQ NC DQA VDDQ VDD VSS VSS VSS VDD DQA VDD VDD VDD VSS VSS ‘VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ NC VDDQ NC VDDQ NC NC DQA DQA ZZ NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC/72M A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A Document #: 38-05352 Rev. *E NC/576M A Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Pin Definitions (continued) Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter.. BWA, BWB BWC, BWD InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. ADSC InputSynchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ InputAsynchronous ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPs I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. VDD Power Supply Power supply inputs to the core of the device. VSS Ground VSSQ VDDQ MODE TDO I/O Ground Ground for the core of the device. Ground for the I/O circuitry. I/O Power Supply Power supply for the I/O circuitry. InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Pin Definitions (continued) Name I/O Description TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAGClock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M, NC/1G – No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are address expansion pins are not internally connected to the die. Functional Overview outputs are controlled by the OE signal. Consecutive single read cycles are supported. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1444AV33/CY7C1445AV33 is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. The CY7C1444AV33/CY7C1445AV33 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the Document #: 38-05352 Rev. *E Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1444AV33/CY7C1445AV33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1444AV33/CY7C1445AV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Because the CY7C1444AV33/CY7C1445AV33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Interleaved Burst Address Table (MODE = Floating or VDD) Burst Sequences The CY7C1444AV33/CY7C1445AV33 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Document #: 38-05352 Rev. *E Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. Max. 100 2tCYC 2tCYC 2tCYC 0 Unit mA ns ns ns ns Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Truth Table[2, 3, 4, 5, 6, 7] Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV Deselect Cycle, Power Down Operation None H X X L X L X WRITE OE CLK X X L-H Tri-State DQ Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State External L H L L L X X X L L-H Q Read Cycle, Begin Burst Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Partial Truth Table for Read/Write[4,8] GW BWE BWD BWC BWB BWA Read Function (CY7C1444AV33) H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write[4,8] GW BWE BWB BWA Read H H X X Read H L H H Write Byte A – (DQA and DQPA) H L H L Write Byte B – (DQB and DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X Function (CY7C1445AV33) Note: 8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test Data-In (TDI) The CY7C1444AV33/CY7C1445AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Disabling the JTAG Feature Test Data-Out (TDO) It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) The CY7C1444AV33/CY7C1445AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with the 1149.1 IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. TAP Controller Block Diagram 0 TAP Controller State Diagram 1 Bypass Register TEST-LOGIC RESET 2 1 0 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 Selection Circuitry TDO Identification Register CAPTURE-IR x . . . . . 2 1 0 Boundary Scan Register SHIFT-IR 1 Instruction Register 31 30 29 . . . 2 1 0 0 SHIFT-DR 0 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-IR 1 TCK TMS 0 PAUSE-DR TAP CONTROLLER 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 TDI 0 1 CAPTURE-DR 0 0 1 Selection Circuitry 0 UPDATE-IR 1 0 Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Document #: 38-05352 Rev. *E TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. IDCODE EXTEST The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. EXTEST OUTPUT BUS TRI-STATE BYPASS IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit# 89 (for 165-FBGA packages).When this scan cell, called the Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. “extest output bus tri-state”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. Reserved This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[9,10] Parameter Description Min. Max. Unit 20 MHz Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 ns 0 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes: 9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.5V 1.25V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[11] Parameter Description Test Conditions Min. Max. Unit VOH1 Output HIGH Voltage IOH = –1.0 mA, VDDQ = 2.5V 2.0 V VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 VOL1 Output LOW Voltage IOL = 8.0 mA, VDDQ = 3.3V 0.4 V IOL = 1.0 mA, VDDQ = 2.5V 0.4 V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage VDDQ = 3.3V VIL Input LOW Voltage IX Input Load Current GND < VIN < VDDQ IOH = –4.0 mA, VDDQ = 3.3V 2.4 VDDQ = 3.3V VDDQ = 2.5V V V 0.2 V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.5 0.7 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA Note: 11. All voltages referenced to VSS (GND). Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Identification Register Definitions Instruction Field Revision Number (31:29) CY7C1444AV33 CY7C1445AV33 000 000 Description Describes the version number. Device Depth (28:24)[12] 01011 01011 Reserved for Internal Use Architecture/Memory Type (23:18) 000110 000110 Defines memory type and architecture Defines width and density Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) 100111 010111 00000110100 00000110100 1 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (x18) Bit Size(X36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note: 12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 165-ball FBGA Boundary Scan Order[13,14] CY7C1444AV33 (1M x 36), CY7C1445AV33 (2M x 18) Bit # Ball ID Bit # Ball ID 1 26 E11 N6 2 27 D11 N7 3 N10 28 G10 4 P11 29 F10 5 P8 30 E10 6 R8 31 D10 7 R9 32 C11 8 P9 33 A11 9 P10 34 B11 10 R10 35 A10 11 R11 36 B10 12 H11 37 A9 13 N11 38 B9 14 M11 39 C10 15 L11 40 A8 16 K11 41 B8 17 J11 42 A7 18 M10 43 B7 19 L10 44 B6 20 K10 45 A6 21 J10 46 B5 22 H9 47 A5 23 H10 48 A4 24 G11 49 B4 25 F11 50 B3 Bit # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 Bit # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal Notes: 13. Balls which are NC (No Connect) are Pre-Set LOW. 14. Bit# 89 is Pre-Set HIGH. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD Range DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD VDDQ 3.3V –5%/+10% 2.5V –5% to VDD Electrical Characteristics Over the Operating Range [15, 16] DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA VIH Input HIGH Voltage[15] for 3.3V I/O VIL Input LOW Voltage[15] for 2.5V I/O IX Input Leakage Current except ZZ and MODE GND ≤ VI ≤ VDDQ Min. 3.135 3.6 V 3.135 VDD V for 2.5V I/O 2.375 2.625 for 3.3V I/O, IOH = −4.0 mA 2.4 for 2.5V I/O,I OH = −1.0 mA 2.0 V V V 0.4 V 0.4 V 2.0 VDD + 0.3V V for 2.5V I/O 1.7 VDD + 0.3V V for 3.3V I/O –0.3 0.8 V –0.3 0.7 V –5 5 µA µA –30 Input Current of MODE Input = VSS Input = VDD 5 Input = VSS µA µA –5 30 µA 5 µA 4-ns cycle, 250 MHz 475 mA 5-ns cycle, 200 MHz 425 mA 6-ns cycle, 167 MHz 375 mA All speeds 225 mA All speeds 120 mA VDD = Max, Device Deselected, or All Speeds Automatic CE Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V Current—CMOS Inputs f = fMAX = 1/tCYC VDD = Max, Device Deselected, Automatic CE All Speeds Power-down VIN ≥ VIH or VIN ≤ VIL, f = 0 Current—TTL Inputs 200 mA 135 mA Input = VDD IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC ISB2 Automatic CE VDD = Max, Device Deselected, Power-down VIN ≤ 0.3V or VIN > VDDQ – 0.3V, Current—CMOS Inputs f = 0 ISB3 ISB4 Unit for 3.3V I/O for 2.5V I/O, IOL = 1.0 mA Input Current of ZZ Max. –5 Notes: 15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 16. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Capacitance[17] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance 100 TQFP Max. 165 FBGA Max. Unit 6.5 7 pF 3 7 pF 5.5 6 pF 100 TQFP Package 165 FBGA Package Unit 25.21 20.8 °C/W 2.28 3.2 °C/W TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V Thermal Resistance[17] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω 10% 90% 10% 90% GND 5 pF R = 351Ω ≤ 1 ns ≤ 1 ns VT = 1.5V INCLUDING JIG AND SCOPE (a) (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT 10% R = 1538Ω VT = 1.25V INCLUDING JIG AND SCOPE 90% 10% 90% GND 5 pF (a) ALL INPUT PULSES VDDQ OUTPUT RL = 50Ω Z0 = 50Ω (b) ≤ 1 ns ≤ 1 ns (c) Note: 17. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Switching Characteristics Over the Operating Range[22, 23] –250 Parameter tPOWER Description Min. [18] VDD(Typical) to the first Access –200 Max. Min. –167 Max. Min. Max. Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5 6 ns tCH Clock HIGH 1.5 2.0 2.4 ns tCL Clock LOW 1.5 2.0 2.4 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [19, 20, 21] 2.6 1.0 3.2 1.5 1.5 ns tCLZ Clock to Low-Z Clock to High-Z[19, 20, 21] 2.6 3.0 3.4 ns tOEV OE LOW to Output Valid 2.6 3.0 3.4 ns tOELZ tOEHZ OE LOW to Output OE HIGH to Output High-Z[19, 20, 21] 1.3 ns tCHZ Low-Z[19, 20, 21] 1.0 3.4 0 1.5 0 2.6 ns 0 3.0 ns 3.4 ns Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.4 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 1.2 1.4 1.5 ns tADVS ADV Set-up Before CLK Rise 1.2 1.4 1.5 ns tWES GW, BWE, BWX Set-up Before CLK Rise 1.2 1.4 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.2 1.4 1.5 ns tAH Address Hold After CLK Rise 0.3 0.4 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.5 ns tADVH ADV Hold After CLK Rise 0.3 0.4 0.5 ns Hold Times tWEH GW, BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.4 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns Notes: 18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 23. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Switching Waveforms Read Cycle Timing[24] tCYC CLK tCH tADS tCL tADH ADSP tADS tADH ADSC tAS ADDRESS tAH A1 A2 tWES A3 Burst continued with new base address tWEH GW, BWE,BW X Deselect cycle tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data Out (DQ) High-Z CLZ t OEHZ Q(A1) tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t CO Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note: 24. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Switching Waveforms Write Cycle Timing[24, 25] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS Data in (D) High-Z t OEHZ t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 25. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Switching Waveforms Read/Write Cycle Timing[24, 26, 27] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO Data In (D) tOELZ High-Z tCLZ Data Out (Q) tDH High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) Q(A2) Q(A4) Q(A4+2) BURST READ Single WRITE DON’T CARE Q(A4+1) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 26. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 27. GW is HIGH. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Switching Waveforms ZZ Mode Timing[28,29] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 28. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 29. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1444AV33-167AXC Package Diagram Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Operating Range Commercial CY7C1445AV33-167AXC CY7C1444AV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-167BZC CY7C1444AV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-167BZXC CY7C1444AV33-167AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1445AV33-167AXI CY7C1444AV33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-167BZI CY7C1444AV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-167BZXI 200 CY7C1444AV33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1445AV33-200AXC CY7C1444AV33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-200BZC CY7C1444AV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-200BZXC CY7C1444AV33-200AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial CY7C1445AV33-200AXI CY7C1444AV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-200BZI CY7C1444AV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-200BZXI 250 CY7C1444AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1445AV33-250AXC CY7C1444AV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-250BZC CY7C1444AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-250BZXC CY7C1444AV33-250AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1445AV33-250AXI CY7C1444AV33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1445AV33-250BZI CY7C1444AV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1445AV33-250BZXI Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Package Diagrams 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 51-85050-*B 1.00 REF. DETAIL Document #: 38-05352 Rev. *E A Page 8 of 27 [+] Feedback CY7C1444AV33 CY7C1445AV33 Package Diagrams PIN 1 CORNER BOTTOM VIEW 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 51-85165-*A 1.40 MAX. 0.36 C i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05352 Rev. *E Page # of 26 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1444AV33 CY7C1445AV33 Document History Page Document Title: CY7C1444AV33/CY7C1445AV33 36-Mbit (1M x 36/2Mx 18) Pipelined DCD Sync SRAM Document Number: 38-05352 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 124419 03/04/03 CGM New data sheet *A 254910 See ECN SYT Part number changed from previous revision. New and old part number differ by the letter “A” Modified Functional Block diagrams Modified switching waveforms Added boundary scan information Added footnote #13 (32-Bit Vendor I.D Code changed) Added IDD, IX and ISB values in DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA package Changed 165 FBGA package from BB165 (15 x 17 x 1.20 mm) to BB165C (15 x 17 x 1.40 mm) *B 303533 See ECN SYT Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200 and 167 Mhz respectively Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167 Mhz respectively Changed ISB2 from 80 mA to 100 mA for all frequencies Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 MHz respectively Changed ISB4 from 100 mA to 110 mA for all frequencies Changed CIN, CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 MHz Speed Bin Added lead-free information for 100-pin TQFP and 165 FBGA packages *C 331778 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Changed CIN, CCLK and CI/O to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grades Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by Shading and Unshading MPNs as per availability *D 417509 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respectively and also Changed IX current value in ZZ from –30 & 5 µA to –5 & 30 µA respectively on page# 16 Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B *E 473229 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. Document #: 38-05352 Rev. *E Page 8 of 27 [+] Feedback