DM5490/DM7490A, DM7493A Decade and Binary Counters General Description Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the 90A and divideby-eight for the 93A. All of these counters have a gated zero reset and the 90A also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade or four-bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the 90A counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA. Features Y Y Typical power dissipation Ð 90A 145 mW Ð 93A 130 mW Count frequency 42 MHz Connection Diagrams Dual-In-Line Package TL/F/6533 – 1 Order Number DM5490J, DM5490W or DM7490AN See NS Package Number J14A, N14A or W14B Dual-In-Line Package TL/F/6533 – 2 Order Number DM7493AN See NS Package Number N14A C1995 National Semiconductor Corporation TL/F/6533 RRD-B30M105/Printed in U. S. A. DM5490/DM7490A, DM7493A Decade and Binary Counters July 1992 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 DM74 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol DM5490 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 5) A tW Pulse Width (Note 5) DM7490A Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V 0.8 0.8 V b 0.8 b 0.8 mA 16 0 32 B 0 16 A 15 16 0 32 0 16 B 30 30 15 15 Reset Release Time (Note 5) TA Free Air Operating Temperature mA MHz 15 Reset tREL V 25 ns 25 b 55 125 ns 0 70 §C ’90A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VOH High Level Output Voltage VCC e Min, II e b12 mA VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max (Note 4) II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max VI e 2.7V IIL IOS ICC Low Level Input Current VCC e Max VI e 0.4V Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max (Note 3) 2.4 Typ (Note 1) Max Units b 1.5 V 3.4 0.2 V 0.4 V 1 mA A 80 Reset 40 B 120 A b 3.2 Reset b 1.6 B b 4.8 DM54 b 20 b 57 DM74 b 18 b 57 29 42 mA mA mA mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded. Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 5: TA e 25§ C and VCC e 5V. 2 ’90A Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter RL e 400X CL e 15 pF From (Input) To (Output) Min fMAX Maximum Clock Frequency A to QA 32 B to QB 16 Units Max MHz tPLH Propagation Delay Time Low to High Level Output A to QA 16 ns tPHL Propagation Delay Time High to Low Level Output A to QA 18 ns tPLH Propagation Delay Time Low to High Level Output A to QD 48 ns tPHL Propagation Delay Time High to Low Level Output A to QD 50 ns tPLH Propagation Delay Time Low to High Level Output B to QB 16 ns tPHL Propagation Delay Time High to Low Level Output B to QB 21 ns tPLH Propagation Delay Time Low to High Level Output B to QC 32 ns tPHL Propagation Delay Time High to Low Level Output B to QC 35 ns tPLH Propagation Delay Time Low to High Level Output B to QD 32 ns tPHL Propagation Delay Time High to Low Level Output B to QD 35 ns tPLH Propagation Delay Time Low to High Level Output SET-9 to QA, QD 30 ns tPHL Propagation Delay Time High to Low Level Output SET-9 to QB, QC 40 ns tPHL Propagation Delay Time High to Low Level Output SET-0 Any Q 40 ns 3 Recommended Operating Conditions Symbol DM7493A Parameter Units Min Nom Max 4.75 5 5.25 V 0.8 V VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b 0.8 mA IOL Low Level Output Current 16 mA fCLK Clock Frequency (Note 5) A 0 32 B 0 16 Pulse Width (Note 5) A 15 B 30 Reset 15 tW 2 V tREL Reset Release Time (Note 5) 25 TA Free Air Operating Temperature 0 MHz ns ns 70 §C ’93A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max (Note 4) II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max VI e 2.4V IIL Low Level Input Current VCC e Max VI e 0.4V IOS Short Circuit Output Current VCC e Max (Note 2) ICC Supply Current VCC e Max (Note 3) 2.4 Typ (Note 1) Max Units b 1.5 V 3.4 0.2 V 0.4 V 1 mA Reset 40 A 80 B 80 Reset b 1.6 A b 3.2 B b 3.2 b 18 26 mA mA b 57 mA 39 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: ICC is measured with all outputs open, both R0 inputs grounded following momentary connection to 4.5V and all other inputs grounded. Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 5: TA e 25§ C and VCC e 5V. 4 ’93A Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter RL e 400X CL e 15 pF From (Input) To (Output) Min fMAX Maximum Clock Frequency A to QA 32 B to QB 16 Units Max MHz tPLH Propagation Delay Time Low to High Level Output A to QA 16 ns tPHL Propagation Delay Time High to Low Level Output A to QA 18 ns tPLH Propagation Delay Time Low to High Level Output A to QD 70 ns tPHL Propagation Delay Time High to Low Level Output A to QD 70 ns tPLH Propagation Delay Time Low to High Level Output B to QB 16 ns tPHL Propagation Delay Time High to Low Level Output B to QB 21 ns tPLH Propagation Delay Time Low to High Level Output B to QC 32 ns tPHL Propagation Delay Time High to Low Level Output B to QC 35 ns tPLH Propagation Delay Time Low to High Level Output B to QD 51 ns tPHL Propagation Delay Time High to Low Level Output B to QD 51 ns tPHL Propagation Delay Time High to Low Level Output SET-0 to Any Q 40 ns 5 Function Tables (Note D) 90A BCD Bi-Quinary (5-2) (See Note B) 90A BCD Count Sequence (See Note A) Outputs Count 0 1 2 3 4 5 6 7 8 9 Outputs Count QD QC QB QA L L L L L L L L H H L L L L H H H H L L L L H H L L H H L L L H L H L H L H L H 0 1 2 3 4 5 6 7 8 9 Reset Inputs QD QC QB L L L L L H H H H H L L L L H L L L L H L L H H L L L H H L L H L H L L H L H L R9(1) R9(2) QD H H X X L L X H H X L X X L L X H X L X L X L H L X L X L L H QC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QD QC QB QA L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H 93A Reset/Count Function Table Outputs R0(2) Outputs Count QA 90A Reset/Count Function Table R0(1) 93A Count Sequence (See Note C) QB L L L L L L COUNT COUNT COUNT COUNT Reset Inputs Outputs QA R0(1) R0(2) QD QC QB QA L L H H L X H X L L L L L COUNT COUNT Note A: Output QA is connected to input B for BCD count. Note B: Output QD is connected to input A for bi-quinary count. Note C: Output QA is connected to input B. Note D: H e High Level, L e Low Level, X e Don’t Care. 6 Logic Diagrams 90A 93A TL/F/6533 – 4 TL/F/6533 – 3 The J and K inputs shown without connection are for reference only and are functionally at a high level. 7 8 Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM5490J NS Package Number J14A 14-Lead Molded Dual-In-Line Package (N) Order Number DM7490AN or DM7493AN NS Package Number N14A 9 DM5490/DM7490A, DM7493A Decade and Binary Counters Physical Dimensions inches (millimeters) (Continued) 14-Lead Ceramic Flat Package (W) Order Number DM5490W NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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