NSC DP83251V

DP83251/55 PLAYER TM Device
(FDDI Physical Layer Controller)
General Description
Features
The DP83251/DP83255 PLAYER device implements one
Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9.5 Standard. The PLAYER device contains NRZ/NRZI and 4B/5B encoders and
decoders, serializer/deserializer, framing logic, elasticity
buffer, line state detector/generator, link error detector, repeat filter, smoother, and configuration switch.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Low power CMOS-BIPOLAR process
Single 5V supply
Full duplex operation
Separate management interface (Control Bus)
Parity on PHY-MAC Interface and Control Bus Interface
On-chip configuration switch
Internal and external loopback
DP83251 for single attach stations
DP83255 for dual attach stations
TL/F/10386 – 1
FIGURE 1-1. FDDI Chip Set Block Diagram
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
BSITM , BMACTM , PLAYERTM , CDDTM and CRDTM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/10386
RRD-B30M105/Printed in U. S. A.
DP83251/DP83255 PLAYER Device (FDDI Physical Layer Controller)
February 1991
Table of Contents
1.0
FDDI CHIP SET OVERVIEW
7.0
ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
7.2 Recommended Operating Conditions
7.3 DC Electrical Charcteristics
7.4 AC Electrical Charcteristics
7.5 Test Circuits
8.0 DETAILED DESCRIPTIONS
8.1 Framing Hold Rules
8.2 Noise Events
8.3 Link Errors
8.4 Repeat Filter
8.5 Smoother
8.6 National Byte-wide Code for PHY-MAC Interface
2.0
ARCHITECTURE DESCRIPTION
2.1 Overview
2.2 Interfaces
3.0 FUNCTIONAL DESCRIPTION
3.1 Receiver Block
3.2 Transmitter Block
3.3 Configuration Switch
4.0 MODES OF OPERATION
4.1 Run Mode
4.2 Stop Mode
4.3 Loopback Mode
4.4 Cascade Mode
5.0 REGISTERS
6.0 PIN DESCRIPTIONS
6.1 DP83251
6.2 DP83255
2
1.0 FDDI Chip Set Overview
National Semiconductor’s FDDI chip set consists of five
components as shown in Figure 1-1 . For more information
on the other devices of the chip set, consult the appropriate
datasheets and application notes.
DP83231 CRD TM Device
Clock Recovery Device
DP83261 BMAC TM Device
Media Access Controller
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.
The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9.5
MAC Standard.
Features
Features
# PHY Layer loopback test
# Crystal controlled
# Clock locks in less than 85 ms
# All of the standard defined ring service options
# Full duplex operation with through parity
DP83241 CDD TM Device
Clock Distribution Device
# Supports Individual, Group, Short, Long, and External
Supports all FDDI Ring Scheduling Classes (Synchronous, Asynchronous, etc.)
Addressing
#
#
#
#
From a 12.5 MHz reference, the Clock Distribution Device
synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clocks
required by the BSI, BMAC and PLAYER devices.
DP83251/55 PLAYER TM Device
Physical Layer Controller
Generates Beacon, Claim, and Void frames internally
Extensive ring and station statistic gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control their operation
# Multi-frame streaming interface
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9.5 Standard.
DP83265 BSI TM Device
System Interface
The BSI device implements the interface between the
BMAC device and a host system.
Features
#
#
#
#
#
#
#
#
4B/5B encoders and decoders
Framing logic
Elasticity Buffer, Repeat Filter and Smoother
Line state detector/generator
Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control their operation
In addition, the DP83255 contains an additional
PHYÐData.request and PHYÐData.indicate port required
for concentrators and dual attach stations.
Features
#
#
#
#
#
#
#
#
#
#
#
3
32-bit wide Address/Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to low cost DRAMs or directly to system bus
Provides 2 Output and 3 Input Channels
Supports Header/Info splitting
Efficient data structures
Programmable Big or Little Endian alignment
Full duplex data path allows transmission to self
Confirmation status batching services
Receive frame filtering services
Operates from 12.5 MHz to 25 MHz synchronously with
the host system
2.0 Architecture Description
2.1 OVERVIEW
# Generates Idle, Master, Halt, Quiet or other user defined
The PLAYER device is comprised of four blocks: Receiver,
Transmitter, Configuration Switch and Control Bus Interface
as shown in Figure 2-1 .
# Converts the data stream from NRZ to NRZI format
symbol pairs upon request.
ready for transmission, if necessary.
# Provides smoothing function when necessary.
Receiver
During normal operation, the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Recovery Device (DP83231). During the Internal Loopback
mode of operation, the Receiver Block accepts data from
the Transmitter Block as inputs.
The Receiver Block performs the following operations:
During normal operation, the Transmitter Block presents serial data to the fiber optic transmitter. While in the External
Loopback mode, the Transmitter Block presents serial data
to the Clock Recovery Device.
Control Bus Interface
The Control Bus Interface allows a user to:
# Program the Configuration Switch.
# Enable/disable functions within the Transmitter and Re-
# Converts the incoming data stream from NRZI to NRZ, if
necessary
ceiver Blocks (i.e., NRZ/NRZI Encoder, Smoother, PHY
Request Data Parity, Line State Generation, Symbol Pair
Injection, NRZ/NRZI Decoder, Cascade Mode, etc.).
The Control Bus Interface also performs the following functions:
# Decodes the data from 5B to 4B coding
# Converts the serial bit stream into 10-bit bytes
# Compensates for the differences between the upstream
and local clocks
# Decodes Line States
# Detects link errors
# Monitors Line States received
# Monitors link errors detected by the Receiver Block
# Monitors other error conditions
Finally, the Receiver Block presents data symbol pairs
(bytes) to the Configuration Switch Block
2.2 INTERFACES
The PLAYER device connects to external components via 5
functional interfaces: Serial Interface, PHY Port Interface,
Control Bus Interface, Clock Interface, and the Miscellaneous Interface.
Configuration Switch
An FDDI station may be in one of three configurations: Isolate, Wrap or Thru. The Configuration Switch supports these
configurations by switching the transmitted and received
data paths between the PLAYER and BMAC devices.
The configuration switching is performed internally, therefore no external logic is required for this function.
Serial Interface
The Serial Interface connects the PLAYER device to a fiber
optic transmitter (FOTX) and the Clock Recovery Device
(DP83231).
Transmitter
The Transmiter Block accepts 10-bit bytes from the Configuration Switch.
The Transmitter Block performs the following operations:
# Encodes the data from 4B to 5B coding.
# Filters out code violations from the data stream.
TL/F/10386 – 2
FIGURE 2-1. PLAYER Device Block Diagram
4
2.0 Architecture Description
3.0 Functional Description
(Continued)
The PLAYER Device is comprised of four blocks: Receiver,
Transmitter, Configuration Switch and Control Bus Interface.
PHY Port Interface
The PHY Port Interface connects the PLAYER device to
one or more BMAC devices and/or PLAYER devices. Each
PHY Port Interface consists of two byte-wide-interfaces,
one for PHY Request data input to the PLAYER device and
one for the PHY Indicate data output of the PLAYER device.
Each byte-wide interface consists of a parity bit (odd parity),
a control bit, and two 4-bit symbols.
The DP8355 PLAYER device has two PHY Port Interfaces
and the DP83251 has only one PHY Port Interface.
3.1 RECEIVER BLOCK
During normal operation, the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Recovery Device (DP83231). During the Internal Loopback
mode of operation, the Receiver Block accepts data from
the Transmitter Block as input.
The Receiver Block performs the following operations:
# Converts the incoming data stream from NRZI to NRZ, if
necessary
Control Bus Interface
The Control Bus Interface connects the PLAYER device to
a wide variety of microprocessors and microcontrollers. The
Control Bus is an asynchronous interface which provides
access to 32 8-bit registers.
# Decodes the data from 5B to 4B coding
# Converts the serial bit stream into National byte-wide
code
# Compensates for the differences between the upstream
and local clocks
Clock Interface
The Clock Interface consists of 12.5 MHz and 125 MHz
clocks used by the PLAYER device.
The clocks are generated by either the Clock Distribution
Device (CDD device) or the Clock Recovery Device (CRD
device).
# Decodes Line States
# Detects link errors
Finally, the Receiver Block presents data symbol pairs to
the Configuration Switch Block.
The Receiver Block consists of the following functional
blocks:
NRZI to NRZ Decoder
Shift Register
Framing Logic
Symbol Decoder
Line State Detector
Elasticity Buffer
Link Error Detector
See Figure 3-1 .
Miscellaneous Interface
The Miscellaneous Interface consists of:
#
#
#
#
A reset signal
User definable sense signals
User definable enable signals
Synchronization for cascaded PLAYER devices (a highperformance non-FDDI mode)
# CMOS power and ground, and ECL ground and power
TL/F/10386 – 3
FIGURE 3-1. Receiver Block Diagram
5
3.0 Functional Description (Continued)
Idle Line State
NRZI TO NRZ DECODER
The NRZI to NRZ Decoder converts Non-Return-To-ZeroInvert-On-Ones data to Non-Return-To-Zero data.
This function can be enabled and disabled through bit 7
(RNRZ) of the Mode Register (MR). When the bit is cleared,
it converts the incoming bit stream from NRZI to NRZ.
When the bit is set the incoming NRZ bit stream is passed
unchanged.
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases).
Idle Line State indicates the preamble of a frame or the lack
for frame transmission during normal operation. Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process.
SHIFT REGISTER
The Shift Register converts the serial bit stream into symbol-wide data for the 5B/4B Decoder.
The Shift Register also provides byte-wide data for the
Framing Logic.
TABLE 3-1. Symbol Decoding
Symbol
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
FRAMING LOGIC
The Framing Logic performs the Framing function by detecting the beginning of a frame or the Halt-Halt or Halt-Quiet
symbol pair.
The J-K symbol pair (11000 10001) indicates the beginning
of a frame during normal operation. The Halt-Halt (00100
00100) and Halt-Quiet (00100 00000) symbol pairs are detected during Connection Management (CMT).
Framing can be temporarily suspended (i.e. framing hold), in
order to maintain data integrity. The Framing Hold rules are
explained in Section 8.1.
SYMBOL DECODER
The Symbol Decoder is a two level system. The first level is
a 5-bit to 4-bit converter, and the second level is a 4-bit
symbol pair to the NSC byte-wide code converter.
The first level latches the received 5-bit symbols and decodes them into 4-bit symbols. Symbols are decoded into
two types: data and control. The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder. See Table 3-1 for the 5B/4B Symbol Decoding
list.
The second level translates two 4-bit symbols from the 5B/
4B converter and the line state information from the Line
State Detector into the National byte-wide code. More details on the National byte-wide code can be found in Section
8.6.
I (Idle)
H (Halt)
JK (Starting
Delimiter)
T (Ending
Delimiter)
R (Reset)
S (Set)
Q (Quiet)
V (Violation)
V
V
V
V
V
V
V
VÊ
IÊ
LINE STATE DETECTOR
The FDDI Physical Layer (PHY) standard specifies eight
Line States that the Physical Layer can transmit. These Line
States are used in the Connection Management process.
They are also used to indicate data within a frame during the
normal operation.
The Line State Detector detects nine Line States, one more
than the required Line States specified in the standard.
The Line States are reported through the Current Receive
State Register (CRSR), Receive Condition Register A
(RCRA), and Receive Condition Register B (RCRB).
Incoming 5B
Decoded 4B
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
11111
00100
11000 &
10001
01101
1010
0001
1101
00111
11001
00000
00001
00010
00011
00101
00110
01000
01100
10000
0110
0111
0010
0010
0010
0010
0010
0010
0010
0010
0010
0011
1011
0101
Notes:
VÊ denotes PHY Invalid or an Elasticity Buffer stuff byte.
IÊ denotes Idle symbol in ILS or an Elasticity Buffer stuff byte.
Line States Description
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair).
The Line State Detector continues to indicate Active Line
State while receiving data symbols, Ending Delimiter (T
symbols), and Frame Status symbols (R and S) after the JK
symbol pair.
Super Idle Line State
The Line State Detector recognizes the incoming data to be
in the Super Idle Line State upon the reception of eight consecutive Idle symbol pairs nominally (plus 1 symbol pair).
The Super Idle Line State is used to insure synchronization.
6
3.0 Functional Description (Continued)
ceive Clock, while data is read from the registers with the
Local Byte Clock.
No Signal Detect
The Line State Detector recognizes the incoming data to be
in the No Signal Detect state upon the deassertion of the
Signal Detect signal. No Signal Detect indicates that the
incoming link is inactive.
The Elasticity Buffer will recenter (i.e. set the read and write
pointers to a predetermined distance from each other) upon
the detection of a JK or every four byte times during PHY
Invalid (i.e. MLS, HLS, QLS, NLS, NSD) and Idle Line State.
To resolve metastability problems, the Elasticity Buffer is
designed such that a given register cannot be written and
read simultaneously under normal operating conditions. In a
symbol-wide station, a 5-bit off boundary JK following after a
maximum size frame situation may be produced which may
result in a small increase in the probability of an error
caused by a metastability condition.
Master Line State
The Line State Detector recognizes the incoming data to be
in the Master Line State upon the reception of eight consecutive Halt-Quiet symbol pairs nominally (plus up to 2 symbol
pairs in start up cases).
The Master Line State is used in the handshake sequence
of the PHY Connection Management process.
LINK ERROR DETECTOR
The Link Error Detector provides continuous monitoring of
an active link (i.e. during Active and Idle Line States) to
insure that it meets the minimum Bit Error Rate requirement
as set by the standard or user to remain on the ring.
Upon detecting a link error, the internal 8-bit Link Error Monitor Counter is decremented. The start value for the Link
Error Monitor Counter is programmed through the Link Error
Threshold Register (LETR). When the Link Error Monitor
Counter reaches zero, bit 4 (LEMT) of the Interrupt Condition Register (ICR) is set to 1. The current value of the Link
Error Monitor Counter can be read through the Current Link
Error Count Register (CLECR). For higher error rates the
current value is an approximate count because the counter
rolls over.
There are two ways to determine Link Error Rate: polling
and interrupt.
Halt Line State
The Line State Detector recognizes the incoming data to be
in the Halt Line State upon the reception of eight consecutive Halt symbol pairs nominally (plus up to 2 symbol pairs in
start up cases).
The Halt Line State is used in the handshake sequence of
the PHY Connection Management process.
Quiet Line State
The Line State Detector recognizes the incoming data to be
in the Quiet Line State upon the reception of eight consecutive Quiet symbol pairs nominally (plus up to 9 bits of 0 in
start up cases).
The Quiet Line State is used in the handshake sequence of
the PHY Connection Management process.
Noise Line State
The Line State Detector recognizes the incoming data to be
in the Noise Line State upon the reception of 16 noise symbol pairs.
The Noise Line State indicates that data is not received
correctly. A detailed description of a noise event can be
found in Section 8.2.
Polling
The Link Error Monitor Counter is set to the value of FF.
This start value is programmed through the Link Error
Threshold Register (LETR).
Upon detecting a link error, the Current Link Error Counter is
decremented.
The Host System reads the current value of the Link Error
Monitor Counter via the Current Link Error Count Register
(CLECR). The Counter is then reset to FF.
Line State Unknown
The Line State Detector recognizes the incoming data to be
in the Line State Unknown state upon the reception of one
inconsistent symbol pair (i.e. data that is not expected). This
may be the beginning of a new line state.
Line State Unknown indicates that data is not received correctly. If the condition persists the noise line state may be
entered.
Interrupt
The Link Error Monitor Counter is set to the value of FF.
This start value is programmed through the Link Error
Threshold Register (LETR).
Upon detecting a link error, the Line Error Monitor Counter
is decremented. When the counter reaches zero, bit 4
(LEMT) of the Interrupt Condition Register (ICR) is set to 1,
and the interrupt signal goes low.
The Host System is interrupted when the Link Error Monitor
Counter reaches 0.
A state table describing Link Errors in more detail can be
found in Section 8.3.
ELASTICITY BUFFER
The Elasticity Buffer performs the function of a ‘‘variable
depth’’ FIFO to compensate for clock skews between the
Receive Clock (RXC g ) and the Local Byte Clock (LBC).
Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is
set to 1 to indicate an error condition when the Elasticity
Buffer cannot compensate for the clock skews.
The Elasticity Buffer will support maximum clock skews of
g 50 ppm with a maximum packet length of 4500 bytes.
To make up for the accumulation of frequency disparity between the two clocks, the Elasticity Buffer will insert or delete Idle symbol pairs in the preamble. Data is written into
the byte-wide registers of the Elasticity Buffer with the Re-
Miscellaneous Items
When bit 0 (RUN) of the Mode Register (MR) is set to zero,
or when the PLAYER device is reset through the Reset pin
(RST), the Signal Detect line (TTLSD) is internally forced to
zero and the Line State Detector is set to Line State Unknown.
7
3.0 Functional Description (Continued)
While in the External Loopback mode, the Transmitter Block
presents serial data to the Clock Recovery Device.
3.2 TRANSMITTER BLOCK
The Transmitter Block accepts 10-bit bytes from the Configuration Switch.
The Transmitter Block performs the following operations:
The Transmitter Block consists of the following functional
blocks:
Data Registers
Parity Checker
4B/5B Encoder
Repeat Filter
Smoother
Line State Generator
Injection Control Logic
Shift Register
NRZ to NRZI Encoder
See Figure 3-2 .
# Encodes the data from 4B to 5B coding
# Filters out code violations from the data stream
# Is capable of generating Idle, Master, Halt, Quiet, or other user defined symbol pairs
# Converts the data stream from NRZ to NRZI ready for
transmission
# Serializes data
During normal operation, the Transmitter Block presents serial data to the fiber optic transmitter.
TL/F/10386 – 4
FIGURE 3-2. Transmitter Block Diagram
8
3.0 Functional Description (Continued)
LINE STATE GENERATOR
DATA REGISTERS
Data from the Configuration Switch is stored in the Data
Registers. The 10-bit byte-wide data consists of a parity bit,
a control bit, and two 4-bit symbols as shown in Figure 3-3.
b9
b8
Parity Bit
Control Bit
b7
The Line State Generator allows the transmission of the
PHY Request data and can also generate and transmit Idle,
Master, Halt, or Quiet symbol pairs which can be used to
implement the Connection Management procedures as
specified in the FDDI Station Management (SMT) document.
The Line State Generator is programmed through Transmit
bits 0 to 2 (TMk2:0l) of the Current Transmit State Register (CTSR).
Based on the setting of these bits, the Transmitter Block
operates in the Transmit Modes where the Line State Generator overwrites the Repeat Filter and Smoother outputs.
See Table 3-3 for the listing of the Transmit Modes.
b0
Data Bits
FIGURE 3-3. Byte-Wide Data
PARITY CHECKER
The Parity Checker verifies that the parity bit in the Data
Register represents odd parity (i.e. odd number of 1s).
The parity checking is enabled and disabled through bit 6
(PRDPE) of the Current Transmit State Register (CTSR).
If a parity error occurs, the Parity Checker will set bit 0 (DPE)
in the Interrupt Condition Register (ICR) and report the error
to the Repeat Filter.
TABLE 3-2. 4B/5B Symbol Encoding
4B/5B ENCODER
The 4B/5B Encoder converts the two 4-bit symbols from
the Configuration Switch into their respective 5-bit codes.
See Table 3-2 for the Symbol Encoding list.
REPEAT FILTER
The Repeat Filter is used to prevent the propagation of
code violations in data frames, to the downstream station.
Upon receiving violations in data frames, the Repeat Filter
replaces them with two Halt symbol pairs followed by Idle
symbols. Thus the code violations are isolated and recovered at each link and will not be propagated throughout the
entire ring.
Details on Repeat Filter operation are described in Section
8.4.
SMOOTHER
The Smoother is used to keep the preamble length of a
frame to a minimum of 6 Idle symbol pairs.
Idle symbols in the preamble of a frame may have been
added or deleted by each station to compensate for the
difference between the Receive Clock and its Local Clock.
The preamble needs to be maintained at a minimum length
to allow stations enough time to complete processing of one
frame and prepare to receive another. Without the Smoother function, the minimum preamble length (6 Idle symbol
pairs) may not be maintained as several stations may consecutively delete Idle symbols.
The Smoother attempts to keep the number of Idle symbol
pairs in the preamble at 7 by:
Symbol
4B Code
Outgoing 5B
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0000
11110 or
11111
11000 and
10001
01101
N
JK
T
R
S
(Starting
Delimiter)
(Ending
Delimiter)
(Reset)
(Set)
1101
0100 or
0101
0110
0111
00111
11001
TABLE 3-3. Transmit Modes
# Deleting an Idle symbol pair in preambles which have
more than 7 Idle symbol pairs
and/or
# Inserting an Idle symbol pair in preambles which have
less than 7 idle symbol pairs (i.e. Extend State).
The Smoother Counter starts counting upon detecting an
Idle symbol pair. It stops counting upon detecting a JK symbol pair.
More details on the operation of the Smoother can be found
in Section 8.5.
9
Active Transmit Mode
Normal Transmission Mode
Off Transmit Mode
Transmit Quiet symbol pairs
and disable the Fiber Optic
Transmitter
Idle Transmit Mode
Transmit Idle symbol pairs
Master Transmit Mode
Transmit Halt-Quiet symbol
pairs
Quiet Transmit Mode
Transmit Quiet symbol pairs
Reserved Transmit
Mode
Reserved for future use. If
selected, Quiet symbol pairs
will be transmitted.
Halt Transmit Mode
Transmit Halt symbol pairs
3.0 Functional Description (Continued)
In the No Injection mode, the data stream is transmitted
unchanged.
INJECTION CONTROL LOGIC
The Injection Control Logic replaces the data stream with a
programmable symbol pair. This function is used to transmit
data other than the normal data frame or Line States.
The Injection Symbols overwrite the Line State Generator
(Transmit Modes) and the Repeat Filter and Smoother outputs.
These programmable symbol pairs are stored in the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB). The Injection Threshold Register (IJTR) determines where the Injection Symbol pair will replace the data
symbols.
The Injection Control Logic is programmed through the bits
0 and 1 (ICk1:0l) of the Current Transmit State Register
(CTSR) to one of the following Injection Modes (see Figure
3-4 ):
1. No Injection (i.e. normal operation)
2. One Shot
3. Periodic
4. Continuous
In the One Shot mode, ISRA and ISRB are injected once on
the nth byte after a JK, where n is the programmed value
specified in the Injection Threshold Register.
In the Periodic mode, ISRA and ISRB are injected every nth
symbol.
In the Continuous mode, all data symbols are replaced with
the contents of ISRA and ISRB. This is the same as periodic
mode with IJTR e 0.
SHIFT REGISTER
The Shift Regiser converts encoded parallel data to serial
data. The parallel data is clocked into the Shift Register by
the Transmit Byte Clock (TBC g ), and clocked out by the
Transmit Bit Clock (TXC g ).
NRZ TO NRZI ENCODER
The NRZ to NRZI Encoder converts the serial Non-ReturnTo-Zero data to Non-Return-To-Zero-Invert-On-One data.
This function can be enabled and disabled through bit 6
(TNRZ) of the Mode Register (MR). When programmed to
‘‘0’’, it converts the bit stream from NRZ to NRZI. When
programmed to ‘‘1’’, the bit stream is transmitted NRZ.
One Shot (Notes 1, 3)
TL/F/10386 – 5
Periodic (Notes 2, 3)
TL/F/10386 – 6
Continuous (Note 3)
TL/F/10386 – 33
Where
ISRA: Injection Symbol Register A
ISRB: Injection Symbol Register B
IJTR: Injection Threshold Register
Note 1: In one shot when n a 0 the JK is replaced.
Note 2: In periodic when n e 0 all symbols are replaced.
Note 3: Max value on n e 255.
FIGURE 3-4. Injection Modes
10
3.0 Functional Description (Continued)
PHY Port Interface output data paths, AÐIndicate and
BÐIndicate, that can drive output data paths of the external
PHY Port Interface. The third output data path is connected
internally to the Transmit Block.
The Configuration Switch is the same on both the DP83251
device and the DP83255 device. However, the DP83255
has two PHY Port interfaces connected to the Configuration
Switch, whereas the DP83251 has one PHY Port Interface.
The DP83255 uses the AÐRequest and AÐIndicate paths
as one PHY Port Interface and the BÐRequest and BÐIndicate paths as the other PHY Port interface (see Figure 35a ). The DP83251, having only one port interface, uses the
BÐRequest and AÐIndicate paths as its external port. The
AÐRequest and BÐIndicate paths of the DP83251 are null
connections and are not used by this device (see Figure 35b ).
3.3 CONFIGURATION SWITCH
The Configuration Switch consists of a set of multiplexors
and latches which allow the PLAYER device to configure
the data paths without the need of external logic. The Configuration Switch is controlled through the Configuration
Register (CR).
The Configuration Switch has four internal buses, the
AÐRequest bus, the BÐRequest bus, the Receive bus, and
the PHYÐInvalid bus. The two Request buses can be driven by external input data connected to the external PHY
Port Interface. The Receive bus is internally connected to
the Receive Block of the PLAYER device, while the PHYÐ
Invalid bus has a fixed 10-bit LSU pattern, useful during the
connection process. The configuration switch also has three
internal multiplexors, each can select any of the four buses
to connect to its respective data path. The first two are
TL/F/10386 – 7
TL/F/10386 – 34
FIGURE 3-5a. Configuration Switch Block
Diagram for DP83255
FIGURE 3-5b. Configuration Switch Block
Diagram for DP83251
11
3.0 Functional Description (Continued)
Although two DP83251s can be connected together to build
a Dual Attach Station, it is recommended that the DP83255
is to be used for this type of station configuration.
A DAS with Single MAC can be configured as follows:
STATION CONFIGURATIONS
Single Attach Station (SAS)
The Single Attach Station can be connected to either the
Primary or Secondary ring via a Concentrator. Only 1 MAC
is needed in a SAS.
Both the DP83251 and DP83255 can be used in a Single
Attach Station. The DP83251 can be connected to the MAC
via its only PHY Port Interface. The DP83255 can be connected to the MAC via either of the 2 PHY Port Interfaces.
See Figures 3-6 and 3-7 .
# BÐIndicate data of PHYÐA is connected to AÐRequest
input of PHYÐB. BÐRequest input of PHYÐA is connected to AÐIndicate output of PHYÐB.
# The MAC can be connected to either the AÐRequest
input and the AÐIndicate output of PHYÐA or the
BÐRequest input and the BÐIndicate output
of PHYÐB.
The DAS with Dual MACs can be configured as follows:
Dual Attach Station (DAS)
A Dual Attach Station can be connected directly to the dual
ring. There are two types of Dual Attach Stations: DAS with
a Single MAC and DAS with Dual MACs. See Figures 3-8
and 3-9 .
# BÐIndicate data of PHYÐA is connected to AÐRequest
input of PHYÐB. BÐRequest input of PHYÐA is connected to AÐIndicate output of PHYÐB.
# The MACÐ1 is connected to the BÐIndicate output and
the BÐRequest Input of PHYÐB.
# The MACÐ2 is connected to the AÐIndicate output and
the AÐRequest Input of PHYÐA.
TL/F/10386–8
FIGURE 3-6. Single Attach Station Using the DP83251
TL/F/10386 – 9
FIGURE 3-7. Single Attachment Station (SAS)
Using the DP83255
TL/F/10386 – 10
FIGURE 3-8. Dual Attachment Station (DAS), Single MAC
TL/F/10386 – 11
FIGURE 3-9. Dual Attachment Station (DAS), Dual MACs
12
3.0 Functional Description (Continued)
Single Attach Concentrator
CONCENTRATOR CONFIGURATIONS
There are 2 types of Concentrators: Single Attach and Dual
Attach. These Concentrators can be designed with or without the MAC(s). Its configuration is determined based upon
its type and the number of active MACs in the Concentrator.
Using the PLAYER devices, a Concentrator can be built with
many different configurations without the need of any external logic.
Both the DP83251 and DP83255 can be used to build a
Single Attach Concentrator. Only the DP83255 is recommended for the Dual Attach Concentrator design.
See Application Note 675, Designing FDDI Concentrators
and Application Note 741, Differentiating FDDI Concentrators for futher information.
A Single Attach Concentrator is a Concentrator that has
only one PHY at the Dual Ring Connect side. It cannot,
therefore, be connected directly to the Dual Ring. A Single
Attach Concentrator is a Branch to the Dual Ring Tree. It is
connected to the ring as a Slave of another Concentrator.
Multiple Single Attach Concentrators can be connected together hierarchically to build multiple levels of branches in a
Dual Ring.
The Single Attach Concentrator can be connected to either
the Primary or Secondary ring depending on the connection
with its Concentrator (the Concentrator that it is connected
to a slave).
Figure 3-10 shows a Single Attach Concentrator with a Single MAC.
Concepts
A Concentrator is comprised of 2 parts: the Dual Ring Connect portion and the Master Ports.
The Dual Ring Connection portion connects the Concentrator to the dual ring directly or to another Concentrator. If the
Concentrator is connected directly to the dual ring, it is a
part of the ‘‘Dual Ring Tree’’. If the Concentrator is connected to another Concentrator, it is a ‘‘Branch’’ of the ‘‘Dual
Ring Tree’’.
The Master Ports connect the Concentrator to its ‘‘Slaves’’.
A Slave could be a Single Attach Station or another Concentrator (thus forming another Branch of the Dual Ring
Tree).
When a MAC in a concentrator is connected to the Primary
or Secondary Ring, it is required to be situated at the exit
port of that concentrator (i.e. its PHÐIND is connected to
the IND Interface of the last Master Port in the Concentrator
(PHYÐM n) that is connected to that ring).
A Concentrator can have two MACs connected to both the
Primary and Secondary rings. In addition, a Roving MAC can
be included in the Concentrator configuration. A Roving
MAC can be used to test the stations connected to the Concentrator before allowing them to join the Dual Ring. This
may require external multiplexers.
Dual Attach Concentrator
A Dual Attach Concentrator is a Concentrator that has two
PHYs at the Dual Ring Connect side. It is connected directly
to the dual ring and is a part of the Dual Ring Tree.
The Dual Attach Concentrator is connected to both the Primary and Secondary rings.
Dual Attach Concentrator with Single MAC
Figure 3-11 shows a Dual Attach Concentrator with a Single
MAC.
Because the Concentrator has one MAC, it can only transmit and receive frames on the ring where the MAC is connected. The Concentrator can only repeat frames on the
other ring.
Dual Attach Concentrator with Dual MACs
Figure 3-12 shows Dual Attach Concentrator wih Dual
MACs.
Because the Concentrator has two MACs, it can transmit
and receive frames on both the Primary and Secondary
rings.
13
3.0 Functional Description (Continued)
TL/F/10386 – 12
FIGURE 3-10. Single Attach Concentrator (SAC), Single MAC
TL/F/10386 – 13
FIGURE 3-11. Dual Attach Concentrator (DAC), Single MAC
TL/F/10386 – 14
FIGURE 3-12. Dual Attach Concentrator (DAC), Dual MACs
14
4.0 Modes of Operation
The PLAYER device can operate in 4 basic modes: RUN,
STOP, LOOPBACK, and CASCADE.
4.1 RUN MODE
RUN is the normal mode of operation.
In this mode, the PLAYER device is configured to be connected to the media via the Fiber Optic Transmitter and
Receiver at the Serial Interface. It is also connected to other
PLAYER device(s) and/or BMAC device(s) via the Port A
and Port B Interfaces.
While operating in the Run mode, the PLAYER device receives and transmits Line States (Quiet, Halt, Master, Idle)
and frames (Active Line State).
4.2 STOP MODE
The PLAYER device operates in the STOP mode while it is
being initialized or configured.
The PLAYER device is also reset to the STOP mode automatically when the RST pin (pin 71 on the DP83251 and pin
111 on the DP83255) is set to ground.
When in STOP mode, the PLAYER device performs the following functions:
#
#
#
#
#
#
Resets the Repeat Filter.
Resets the Smoother.
Resets the Receiver Block Line State Counters.
Flushes the Elasticity Buffer.
Forces Line State Unknown in the Receiver Block.
Outputs LSU symbol pairs (0 1 0011 1010) through
the PHY Data Indicate pins (AIP, AIC, AID k7:0l, BIP,
BIC, BIDk7:0l).
TL/F/10386 – 42
FIGURE 4-1a. Configuration Switch
Loopback for DP83255
# Outputs Quiet symbol pairs through the PMD Data Request pins (TXD g ).
# Resets all Control Bus register contents to zero or default values.
4.3 LOOPBACK MODE
The PLAYER device provides three types of loopback tests:
Configuration Switch Loopback, Internal Loopback, and External Loopback. These Loopback modes can be used to
test different portions of the device.
4.3.1 Configuration Switch Loopback
The Configuration Switch Loopback can be used to test the
data paths of the BMAC device(s) that are connected to the
PLAYER device before transmitting and receiving data
through the network.
In the Configuration Switch Loopback mode, the PLAYER
device performs the following functions:
# Selects Port A PHY Request Data, Port B PHY Request
Data, or PHY Invalid to connect to Port A PHY Indicate
Data via the AÐIND Mux.
# Selects Port A PHY Request Data, Port B PHY Request
Data, or PHY Invalid to connect to Port B PHY Indicate
Data via the BÐIND Mux.
# Connects data from the Receiver Block to the Transmitter Block via the TransmitterÐMux. (The PLAYER device
is repeating incoming data from the media in the Configuration Switch Loopback mode.)
See Figure 4-1a and 4-1b for block diagrams.
TL/F/10386 – 43
FIGURE 4-1b. Configuration Switch
Loopback for DP83251
FIGURE 4-1.
15
4.0 Modes of Operation (Continued)
# Outputs Quiet symbols through the External Loopback
4.3.2 Internal Loopback
The Internal Loopback mode can be used to test the functionality of the PLAYER device and to test the data paths
between the PLAYER and BMAC devices before ring insertion.
When in the Internal Loopback mode, the PLAYER device
performs the following functions:
Data pins (LBD g ).
The level of the Quiet symbols transmitted through the
TXC g pins is programmable through the Transmit Quiet
Level bit of the Mode Register.
The level of the Quiet symbols transmitted through the
LBD g pins is always high, regardless of the Transmit Quiet
Level bit of the Mode Register.
If both Internal Loopback and External Loopback modes are
selected, Internal Loopback mode will have priority over External Loopback mode.
See Figure 4-2 for a block diagram.
# Directs the output data of the Transmitter Block to the
input of the Receiver Block through internal paths (see
Figure 2-1 PLAYER Device Block Diagram).
# Ignores the PMD Data Indicate pins (RXD g and RXC g ),
# Outputs Quiet symbols through the PMD Data Request
pins (TXD g ), and
TL/F/10386 – 16
FIGURE 4-2. Internal Loopback
16
4.0 Modes of Operation (Continued)
# Outputs Quiet symbols through the PMD Data Request
4.3.3 External Loopback
The External Loopback mode can be used to test the functionality of the PLAYER device and to test the data paths
between the PLAYER, CRD, and BMAC devices before
transmitting and receiving data through the network.
When in the External Loopback mode, the PLAYER device
performs the following functions:
pins (TXD g ).
The level of the Quiet symbols transmitted through the
TXC g pins is programmable through the Transmit Quiet
Level bit of the Mode Register.
If both Internal Loopback and External Loopback modes are
selected, Internal Loopback mode will have priority over External Loopback mode.
See Figure 4-3 for a block diagram.
# Directs the output data of the Transmitter Block to the
external Loopback Data pins (LBD g ), which are normally connected to the Clock Recovery Device (see Figure
2 . PLAYER Device Block Diagram).
TL/F/10386 – 17
FIGURE 4-3. External Loopback
17
4.0 Modes of Operation (Continued)
# Data frames must be a minimum of three bytes long (in-
4.4 CASCADE MODE
The PLAYER device can operate in the Cascade (parallel)
modeÐFigure 4-4 Ðwhich is used in high bandwidth, pointto-point data transfer applications. This is a non-FDDI mode
of operation.
cluding the JK symbol pair). Smaller frames will cause
Elasticity Buffer errors.
# Data frames must have a maximum size of 4500 bytes,
with a JK starting delimiter and a (T or R or S)x or x(T or
R or S) ending delimiter byte.
3. Due to the different clock rates, the JK symbol pair may
arrive at different times at each PLAYER device. The total
skew between the fastest and slowest cascaded PLAYER devices receiving the JK starting delimiter must not
exceed 80 ns.
4. The first PLAYER device to receive a JK symbol pair will
present it to the host system and assert the Cascade
Ready signal. The PLAYER device will present one more
JK as it waits for the other PLAYER devices to recognize
their JK. The maximum number of consecutive JKs that
can be presented to the host is 2.
5. The Cascade Start signal is set to 1 when all the cascaded PLAYER devices release their Cascade Ready signals.
6. Bit 4 (CSE) of the Receive Condition Register B (RCRB)
is set to 1 if the Cascade Start signal (CS) is not set
before the second falling edge of clock signal LBC from
when Cascade Ready (CR) was released. CS has to be
set within approximately 80 ns of CR release. This condition signifies that not all cascaded PLAYERs have received their respective JK symbol pair within the allowed
skew range.
7. If the JK symbols are corrupted in the point-to-point links,
some PLAYER devices may not report a Cascaded Synchronization Error.
8. To guarantee integrity of the interframe information, the
user must put at least 8 Idle symbol pairs between
frames. The PLAYER device will function properly with
only 4 Idle symbol pairs, however the interframe symbols
may be corrupted with random non-JK symbols.
The BMAC device could be used to provide required framing and optical FCS support.
CONCEPTS
In the Cascade mode, multiple PLAYER devices are connected together to provide data transfer at multiples of the
FDDI data rate. Two cascaded PLAYER devices provide a
data rate twice the FDDI data rate; three cascaded PLAYER
devices provide a data rate three times the FDDI data rate,
etc.
Multiple data streams are transmitted in parallel over each
pair of cascaded PLAYER devices. All data streams start
simultaneously and begin with the JK symbol pair on each
PLAYER device.
Data is synchronized at the receiver of each PLAYER device by the JK symbol pair. Upon receiving a JK symbol pair,
a PLAYER device asserts the Cascade Ready signal to indicate the beginning of data reception.
The Cascade Ready signals of all PLAYER devices are
open drain ANDed together to create the Cascade Start
signal. The Cascade Start signal is used as the input to
indicate that all PLAYER devices have received the JK symbol pair. Data is now being received at every PLAYER device and can be transferred from the cascaded PLAYER
devices to the host system.
See Figure 4-5 for more information.
OPERATING RULES
When the PLAYER device is operating in Cascade mode,
the following rules apply:
1. Data integrity can be guaranteed if the worst case fiber
optic transmission skew between parallel fiber cables is
less than 40 ns. This amounts to about 785 meters of
fiber, assuming a 1% worst case variance.
2. Even though this is a non-FDDI application, the general
rules for FDDI frames must be obeyed.
18
4.0 Modes of Operation (Continued)
TL/F/10386 – 18
FIGURE 4-4. Parallel Transmission
TL/F/10386 – 19
FIGURE 4-5. Cascade Mode of Operation
Note: N is recommended to be less than 3 for this mode. See Application Note 679 for larger values of N.
19
5.0 Registers
The PLAYER device is initialized, configured, and monitored via 32 8-bit registers. These registers are accessible through the
Control Bus Interface.
Table 5-1 is a Register Summary List. Table 5-2 shows the contents of each register.
TABLE 5-1. Register Summary
Register
Address
Register
Symbol
Access Rules
00h
MR
Mode Register
Always
Always
01h
CR
Configuration Register
Always
Always
02h
ICR
Interrupt Condition Register
Always
Conditional
03h
ICMR
Interrupt Condition Mask Register
Always
Always
04h
CTSR
Current Transmit State Register
Always
Conditional
05h
IJTR
Injection Threshold Register
Always
Always
06h
ISRA
Injection Symbol Register A
Always
Always
07h
ISRB
Injection Symbol Register B
Always
Always
08h
CRSR
Current Receive State Register
Always
Write Reject
09h
RCRA
Receive Condition Register A
Always
Conditional
0Ah
RCRB
Receive Condition Register B
Always
Conditional
0Bh
RCMRA
Receive Condition Mask Register A
Always
Always
0Ch
RCMRB
Receive Condition Mask Register B
Always
Always
0Dh
NTR
Noise Threshold Register
Always
Always
0Eh
NPTR
Noise Prescale Threshold Register
Always
Always
Register Name
Read
Write
0Fh
CNCR
Current Noise Count Register
Always
Write Reject
10h
CNPCR
Current Noise Prescale Count Register
Always
Write Reject
11h
STR
State Threshold Register
Always
Always
12h
SPTR
State Prescale Threshold Registger
Always
Always
13h
CSCR
Current State Count Register
Always
Write Reject
14h
CSPCR
Current State Prescale Count Register
Always
Write Reject
15h
LETR
Link Error Threshold Register
Always
Always
16h
CLECR
Current Link Error Count Register
Always
Write Reject
17h
UDR
User Definable Register
Always
Always
18h
IDR
Device ID Register
Always
Write Reject
19h
CIJCR
Current Injection Count Register
Always
Write Reject
1Ah
ICCR
Interrupt Condition Comparison Register
Always
Always
1Bh
CTSCR
Current Transmit State Comparison Register
Always
Always
1Ch
RCCRA
Receive Condition Comparison Register A
Always
Always
1Dh
RCCRB
Receive Condition Comparison Register B
Always
Always
1Eh
RR0
Reserved Register 0
Always
Write Reject
1Fh
RR1
Reserved Register 1
Always
Write Reject
20
5.0 Registers (Continued)
TABLE 5-2. Register Content Summary
Register
Address
Register
Symbol
00h
Bit Symbols
D7
D6
D5
D4
MR
RNRZ
TNRZ
TE
TQL
CM
EXLB
ILB
RUN
01h
CR
BIE
AIE
TRS1
TRS0
BIS1
BIS0
AIS1
AIS0
02h
ICR
UDI
RCB
RCA
LEMT
CWI
CCR
CPE
DPE
03h
ICMR
UDIM
RCBM
RCAM
LEMTM
CWIM
CCRM
CPEM
DPEM
04h
CTSR
RES
PRDPE
SE
IC1
IC0
TM2
TM1
TM0
05h
IJTR
IJT7
IJT6
IIJ5
IJT4
IJT3
IJT2
IJT1
IJT0
06h
ISRA
RES
RES
RES
IJS4
IJS3
IJS2
IJS1
IJS0
07h
ISRB
RES
RES
RES
IJS9
IJS8
IJS7
IJS6
IJS5
08h
CRSR
RES
RES
RES
RES
LSU
LS2
LS1
LS0
09h
RCRA
LSUPI
LSC
NT
NLS
MLS
HLS
QLS
NSD
0Ah
RCRB
RES
SILS
EBOU
CSE
LSUPV
ALS
ST
ILS
0Bh
RCMRA
LSUPIM
LSCM
NTM
NLSM
NLSM
HLSM
QLSM
NSDM
0Ch
RCMRB
RES
SILSM
EBOUM
CSEM
LSUPVM
ALSM
STM
ILSM
0Dh
NTR
RES
NT6
NT5
NT4
NT3
NT2
NT1
NT0
0Eh
NPTR
NPT7
NPT6
NPT5
NPT4
NPT3
NPT2
NPT1
NPT0
0Fh
CNCR
NCLSCD
CNC6
CNC5
CNC4
CNC3
CNC2
CNC1
CNC0
10h
CNPCR
CNPC7
CNPC6
CNPC5
CNPC4
CNPC3
CNPC2
CNPC1
CNPC0
11h
STR
RES
ST6
ST5
ST4
ST3
ST2
ST1
ST0
12h
SPTR
SPT7
SPT6
SPT5
SPT4
SPT3
SPT2
SPT1
SPT0
13h
CSCR
SCLSCD
CSC6
CSC5
CSC4
CSC3
CSC2
CSC1
CSC0
14h
CSPCR
CSPC7
CSPC6
CSPC5
CSPC4
CSPC3
CSPC2
CSPC1
CSPC0
15h
LETR
LET7
LET6
LET5
LET4
LET3
LET2
LET1
LET0
16h
CLECR
LEC7
LEC6
LEC5
LEC4
LEC3
LEC2
LEC1
LEC0
17h
UDR
RES
RES
RES
RES
EB1
EB0
SB1
SB0
18h
IDR
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
19h
CIJCR
IJC7
IJC6
IJC5
IJC4
IJC3
IJC2
IJC1
IJC0
1Ah
ICCR
UDIC
RCBC
RCAC
LEMTC
CWIC
CCRC
CPEC
DPEC
1Bh
CTSCR
RESC
PRDPEC
SEC
IC1C
IC0C
TM2C
TM1C
TM0C
1Ch
RCCRA
LSUPIC
LSCC
NTC
NLSC
MLSC
HLSC
QLSC
NSDC
1Dh
RCCRB
RESC
SILSC
EBOUC
CSEC
LSUPVC
ALSC
STC
ILSC
1Eh
RR1
RES
RES
RES
RES
RES
RES
RES
RES
1Fh
RR2
RES
RES
RES
RES
RES
RES
RES
RES
21
D3
D2
D1
D0
5.0 Registers (Continued)
MODE REGISTER (MR)
The Mode Register is used to initialize and configure the PLAYER device.
In order to minimize interruptions on the network, it is recommended that the PLAYER device first be put in STOP mode (i.e. set
the RUN bit to zero) before programming the Mode Register, the Configuration Register, or the Current Transmit State Register.
ACCESS RULES
ADDRESS
READ
WRITE
00h
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RNRZ
TNRZ
TE
TQL
CM
EXLB
ILB
RUN
Bit
Symbol
Description
D0
RUN
D1
ILB
D2
EXLB
D3
CM
D4
TQL
TRANSMIT QUIET LEVEL: This bit is used to program the transmission level of the Quiet
symbols.
0: Low level Quiet symbols are transmitted through the PMD Data Request pins
(i.e. TXD a e low, TXDb e high).
1: High level Quiet symbols are transmitted through the PMD Data Request pins
(i.e. TXD a e high, TXDb e low).
D5
TE
TRANSMIT ENABLE: The TE bit controls the action of FOTX Enable (TXE) pin independent
of the current transmit mode. When TE is 0, the TXE output disables the optical transmitter;
when TE is 1, the optical transmitter is disabled during the Off Transmit Mode (OTM) and
enabled otherwise. The On and Off level of the TXE is dependent on the FOTX Enable Level
(TEL) pin to the PLAYER device. The following rules summarizes the output of TXE:
(1) If TE e 0, then TXE e Off
(2) If TE e 1 and OTM, then TXE e 0ff
(3) If TE e 1 and not OTM, then TXE e On.
D6
TNRZ
TRANSMIT NRZ DATA:
0: Transmits data in Non-Return-To-Zero-Invert-On-Ones format.
1: Transmits data in Non-Return-To-Zero format.
D7
RNRZ
RECEIVE NRZ DATA:
0: Receives data in Non-Return-To-Zero-Invert-On-Ones format.
1: Receives data in Non-Return-To-Zero format.
RUN /STOP
0: Enables the STOP mode. Refer to Section 4.2, STOP Mode of Operation, for more
information.
1: Normal Operation (i.e. RUN mode).
Note: The RUN bit is automatically set to 0 when the RST pin is asserted (i.e. set to ground).
INTERNAL LOOPBACK:
0: Disables Internal Loopback mode (i.e. normal operation).
1: Enables Internal Loopback mode.
Refer to Section 4.3, Loopback Mode of Operation, for more information.
EXTERNAL LOOPBACK
0: Disables External Loopback mode (i.e. normal operation).
1: Enables External Loopback mode.
Refer to Section 4.3, Loopback Mode of Operation, for more information.
CASCADE MODE:
0: Disables synchronization of cascaded PLAYER devices.
1: Enables the synchronization of cascaded PLAYER devices.
Refer to Section 4.4, Cascade Mode of Operation, for more information.
22
5.0 Registers (Continued)
CONFIGURATION REGISTER (CR)
The Configuration Register controls the Configuration Switch Block and enables/disables both the A and B Indicate output
ports.
Note that the BÐIndicate output port is offered only on the DP83255 (for Dual Attach Stations), and not in the DP83251 (for
Single Attach Stations).
For further information, refer to Section 3.3, Configuration Switch.
ACCESS RULES
ADDRESS
READ
WRITE
01h
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
BIE
AIE
TRS1
TRS0
BIS1
BIS0
AIS1
AIS0
Bit
D0, D1
Symbol
AIS0, AIS1
Description
AÐINDICATE SELECTOR k0, 1l: The AÐIndicate Selector k0, 1l bits select one of the four
Configuration Switch data buses for the A Indicate output port (AIP, AIC, AID k7:0l).
Ð
AIS1
0
0
1
1
D2, D3
BIS0, BIS1
AIS0
0
1
0
1
PHY Invalid Bus
Receiver Bus
AÐRequest Bus
BÐRequest Bus
BÐINDICATE SELECTOR k0, 1l: The BÐIndicate Selector k0, 1l bits select one of the four
Configuration Switch data buses for the BÐIndicate output port (BIP, BIC, BID k7:0l).
BIS1
0
0
1
1
BIS0
0
1
0
1
PHY Invalid Bus
Receiver Bus
AÐRequest Bus
BÐRequest Bus
Note: Even though this bit can be set and/or cleared in the DP83251 (for Single Attach Stations), it will not affect
any I/Os since the DP83251 does not offer a BÐIndicate port.
D4, D5
TRS0, TRS1
TRANSMIT REQUEST SELECTOR k0, 1l: The Transmit Request Selector k0, 1l bits select
one of the four Configuration Switch data buses for the input to the Transmitter Block.
TRS1
0
0
1
1
TRS0
0
1
0
1
PHY Invalid Bus
Receiver Bus
AÐRequest Bus
BÐRequest Bus
Note: If the PLAYER device is in Active Transmit Mode (i.e. the Transmit Mode bits (TM k 2:0 l ) of the Current
Transmit State Register (CTSR) are set to 000) and the PHY Invalid Bus is selected, then the PLAYER device will
transmit a maximum of four Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter.
D6
AIE
AÐINDICATE ENABLE:
0: Disables the AÐIndicate output port. The AÐIndicate port pins will be at TRI-STATE when
the port is disabled.
1: Enables the AÐIndicate output port (AIP, AIC, AIDk7:0l).
D7
BIE
BÐINDICATE ENABLE:
0: Disable the BÐIndicate output port. The BÐIndicate port pins will be at TRI-STATE
when the port is disabled.
1: Enables the BÐIndicate output port (BIP, BIC, BIDk7:0l).
Note: Even though this bit can be set and/or cleared in the DP83251 (for Single Attach Stations), it will not affect
any I/Os since the DP83251 does not offer a BÐIndicate port.
23
5.0 Registers (Continued)
INTERRUPT CONDITION REGISTER (ICR)
The Interrupt Condition Register records the occurrence of an internal error event, the detection of Line State, an unsuccessful
write by the Control Bus Interface, the expiration of an internal counter, or the assertion of one or more of the User Definable
Sense pins.
The Interrupt Condition Register will assert the Interrupt pin (INT) when one or more bits within the register are set to 1 and the
corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1.
ACCESS RULES
ADDRESS
READ
WRITE
02h
Always
Conditional
D7
D6
D5
D4
D3
D2
D1
D0
UDI
RCB
RCA
LEMT
CWI
CCR
CPE
DPE
Bit
D0
Symbol
DPE
Description
PHYÐREQUESTÐDATA PARITY ERROR: This bit will be set to 1 when:
(1) The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register
(CTSR) is set to 1 and
(2) The Transmitter Block detects a parity error in the incoming PHY Request Data.
The source of the data can be from the PHY Invalid Bus, the Receiver Bus, the AÐBus, or the
BÐBus of the Configuration Switch.
D1
CPE
CONTROL BUS DATA PARITY ERROR: This bit will be set to 1 when:
(1) The Control Bus Parity Enable pin is asserted (CBPE e VCC) and
(2) The Control Bus Interface detects a parity error in the incoming Control Bus Data
(CBDk7:0l) during a write cycle.
D2
CCR
CONTROL BUS WRITE COMMAND REJECT: This bit will be set to 1 when an attempt to
write into one of the following read-only registers is made:
Current Receive State Register (Register 08, CRSR)
Current Noise Count Register (Register 0F, CNCR)
Current Noise Prescale Count Register (Register 10, CNPCR)
Current State Count Register (Register 13, CSCR)
Current State Prescale Count Register (Register 14, CSPCR)
Current Link Error Count Register (Register 16, CLECR)
Device ID Register (Register 18, IDR)
Current Injection Count Register (Register 19, CIJCR)
Reserved Register 0 (Register 1E, RR0)
Reserved Register 1 (Register 1F, RR1)
D3
CWI
CONDITIONAL WRITE INHIBIT: Set to 1 when bits within mentioned registers do not match
bits in compare register. This bit ensures that new (i.e. unread) data is not inadvertently
cleared while old data is being cleared through the Control Bus Interface.
This bit is set to 1 to prevent the setting or clearing of any bit within the following registers:
Interrupt Condition Register (Register 02, ICR)
Current Transmit State Register (Register 04, CTSR)
Receive Condition Register A (Register 09, RCRA)
Receive Condition Register B (Register 0A, RCRB)
when they differ from the value of the corresponding bit in the following registers respectively:
Interrupt Condition Compare Register (Register 1A, ICCR)
Current Transmit State Compare Register (Register 1B, CTSCR)
Receive Condition Compare Register A (Register 1C, RCCRA)
Receive Condition Compare Register B (Register 1D, RCCRB)
This bit must be cleared by software. Note that this differs from the BMAC device bit of the
same name.
24
5.0 Registers (Continued)
INTERRUPT CONDITION REGISTER (ICR) (Continued)
Bit
Symbol
D4
LEMT
LINK ERROR MONITOR THRESHOLD: This bit is set to 1 when the internal 8-bit Link Error Monitor
Counter reaches zero. It will remain set until cleared by software.
During the reset process (i.e. RST e GND), the Link Error Monitor Threshold bit is set to 1 because the
Link Error Monitor Counter is initialized to zero.
Description
D5
RCA
RECEIVE CONDITION A: This bit is set to 1 when:
(1) One or more bits in the Receive Condition Register A (RCRA) is set to 1 and
(2) The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1.
In order to clear (i.e. set to 0) the Receive Condition A bit, the bits within the Receive Condition Register
A that are set to 1 must first be either cleared or masked.
D6
RCB
RECEIVE CONDITION B: This bit is set to 1 when:
(1) One or more bits in the Receive Condition Register B (RCRB) is set to 1 and
(2) The corresponding mask bits in the Receive Condition Mask Register B (RCMRB) are also set to 1.
In order to clear (i.e. set to 0) the Receive Condition B bit, the bits within the Receive Condition Register
B that are set to 1 must first be either cleared or masked.
D7
UDI
USER DEFINABLE INTERRUPT: This bit is set to 1 when one or both of the Sense Bits (SB0 or SB1) in
the User Definable Register (UDR) is set to 1.
In order to clear (i.e. set to 0) the User Definable Interrupt Bit, both Sense Bits must be set to 0.
25
5.0 Registers (Continued)
INTERRUPT CONDITION MASK REGISTER (ICMR)
The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt.
The Interrupt pin will be asserted (i.e. INT e GND) when one or more bits within the Interrupt Condition Register (ICR) are set to
1 and the corresponding mask bits in this register are also set to 1.
This register is cleared (i.e. set to 0) and all interrupts are initially masked during the reset process.
ACCESS RULES
ADDRESS
03h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
UDIM
RCBM
RCAM
LEMTM
CWIM
CCRM
CPEM
DPEM
Bit
Symbol
D0
DPEM
PHYÐREQUESTÐDATA PARITY ERROR MASK: The mask bit for the PHYÐRequest Data Parity
Error bit (DPE) of Interrupt Condition Register (ICR).
Description
D1
CPEM
CONTROL BUS DATA PARITY ERROR MASK: The mask bit for the Control Bus Data Parity Error bit
(CPE) of the Interrupt Condition Register (ICR).
D2
CCRM
CONTROL BUS WRITE COMMAND REJECT MASK: The mask bit for the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR).
D3
CWIM
CONDITIONAL WRITE INHIBIT MASK: The mask bit for the Conditional Write Inhibit bit (CWI) of the
Interrupt Condition Register (ICR).
D4
LEMTM
LINK ERROR MONITOR THRESHOLD MASK: The mask bit for the Link Error Monitor Threshold bit
(LEMT) of the Interrupt Condition Register (ICR).
D5
RCAM
RECEIVE CONDITION A MASK: The mask bit for the Receive Condition A bit (RCA) of the Interrupt
Condition Register (ICR).
D6
RCBM
RECEIVE CONDITION B MASK: The mask bit for the Receive Condition B bit (RCB) of the Interrupt
Condition Register (ICR).
D7
UDIM
USER DEFINABLE INTERRUPT MASK: The mask bit for the User Definable Interrupt bit (UDI) of the
Interrupt Condition Register (ICR).
26
5.0 Registers (Continued)
CURRENT TRANSMIT STATE REGISTER (CTSR)
The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle, Master, Halt,
Quiet, or user programmable symbol pairs, in addition to the normal transmission of incoming PHY Request data. The Smoother
and PHY Request Data Parity may also be enabled and disabled through this register.
The Transmit Modes overwrite the Repeat Filter and Smoother outputs, while the Injection Symbols overwrite the Transmit
Modes.
During the reset process (i.e. RST e GND) the Transmit Mode is set to Off (TM k2:0l e 010), the Smoother is enabled (i.e. SE
is set to 1), and the Reserved bit (b7) is set to 1. All other bits of this register are cleared (i.e. set to 0) during the reset process.
ACCESS RULES
ADDRESS
04h
READ
WRITE
Always
Conditional
D7
D6
D5
D4
D3
D2
D1
D0
RES
PRDPE
SE
IC1
IC0
TM2
TM1
TM0
Bit
Symbol
Description
D0, D1,
D2
TM0, TM1,
TM2
Transmit Mode k0, 1, 2l: These bits select one of the 6 transmission modes for the PMD Request
Data output port (TXD g ).
TM2
0
TM1
0
TM0
0
0
0
1
Idle Transmit Mode (ITM): Transmission of
Idle symbol pairs (11111 11111).
0
1
0
Off Transmit Mode (OTM): Transmission of
Quiet symbol pairs (00000 00000) and
deassertion of the FOTX Enable pin (TXE).
0
1
1
Reserved: Reserved for future use. Users
are discouraged from using this transmit
mode. If selected, however, the transmitter
will generate Quiet symbol pairs (00000
00000).
1
0
0
Master Transmit Mode (MTM):
Transmission of Halt and Quiet symbol pairs
(00100 00000).
1
0
1
Halt Transmit Mode (HTM): Transmission of
Halt symbol pairs (00100 00100).
1
1
0
Quiet Transmit Mode (QTM): Transmission
of Quiet symbol pairs (00000 00000).
1
1
1
Reserved: Reserved for future use. Users
are discouraged from using this transmit
mode. If selected, however, the transmitter
will generate Quiet symbol pairs (00000
00000).
27
Active Transmit Mode (ATM): Normal
transmission of incoming PHY Request data.
5.0 Registers (Continued)
CURRENT TRANSMIT STATE REGISTER (CTSR) (Continued)
Bit
Symbol
D3, D4
IC0, IC1
Description
Injection Control k0, 1l: These bits select one of the 4 injection modes. The injection modes
overwrite data from the Smoother, Repeat Filter, Encoder, and Transmit Modes.
IC0 is the only bit of the register that is automatically cleared by the PLAYER device after the One Shot
Injection is executed. The automatic clear of IC0 during the One Shot mode can be interpreted as an
acknowledgment that the One Shot has been completed.
D5
SE
IC1
0
IC0
0
0
1
One Shot: In one shot mode, Injection
Symbol Register A (ISRA) and Injection
Symbol Register B (ISRB) are injected n
symbol pairs after a JK, where n is the
programmed value of the Injection Count
Register (IJCR). If IJCR is set to 0, the JK
symbol pair is replaced by ISRA and ISRB.
Once the One Shot is executed, the PLAYER
device automatically sets IC0 to 0, thereby
returning to normal transmission of data.
1
0
Periodic: In Periodic mode, Injection Symbol
Register A (ISRA) and Injection Symbol
Register B (ISRB) are injected every (n a 1)th
symbol pair, where n is the programmed
value of the Injection Count Register (IJCR).
If IJCR is set to 0, all data symbols are
replaced with ISRA and ISRB.
1
1
Continuous: In Continuous mode, all data
symbols are replaced with Injection Symbol
Register A (ISRA) and Injection Symbol
Register B (ISRB).
No Injection: The normal transmission of
incoming PHY Request data (i.e. symbols are
not injected).
SMOOTHER ENABLE:
0: Disables the Smoother.
1: Enables the Smoother.
When enabled, the Smoother can redistribute Idle symbol pairs which were added or deleted by
the local or upstream receivers.
Note: Once the counter has started, it will continue to count irrespective of the incoming symbols with the exception of a
JK symbol pair. This bit should be enabled for interoperable operation.
D6
PRDPE
PHYÐREQUEST DATA PARITY ENABLE:
0: Disables PHYÐRequest Data parity.
1: Enables PHYÐRequest Data parity.
D7
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset process. It may be set or
cleared without any effects to the functionality of the PLAYER device.
28
5.0 Registers (Continued)
INJECTION THRESHOLD REGISTER (IJTR)
The Injection Threshold Register, in conjunction with the Injection Control bits (IC k1:0l) in the Current Transmit State Register
(CTSR), set the frequency at which the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are inserted
into the data stream. It contains the start value for the Injection Counter.
The Injection Threshold Register value is loaded into the Injection Counter when the counter reaches zero or during every
Control Bus Interface write-cycle of this register.
The Injection Counter is an 8-bit down-counter which decrements every 80 ns. Its current value is read for CIJCR.
The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Controlk1:0l bits (ICk1:0l) of the
Current Transmit State Register (CTSR) are set to either 01 or 10). The Transmitter Block will replace a data symbol pair with
ISRA and ISRB when the counter reaches 0 and the Injection Mode is either One Shot or Periodic.
If the Injection Threshold Register is set to 0 during the One Shot mode, the JK will be replaced with ISRA and ISRB. If the
Injection Threshold Register is set to 0 during the Periodic mode, all data symbols are replaced with ISRA and ISRB.
The counter is initialized to 0 during the reset process (i.e. RST e GND).
For further information, see the Injection Control Logic subsection within Section 3.2.
ACCESS RULES
ADDRESS
05h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
IJT7
IJT6
IJT5
IJT4
IJT3
IJT2
IJT1
IJT0
Bit
Symbol
Description
D0
IJT0
INJECTION THRESHOLD BIT k0l: Least significant bit (LSB) of the start
value for the Injection Counter.
D1 – 6
IJT1 – 6
INJECTION THRESHOLD BIT k1 –6l: Intermediate bits of start value for the
Injection Counter.
D7
IJT7
INJECTION THRESHOLD BIT k7l: Most significant bit (MSB) of the start
value for the Injection Counter.
29
5.0 Registers (Continued)
INJECTION SYMBOL REGISTER A (ISRA)
The Injection Symbol Register A, along with Injection Symbol Register B, contains the programmable value (already in 5B code)
that will replace the data symbol pairs.
The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection
Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data
symbols are replaced with ISRA and ISRB.
ACCESS RULES
ADDRESS
06h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
IJS4
IJS3
IJS2
IJS1
IJS0
Bit
Symbol
Description
D0
IJS0
INJECTION THRESHOLD BIT k0l: Least significant bit (LSB) of Injection
Symbol Register A.
D1 – 3
IJS1– 3
INJECTION THRESHOLD BIT k1 –3l: Intermediate bits of Injection Symbol
Register A.
D4
IJS4
INJECTION THRESHOLD BIT k4l: Most significant bit (MSB) of Injection
Symbol Register A.
D5
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
D6
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
D7
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
30
5.0 Registers (Continued)
INJECTION SYMBOL REGISTER B (ISRB)
The Injection Symbol Register B, along with Injection Symbol Register A, contains the programmable value (already in 5B code)
that will replace the data symbol pairs.
The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection
Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data
symbols are replaced with ISRA and ISRB.
ACCESS RULES
ADDRESS
07h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
IJS9
IJS8
IJS7
IJS6
IJS5
Bit
Symbol
Description
D0
IJS5
INJECTION THRESHOLD BITk5l: Least significant bit (LSB) of Injection
D1 – 3
IJS6– 8
INJECTION THRESHOLD BIT k6 –8l: Intermediate bits of Injection Symbol
Register B.
D4
IJS9
INJECTION THRESHOLD BITk9l: Most significant bit (MSB) of Injection
Symbol Register B.
D5
RES
RESERVED: Reserved for future use.
Symbol Register B.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
D6
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
D7
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.
31
5.0 Registers (Continued)
CURRENT RECEIVE STATE REGISTER (CRSR)
The Current Receive State Register represents the current line state being detected by the Receiver Block. Once the Receiver
Block recognizes a new Line State, the bits corresponding to the previous line state are cleared, and the bits corresponding to
the new line state are set.
During the reset process (RST e GND), the Receiver Block is forced to Line State Unknown (i.e. the Line State Unknown bit
(LSU) is set to 1).
ACCESS RULES
ADDRESS
08h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
RES
LSU
LS2
LS1
LS0
Bit
D0, D1
D2
Symbol
LS0, LS1,
LS2
Description
LINE STATEk0, 1, 2l: These bits represent the current Line State being detected by the Receiver
Block. Once the Receiver Block recognizes a new line state, the bits corresponding to the previous
line state are cleared, and the bits corresponding to the new line state are set.
LS2
0
LS1
0
LS0
0
0
0
1
Idle Line State (ILS): Received a minimum
of two consecutive Idle symbol pairs (11111
11111).
0
1
0
No Signal Detect (NSD): The Signal Detect
pin (TTLSD) has been deasserted, indicating
that the Clock Recovery Device is not
receiving data from the Fiber Optic Receiver.
0
1
1
Reserved: Reserved for future use.
1
0
0
Master Line State (MLS): Received a
minimum of 8 consecutive Halt-Quiet symbol
pairs (00100 00000).
1
0
1
Halt Line State (HLS): Received a minimum
of 8 consecutive Halt symbol pairs (00100
00100).
1
1
0
Quiet Line State (QLS): Received a
minimum of 8 consecutive Quiet symbol pairs
(00000 00000).
1
1
1
Noise Line State (NLS): Detected a
minimum of 16 noise events. Refer to the
Receiver Block for further information on
noise events.
Active Line State (ALS): Received a JK
symbol pair (11000 10001), and possibly
followed by data symbols.
D3
LSU
LINE STATE UNKNOWN: The Receiver Block has not detected the minimum conditions to enter a
known line state. When the Line State Unknown bit is set, LSk2:0l represent the most recently
known line state.
D4
RES
RESERVED: Reserved for future use. The reserved bit is set to 0.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore
the Control Bus write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition
Register (ICR) to 1.
32
5.0 Registers (Continued)
CURRENT RECEIVE STATE REGISTER (CRSR) (Continued)
Bit
Symbol
D5
RES
Description
RESERVED: Reserved for future use. The reserved bit is set to 0.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.
D6
RES
RESERVED: Reserved for future use. The reserved bit is set to 0.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.
D7
RES
RESERVED: Reserved for future use. The reserved bit is set to 0.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.
33
5.0 Registers (Continued)
RECEIVE CONDITION REGISTER A (RCRA)
The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block.
When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line
States are not cleared by the PLAYER device, thereby maintaining a record of the Line States detected.
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is
also set to 1.
ACCESS RULES
ADDRESS
09h
READ
WRITE
Always
Conditional
D7
D6
D5
D4
D3
D2
D1
D0
LSUPI
LSC
NT
NLS
MLS
HLS
QLS
NSD
Bit
Symbol
Description
D0
NSD
NO SIGNAL DETECT: Indicates that the Signal Detect pin (TTLSD) has been
deasserted and that the Clock Recovery Device is not receiving data from the
Fiber Optic Receiver.
D1
QLS
QUIET LINE STATE: Received a minimum of eight consecutive Quiet symbol
pairs (00000 00000).
D2
HLS
HALT LINE STATE: Received a minimum of eight consecutive Halt symbol
pairs (00100 00100).
D3
MLS
MASTER LINE STATE: Received a minimum of eight consecutive Halt-Quiet
symbol pairs (00100 00000).
D4
NLS
NOISE LINE STATE: Detected a minimum of sixteen noise events.
D5
NT
NOISE THRESHOLD: This bit is set to 1 when the internal Noise Counter
reaches 0. It will remain set until a value equal to or greater than one is
loaded into the Noise Threshold Register or Noise Prescale Threshold
Register.
During the reset process (i.e. RST e GND), since the Noise Counter is
initialized to 0, the Noise Threshold bit will be set to 1.
D6
LSC
LINE STATE CHANGE: A line state change has been detected.
D7
LSUPI
LINE STATE UNKNOWN & PHY INVALID: The Receiver Block has not
detected the minimum conditions to enter a known line state.
In addition, the most recently known line state was one of the following line
states: No Signal Detect, Quiet Line State, Halt Line State, Master Line State,
or Noise Line State.
34
5.0 Registers (Continued)
RECEIVE CONDITION REGISTER B (RCRB)
The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block.
When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line
States are not clear by the PLAYER device, thereby maintaining a record of the Line States detected.
The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register B is set to 1 and the corresponding mask bits in Receive Condition Mask Register B (RCMRB) is
also set to 1.
ACCESS RULES
ADDRESS
0Ah
READ
WRITE
Always
Conditional
D7
D6
D5
D4
D3
D2
D1
D0
RES
SILS
EBOU
CSE
LSUPV
ALS
ST
ILS
Bit
Symbol
Description
D0
ILS
IDLE LINE STATE: Received a minimum of two consecutive Idle symbol
pairs (11111 11111).
D1
ST
STATE THRESHOLD: This bit will be set to 1 by the PLAYER device when
the internal State Counter reaches zero. It will remain set until a value equal
to or greater than one is loaded into the State Threshold Register or State
Prescale Threshold Register, and this register is cleared.
During the reset process (i.e. RST e GND), since the State Counter is
initialized to 0, the State Threshold bit is set to 1.
D2
ALS
ACTIVE LINE STATE: Received a JK symbol pair (11000 10001), and
possibly data symbols following.
D3
LSUPV
LINE STATE UNKNOWN & PHY VALID: Receiver Block has not detected
the minimum conditions to enter a know line state when the most recently
known line state was one of the following line states: Active Line State or Idle
Line State
D4
CSE
CASCADE SYNCHRONIZATION ERROR: When a synchronization error
occurs, the Cascade Synchronization Error bit is set to 1.
A synchronization error occurs if the Cascade Start signal (CS) is not asserted
within approximately 80 ns of Cascade Ready (CR) release.
D5
EBOU
ELASTICITY BUFFER UNDERFLOW/OVERFLOW: The Elasticity Buffer
has either overflowed or underflowed. The Elasticity Buffer will automatically
recover if the condition which caused the error is only transient.
D6
SILS
SUPER IDLE LINE STATE: Received a minimum of eight Idle symbol pairs
(11111 11111).
D7
RES
RESERVED: Reserved for future use. The reserved bit is set to 0 during the
reset process.
Note: Users are discouraged from using this bit. It may be set or cleared without any
effects to the functionality of the PLAYER device.
35
5.0 Registers (Continued)
RECEIVE CONDITION MASK REGISTER A (RCMRA)
The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt.
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1.
Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.
ACCESS RULES
ADDRESS
READ
WRITE
0Bh
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
LSUPIM
LSCM
NTM
NLSM
MLSM
HLSM
QLSM
NSDM
Bit
Symbol
Description
D0
NSDM
NO SIGNAL DETECT MASK: The mask bit for the No Signal Detect bit (NSD)
of the Receive Condition Register A (RCRA).
D1
QLSM
QUIET LINE STATE MASK: The mask bit for the Quiet Line State bit (QLS) of
the Receive Condition Register A (RCRA).
D2
HLSM
HALT LINE STATE MASK: The mask bit for the Halt Line State bit (HLS) of
the Receive Condition Register A (RCRA).
D3
MLSM
MASTER LINE STATE MASK: The mask bit for the Master Line State bit
(MLS) of the Receive Condition Register A (RCRA).
D4
NLSM
NOISE LINE STATE MASK: The mask bit for the Noise Line State bit (NLS)
of the Receive Condition Register A (RCRA)
D5
NTM
NOISE THRESHOLD MASK: The mask bit for the Noise Threshold bit (NT) of
the Receive Condition Register A (RCRA).
D6
LSCM
LINE STATE CHANGE MASK: The mask bit for the Line State Change bit
(LSC) of the Receive Condition Register A (RCRA).
D7
LSUPIM
LINE STATE UNKNOWN & PHY INVALID MASK: The mask bit for the line
State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A
(RCRA).
36
5.0 Registers (Continued)
RECEIVE CONDITION MASK REGISTER B (RCMRB)
The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt.
The Receiver Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1.
Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.
ACCESS RULES
ADDRESS
READ
WRITE
0Ch
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RES
SILSM
EBOUM
CSEM
LSUPVM
ALSM
STM
ILSM
Bit
Symbol
Description
D0
ILSM
IDLE LINE STATE MASK: The mask bit for the Idle Line State bit (ILS) of the
Receive Condition Register B (RCRB).
D1
STM
STATE THRESHOLD MASK: The mask bit of the State Threshold bit (ST) of
the Receive Condition Register B (RCRB).
D2
ALSM
ACTIVE LINE STATE MASK: The mask bit for the Active Line State bit (ALS)
of the Receive Condition Register B (RCRB).
D3
LSUPVM
LINE STATE UNKNOWN & PHY VALID MASK: The mask bit for the Line
State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B
(RCRB).
D4
CSEM
CASCADE SYNCHRONIZATION ERROR MASK: The mask bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B
(RCRB).
D5
EBOUM
ELASTICITY BUFFER OVERFLOW/UNDERFLOW MASK: The mask bit for
the Elasticity Buffer Overflow/Underflow bit (EBOU) of the Receive Condition
Register B (RCRB).
D6
SILSM
SUPER IDLE LINE STATE MASK: The mask bit for the Super Idle Line State
bit (SILS) of the Receive Condition Register B (RCRB).
D7
RESM
RESERVED MASK: The mask bit for the Reserved bit (RES) of the Receive
Condition Register B (RCRB).
37
5.0 Registers (Continued)
NOISE THRESHOLD REGISTER (NTR)
The Noise Threshold Register contains the start value for the Noise Counter. This counter may be used in conjunction with the
Noise Prescale Counter for counting the Noise events. Definiton of Noise event is explained in detail in Section 8.2. The Noise
Counter decrements once every 80 ns if the noise Prescale counter is zero and there is a noise event. As a result, the internal
noise counter takes
((NPTR a 1) x (NTR a 1)) x 80 ns
to reach zero in the event of continuous Noise event.
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active
Line State, or Line State Unknown.
or
(2) The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero.
The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a
Line State change occurs and the new line state is either Noise Line State, Active Line State or Line State Unknown.
When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition
Register A will be set.
ACCESS RULES
ADDRESS
0Dh
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
NT7
NT6
NT5
NT4
NT3
NT2
NT1
NT0
Bit
Symbol
Description
D0
NT0
NOISE THRESHOLD BITk0l: Least significant bit (LSB) of the start value
for the Noise Counter.
D1 – 5
NT1– 5
NOISE THRESHOLD BIT k1 –5l: Intermediate bits of start value for the
Noise Counter.
D6
NT6
NOISE THRESHOLD BIT k6l: Most significant bit (MSB) of the start value
for the Noise Counter.
D7
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. Write data is ignored since the reserved
bit is permanently set to 0.
38
5.0 Registers (Continued)
NOISE PRESCALE THRESHOLD REGISTER (NPTR)
The Noise Prescale Threshold Register contains the start value for the Noise Prescale Counter. The Noise Prescale Counter is a
count-down counter and it is used in conjunction with the Noise Counter for counting the Noise events. The Noise Prescale
Counter decrements once every 80 ns while there is a noise event. When the Noise Prescale Counter reaches zero, it reloads
the count with the content of the Noise Prescale Threshold Register and also causes the Noise Counter to decrement.
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active
Line State, or Line State Unknown.
or
(2) The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero.
The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a
Line State change occurs and the new line state is either Noise Line State, Active Line State, or Line State Unknown.
When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition
Register A will be set.
ACCESS RULES
ADDRESS
0Eh
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
NPT7
NPT6
NPT5
NPT4
NPT3
NPT2
NPT1
NPT0
Bit
D0
D1 – 6
D7
Symbol
NPT0
NPT1– 6
NPT7
Description
NOISE PRESCALE THRESHOLD BIT k0l: Least significant bit (LSB) of the
start value of the Noise Prescale Counter.
NOISE PRESCALE THRESHOLD BITk1 –6l: Intermediate bits of start
value for the Noise Prescale Counter.
NOISE PRESCALE THRESHOLD BIT k7l: Most significant bit (MSB) of the
start value for the Noise Prescale Counter.
39
5.0 Registers (Continued)
CURRENT NOISE COUNT REGISTER (CNCR)
The Current Noise Count Register takes a snap-shot of the Noise Counter during every Control Bus Interface read-cycle of this
register.
During a Control Bus Interface write-cycle to the Current Noise Count Register, the PLAYER device will set the Control Bus
Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS
0Fh
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
NCLSCD
CNC6
CNC5
CNC4
CNC3
CNC2
CNC1
CNC0
Bit
Symbol
Description
D0 – 6
CNC0 – 6
CURRENT NOISE COUNT BIT k0 –6l
D7
NCLSCD
NOISE COUNTER LINE STATE CHANGE DETECTION
40
5.0 Registers (Continued)
CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR)
The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Counter during every Control Bus Interface
read-cycle of this register.
During a Control Bus Interface write-cycle to the Current Noise Prescale Count Register, the PLAYER device will set the Control
Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS
10h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
CNPC7
CNPC6
CNPC5
CNPC4
CNPC3
CNPC2
CNPC1
CNPC0
Bit
Symbol
D0 – 7
CNPC0–7
Description
CURRENT NOISE PRESCALE COUNT BY k0 –7l
41
5.0 Registers (Continued)
STATE THRESHOLD REGISTER (STR)
The State Threshold Register contains the start value of the State Counter. This counter is used in conjunction with the State
Prescale Counter to count the Line State duration. The State Counter will decrement every 80 ns if the State Prescale Counter is
zero and the current Line State is Halt Line, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect. State The
State Counter takes
((SPTR a 1) x (STR a 1)) x 80 ns
to reach zero during a continuous line state condition.
The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,
Master Line State, Quiet Line State, or No Signal Detect
or
(2) A line state change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or
No Signal Detect
or
(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the State Prescale Threshold register is loaded into the State Prescale Counter if the State Prescale
Counter reaches zero.
The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the
new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.
ACCESS RULES
ADDRESS
11h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
Bit
Symbol
Description
D0
ST0
STATE THRESHOLD BIT k0l: Least significant bit (LSB) of the start value
for the State Counter.
D1 – 5
ST1 – 5
STATE THRESHOLD BIT k1 –5l: Intermediate bits of start value for the
State Counter.
D6
ST6
STATE THRESHOLD BIT k6l: Most significant bit (MSB) of the start value
for the State Counter.
D7
RES
RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. Write data is ignored since the reserved
bit is permanently set to 0.
42
5.0 Registers (Continued)
STATE PRESCALE THRESHOLD REGISTER (SPTR)
The State Prescale Threshold Register contains the start value for the State Prescale Counter. The State Prescale Counter is a
down counter. The Register is used in conjunction with the State Counter to count the Line State duration.
The State Prescale Counter will decrement every 80 ns if the current Line State is Halt Line, Idle Line State, Master Line State,
Quiet Line State, or No Signal Detect. As a result, the State Prescale Counter takes SPTR x 80 ns to reach zero during a
continuous line state condition. When the State Prescale Counter reaches zero, the State Prescale Threshold Register will be
reloaded into the State Prescale Counter.
The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,
Master Line State, Quiet Line State, or No Signal Detect.
or
(2) A Line State change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or
No Signal Detect
or
(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.
The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the
new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.
ACCESS RULES
ADDRESS
12h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
SPT7
SPT6
SPT5
SPT4
SPT3
SPT2
SPT1
SPT0
Bit
Symbol
Description
D0
SPT0
STATE PRESCALE THRESHOLD BIT k0l: Least significant bit (LSB) of
the start value for the State Prescale Counter.
D1 – 6
SPT1– 6
STATE PRESCALE THRESHOLD BIT k1 –6l: Intermediate bits of start
value for the State Prescale Counter.
D7
SPT7
STATE PRESCALE THRESHOLD BIT k7l: Most significant bit (MSB) of
the start value for the State Prescale Counter.
43
5.0 Registers (Continued)
CURRENT STATE COUNT REGISTER (CSCR)
The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read-cycle of this
register.
During a Control Bus Interface write-cycle to the Current State Count Register, the PLAYER device will set the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS
13h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
SCLSCD
CSC6
CSC5
CSC4
CSC3
CSC2
CSC1
CSC0
Bit
Symbol
Description
D0 – 6
CSC0– 6
CURRENT STATE COUNT BIT k0 –6l
D7
SCLSCD
STATE COUNTER LINE STATE CHANGE DETECTION
44
5.0 Registers (Continued)
CURRENT STATE PRESCALE COUNT REGISTER (CSPCR)
The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus interface
read-cycle of this register.
During a Control Bus Interface write-cycle to the Current State Prescale Count Register, the PLAYER device will set the Control
Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS
14h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
CSPC7
CSPC6
CSPC5
CSPC4
CSPC3
CSPC2
CSPC1
CSPC0
Bit
Symbol
Description
D0–7
CSPC0–7
CURRENT STATE PRESCALE COUNT k0 –7l
45
5.0 Registers (Continued)
LINK ERROR THRESHOLD REGISTER (LETR)
The Link Error Threshold Register contains the start value for the Link Error Monitor Counter, which is an 8-bit down-counter that
decrements if link errors are detected.
When the Counter reaches 0, the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and
the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to 1.
The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus
Interface write-cycle of LETR.
The Counter is initialized to 0 during the reset process (i.e. RST e GND).
ACCESS RULES
ADDRESS
15h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
LET7
LET6
LET5
LET4
LET3
LET2
LET1
LET0
Bit
Symbol
Description
D0
LET0
LINK ERROR THRESHOLD BIT k0l: Least significant bit of the start value
for the Link Error Monitor Counter.
D1 – 6
LET1 – 6
LINK ERROR THRESHOLD BIT k1 –6l: Intermediate bits of start value for
the Link Error Monitor Counter.
D7
LET7
LINK ERROR THRESHOLD BIT k7l: Most significant bit of the start value
for the Link Error Monitor Counter.
46
5.0 Registers (Continued)
CURRENT LINK ERROR COUNT REGISTER (CLECR)
The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface
read-cycle of this register.
During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS
16h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
LEC7
LEC6
LEC5
LEC4
LEC3
LEC2
LEC1
LEC0
Bit
Symbol
Description
D0– 7
LEC0–7
LINK ERROR COUNT BIT k0 –7l
47
5.0 Registers (Continued)
USER DEFINABLE REGISTER (UDR)
The User Definable Register is used to monitor and control events which are external to the PLAYER device.
The value of the Sense Bits reflects the asserted/deasserted state of their corresponding Sense pins. On the other hand, the
Enable bits assert/deassert the Enable pins.
ACCESS RULES
ADDRESS
17h
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RES
RES
RES
RES
EB1
EB0
SB1
SB0
Bit
Symbol
Description
D0
SB0
SENSE BIT 0: This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (i.e. SP0 e VCC) for a minimum of
160 ns. Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus
Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner.
D1
SB1
SENSE BIT 1: This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i.e. SP1 e VCC) for a minimum of
160 ns. Once the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus
Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner.
D2
EB0
ENABLE BIT 0: The Enable Bit 0 allows control of external logic through the Control Bus Interface. The
User Definable Enable Pin 0 (EP0) is asserted/deasserted by this bit.
0: EP0 is deasserted (i.e. EP0 e GND).
1: EP0 is asserted (i.e. EP0 e VCC).
D3
EB1
ENABLE BIT 1: This bit allows control of external logic through the Control Bus Interface. The User
Definable Enable Pin 0 (EP0) is asserted/deasserted by this bit.
0: EP1 is deasserted (i.e. EP1 e GND).
1: EP1 is asserted (i.e. EP1 e VCC).
D4 – 7
RES
RESERVED: Reserved for future use. The reserved bit is set to 0 during the initialization process
(i.e. RST e GND).
Note: Users are discouraged from using this bit. It may be set or cleared without any effects to the functionality of the
PLAYER device.
48
5.0 Registers (Continued)
DEVICE ID REGISTER (IDR)
The Device ID Register contains the binary equivalent of the revision number for this device. It can be used to ensure proper
software and hardware versions are matched.
During the Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Register bit (CCR) of
the Interrupt Condition Register (ICR) to 1, and will ignore write-cycle.
ACCESS RULES
ADDRESS
18h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
Bit
Symbol
Description
D0
DID0
DEVICE ID BIT k0l: Least significant bit (LSB) of the revision number.
D1 – 6
DID1 – 6
DEVICE ID BIT k1-0-6l: Intermediate bits of the revision number.
D7
DID7
DEVICE ID BIT k7l: Most significant bit (MSB) of the revision number.
49
5.0 Registers (Continued)
CURRENT INJECTION COUNT REGISTER (CIJCR)
The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read-cycle of
this register.
During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
The Injection Counter is an 8-bit down-counter which decrements every 80 ns.
The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control k1:0l bits (ICk1:0l) of the
Current Transmit State Register (CTSR) are set to either 01 or 10).
The Injection Threshold Register (IJTR) value is loaded into the Injection Counter when the counter reaches zero and during
every Control Bus Interface write-cycle of IJTR.
The counter is initialized to 0 during the reset process (i.e. RST e GND).
ACCESS RULES
ADDRESS
19h
READ
WRITE
Always
Write Reject
D7
D6
D5
D4
D3
D2
D1
D0
IJC7
IJC6
IJC5
IJC4
IJC3
IJC2
IJC1
IJC0
Bit
Symbol
Description
D0
IJC0
INJECTION COUNT BIT k0l: Least significant bit (LSB) of the current value
of the Injection Counter.
D1 – 6
IJC1– 6
INJECTION COUNT BIT k1 –6l: Intermediate bits representing the current
value of the Injection Counter.
D7
IJC7
INJECTION COUNT BIT k7l: Most significant bit (MSB) of the current
value of the Injection Counter.
50
5.0 Registers (Continued)
INTERRUPT CONDITION COMPARISON REGISTER (ICCR)
The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface.
The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison
Register (i.e. ICCR e ICR) during a Control Bus Interface read-cycle of ICR.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the
value of the corresponding bit in the Interrupt Condition Comparison Register.
ACCESS RULES
ADDRESS
1Ah
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
UDIC
RCBC
RCAC
LEMTC
CWIC
CCRC
CPEC
DPEC
Bit
Symbol
Description
D0
DPEC
PHYÐREQUEST DATA PARITY ERROR COMPARISON: The comparison
bit for the PHYÐRequest Data Parity Error bit (DPE) of the Interrupt Condition
Register (ICR).
D1
CPEC
CONTROL BUS DATA PARITY ERROR COMPARISON: The comparison bit
for the Control Bus Data Parity Error bit (CPE) of the Interrupt Condition
Register (ICR).
D2
CCRC
CONTROL BUS WRITE COMMAND REJECT COMPARISON: The
comparison bit for the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR).
D3
CWIC
CONDITIONAL WRITE INHIBIT COMPARISON: The comparison bit for the
Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR).
D4
LEMTC
LINK ERROR MONITOR THRESHOLD COMPARISON: The comparison bit
for the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition
Register (ICR).
D5
RCAC
RECEIVE CONDITION A COMPARISON: The comparison bit for the
Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR).
D6
RCBC
RECEIVE CONDITION B COMPARISON.: The comparison bit for the
Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR).
D7
UDIC
USER DEFINABLE INTERRUPT COMPARISON: The comparison bit for the
User Definable Interrupt bit (UDIC) of the Interrupt Condition Register (ICR).
51
5.0 Registers (Continued)
CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR)
The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface.
The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State
Comparison Register A (i.e. CTSCR e CTSR) during a Control Bus Interface read-cycle of CTSR.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR
differs from the value of the corresponding bit in the Current Transmit State Comparison Register.
ACCESS RULES
ADDRESS
1Bh
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RESC
PRDPEC
SEC
IC1C
IC0C
TM2C
TM1C
TM0C
Bit
Symbol
Description
D0
TM0C
TRANSMIT MODE k0l COMPARISON: The comparison bit for the
Transmit Mode k0l (TM0) of the Current Transmit State Register (CTSR).
D1
TM1C
TRANSMIT MODE k1l COMPARISON: The comparison bit for the
Transmit Mode k1l bit (TM1) of the Current Transmit State Register
(CTSR).
D2
TM2C
TRANSMIT MODE k2l COMPARISON: The comparison bit for the
Transmit Mode k2l bit (TM2) of the Current Transmit State Register
(CTSR).
D3
IC0C
INJECTION CONTROL k0l COMPARISON: The comparison bit for the
Injection Control k0l bit (IC0) of the Current Transmit State Register
(CTSR).
D4
IC1C
INJECTION CONTROL k1l COMPARISON: The comparison bit for the
Injection Control k1l bit (IC1) of the Current Transmit Register (CTSR).
D5
SEC
SMOOTHER ENABLE COMPARISON: The comparison bit for the Smoother
Enable bit (SE) to the Current Transmit State Register (CTSR).
D6
PRDPEC
PHYÐREQUEST DATA PARITY ENABLE COMPARISON: The comparison
bit for the PHYÐRequest Data Parity Enable bit (PRDPE) of the Current
Transmit State Register (CTSR).
D7
RESC
RESERVED COMPARISON: The comparison bit for the Reserved bit (RES)
of the Current Transmit State Register (CTSR).
52
5.0 Registers (Continued)
RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)
The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface.
The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i.e. RCCRA e RCRA)
during a Control Bus Interface read-cycle of RCRA.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of a bit in RCRA differs
from the value of the corresponding bit in the Receive Condition Comparison Register A.
ACCESS RULES
ADDRESS
1Ch
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
LSUPIC
LSCC
NTC
NLSC
MLSC
HLSC
QLSC
NSDC
Bit
Symbol
D0
NSDC
NO SIGNAL DETECT COMPARISON: The comparison bit for the No Signal Detect bit
(NSD) of the Receive Condition Register A (RCRA).
Description
D1
QLSC
QUIET LINE STATE COMPARISON: The comparison bit for the Quiet Line State bit
(QLS) of the Receive Condition Register A (RCRA).
D2
HLSC
HALT LINE STATE COMPARISON: The comparison bit for the Halt Line State bit (HLS)
of the Receive Condition Register A (RCRA).
D3
MLSC
MASTER LINE STATE COMPARISON: The comparison bit for the Master Line State bit
(MLS) of the Receive Condition Register A (RCRA).
D4
NLSC
NOISE LINE STATE COMPARISON: The comparison bit for the Noise Line State bit
(NLS) of the Receive Condition Register A (RCRA).
D5
NTC
NOISE THRESHOLD COMPARISON: The comparison bit for the Noise Threshold bit
(NT) of the Receive Condition Register A (RCRA).
D6
LSCC
LINE STATE CHANGE COMPARISON: The comparison bit for the Line State Change
bit (LSC) of the Receive Condition Register A (RCRA).
D7
LSUPIC
LINE STATE UNKNOWN & PHY INVALID COMPARISON: The comparison bit for the
Line State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A
(RCRA).
53
5.0 Registers (Continued)
RECEIVE CONDITION COMPARISON REGISTER B (RCCRB)
The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface.
The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i.e. RCCRB e RCRB)
during a Control Bus Interface read-cycle RCRB.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs
from the value of the corresponding bit in the Receive Condition Comparison Register B.
ACCESS RULES
ADDRESS
1Dh
READ
WRITE
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
RESC
SILSC
EBOUC
CSEC
LSUPVC
ALSC
STC
ILSC
Bit
Symbol
D0
ILSC
IDLE LINE STATE COMPARISON: The comparison bit for the Idle State bit (ILS) of the
Receive Condition Register B (RCRB).
Description
D1
STC
STATE THRESHOLD COMPARISON: The comparison bit for the State Threshold bit
(ST) of the Receive Condition Register B (RCRB).
D2
ALSC
ACTIVE LINE STATE COMPARISON: The comparison bit for the Active Line State bit
(ALS) of the Receive Condition Register B (RCRB).
D3
LSUPVC
LINE STATE UNKNOWN & PHY VALID COMPARISON: The comparison bit for the Line
State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB).
D4
CSEC
CASCADE SYNCHRONIZATION ERROR COMPARISON: The comparison bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B (RCRB).
D5
EBOUC
ELASTICITY BUFFER OVERFLOW/UNDERFLOW COMPARISON: The comparison bit
for the Elasticity Buffer Overflow/Underflow bit (EBOU) of the Receive Condition
Register B (RCRB).
D6
SILSC
SUPER IDLE LINE STATE COMPARISON: The comparison bit for the Super Idle Line
State bit (SILS) of the Receive Condition Register B (RCRB).
D7
RESC
RESERVED COMPARISON: The comparison bit for the Reserved bit (RES) of the
Receive Condition Register B (RCRB).
RESERVED REGISTER 0 (RR0) ADDRESS 1EhÐDO NOT USE
RESERVED REGISTER 1 (RR1) ADDRESS 1FhÐDO NOT USE
54
6.0 Pin Descriptions
6.1 DP83251
The pin descriptions for the DP83251 are divided into 5 functional interfaces: Serial Interface, PHY Port Interface, Control Bus
Interface, Clock Interface, and Miscellaneous Interface.
For a Pinout Summary List, refer to Table 6-1.
TL/F/10386 – 20
Order Number DP83251V
See NS Package Number V84A
FIGURE 6-1. DP83251 84-Pin PLCC Pinout
55
6.0 Pin Descriptions (Continued)
TABLE 6-1. DP83251 Pinout Summary
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
TTL
1
Control Bus Datak2l
CBD2
I/O
2
Control Bus Datak3l
CBD3
I/O
3
CMOS I/O Ground
GND
4
Control Bus Datak4l
CBD4
I/O
5
Control Bus Datak5l
CBD5
I/O
6
CMOS I/O Power
VCC
7
Control Bus Datak6l
CBD6
I/O
TTL
8
Control Bus Datak7l
CBD7
I/O
TTL
TTL
a 0V
TTL
TTL
a 5V
9
Control Bus Data Parity
CBP
I/O
TTL
10
Enable Pin 0
EP0
O
TTL
11
Enable Pin 1
EP1
O
12
CMOS Logic Ground
GND
13
Control Bus Data Parity Enable
CBPE
I
TTL
14
Sense Pin 0
SP0
I
TTL
15
Sense Pin 1
SP1
I
TTL
16
PHY Port A Indicate Parity
AIP
O
TTL
17
PHY Port A Indicate Control
AIC
O
TTL
18
PHY Port A Indicate Datak7l
AID7
O
TTL
19
PHY Port A Indicate Datak6l
AID6
O
20
CMOS I/O Ground
GND
21
PHY Port A Indicate Datak5l
AID5
22
CMOS I/O Power
VCC
23
PHY Port A Indicate Datak4l
AID4
24
CMOS Logic Ground
GND
25
PHY Port A Indicate Datak3l
AID3
O
TTL
26
PHY Port A Indicate Datak2l
AID2
O
TTL
27
PHY Port A Indicate Datak1l
AID1
O
TTL
28
PHY Port A Indicate Datak0l
AID0
O
TTL
29
Cascade Start
CS
O
TTL
30
Cascade Ready
CR
I
Open Drain
31
No Connect
N/C
32
No Connect
N/C
33
Clock Detect
CD
I
TTL
34
Signal Detect
TTLSD
I
TTL
35
External Loopback Enable
ELB
O
TTL
56
TTL
a 0V
TTL
a 0V
O
TTL
a 5V
O
TTL
a 0V
6.0 Pin Descriptions (Continued)
TABLE 6-1. DP83251 Pinout Summary (Continued)
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
ECL
36
Receive Bit Clock a
RXC a
I
37
Receive Bit Clock b
RXCb
I
38
ECL Logic Power
VCC
39
Receive Data a
RXD a
I
40
Receive Data b
RXDb
I
41
ECL Logic Ground
GND
42
External Loopback Data a
LBD a
O
43
External Loopback Data b
LBDb
O
ECL
a 5V
ECL
ECL
a 0V
ECL
ECL
44
ECL I/O Power
VCC
45
Transmit Data a
TXD a
O
46
Transmit Data a
TXDb
O
47
ECL Logic Ground
GND
48
Transmit Bit Clock a
TXC a
I
49
Transmit Bit Clock b
TXCb
I
50
ECL Logic Power
VCC
51
Transmit Byte Clock a
TBC a
I
ECL
52
Transmit Byte Clock b
TBCb
I
ECL
53
FOTX Enable Level
TEL
I
TTL
54
No Connect
N/C
55
No Connect
N/C
56
FOTX Enable
TXE
O
TTL
57
Local Byte Clock
LBC
I
TTL
58
PHY Port B Request Datak0l
BRD0
I
TTL
59
PHY Port B Request Datak1l
BRD1
I
TTL
60
PHY Port B Request Datak2l
BRD2
I
TTL
61
PHY Port B Request Datak3l
BRD3
I
62
CMOS Logic Ground
GND
63
PHY Port B Request Datak4l
BRD4
64
CMOS I/O Power
VCC
65
PHY Port B Request Datak5l
BRD5
66
CMOS I/O Ground
GND
67
PHY Port B Request Datak6l
BRD6
I
TTL
68
PHY Port B Request Datak7l
BRD7
I
TTL
69
PHY Port B Request Control
BRC
I
TTL
70
PHY Port B Request Parity
BRP
O
TTL
57
a 5V
ECL
ECL
a 0V
ECL
ECL
a 5V
TTL
a 0V
I
TTL
a 5V
I
TTL
a 0V
6.0 Pin Descriptions (Continued)
TABLE 6-1. DP83251 Pinout Summary (Continued)
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
71
E PLAYER Device Reset
RST
I
TTL
72
Read/ E Write
R/W
I
TTL
73
Chip Enable
CE
I
TTL
74
E Interrupt
INT
O
Open Drain
75
E Acknowledge
ACK
O
Open Drain
76
Control Bus Addressk0l
CBA0
I
TTL
77
Control Bus Addressk1l
CBA1
I
TTL
78
Control Bus Addressk2l
CBA2
I
TTL
79
Control Bus Addressk3l
CBA3
I
TTL
80
Control Bus Addressk4l
CBA4
I
81
CMOS Logic Power
VCC
82
Control Bus Datak0l
CBD0
I/O
83
Control Bus Datak1l
CBD1
I/O
84
CMOS Logic Ground
GND
58
TTL
a 5V
TTL
TTL
a 0V
6.0 Pin Descriptions (Continued)
SERIAL INTERFACE
The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)
sublayer.
The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FOXR), Clock
Recovery Device (CRD device), and Clock Distribution Device (CDD device).
Pin No.
I/O
CD
Symbol
33
I
Clock Detect: A TTL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXC g ) is properly synchronized with the Receive Data RXD g ).
Description
TTLSD
34
I
Signal Detect: A TTL signal from the clock Recovery Device indicating that a signal is
being received by the Fiber Optic Receiver.
RXD a
RXDb
39
40
I
Receive Data: Differential 100K ECL, 125 Mbps serial data input signals from the Clock
Recovery Device.
TXD a
TXDb
45
46
O
Transmit Data: Differential, 100K ECL, 125 Mbps serial data output signals to the Fiber
Optic Transmitter.
ELB
35
O
External Loopback Enable: A TTL output signal to the Clock Recovery Device which
enables/disables loopback data through the Clock Recovery Device. This signal is
controlled by the Mode Register.
LBD a
LBDb
42
43
O
Loopback Data: Differential, 100K ECL, 125 Mbps, external serial loopback data output
signals to the Clock Recovery Device.
When the PLAYER device is not in external loopback mode, the LBD a signal is kept
high and the LBDb signal is kept low.
TEL
53
I
FOTX Enable Level: A TTL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level.
TXE
56
O
FOTX Enable: A TTL output signal to enable/disable the Fiber Optic Transmitter. The
output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)
bit in the Mode Register, the TM2 – TM0 bits in the Current Transmit State Register, and
also the input to the TEL pin.
The following rules summarizes the output of the TXE pin:
(1) If TE e 0 and TEL e GND, then TXE e VCC
(2) If TE e 0 and TEL e VCC, then TXE e GND
(3) If TE e 1 and OTM and TEL e GND, then TXE e VCC
(4) If TE e 1 and OTM and TEL e VCC, then TXE e GND
(5) If TE e 1 and not OTM and TEL e GND, then TXE e GND
(6) If TE e 1 and not OTM and TEL e VCC, then TXE e VCC
59
6.0 Pin Descriptions (Continued)
PHY PORT INTERFACE
The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access Control (MAC)
sublayer or other PLAYER Devices. The DP83251 Device has one PHY Port Interface which consists of the BÐRequest and the
AÐIndicate paths.
Each path consists of an odd parity bit, a control bit, and two 4-bit symbols.
Refer to Section 3.3, the Configuration Switch, for further information.
Symbol
Pin No.
I/O
Description
AIP
16
O
PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port A Indicate signals (AIP, AIC, and AIDk7:0l).
AIC
17
O
PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(AIDk7:4l and AIDk3:0l) are either control symbols (AIC e 1) or data symbols (AIC
e 0).
AID7
AID6
AID5
AID4
18
19
21
23
O
PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control
symbol.
AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.
AID3
AID2
AID1
AID0
25
26
27
28
O
PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/
control symbol.
AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.
BRP
70
I
PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit
wide Port A Request signals (BRP, BRC, and BRDk7:0l).
BRC
69
I
PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols
(BRDk7:4l) and BRDk3:0l) are either control symbols (BRC e 1) or data symbols
(BRC e 0).
BRD7
BRD6
BRD5
BRD4
68
67
65
63
I
PHY Port B Request Data: TTL input signals representing the first 4 bit data/control
symbol.
BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.
BRD3
BRD2
BRD1
BRD0
61
60
59
58
I
PHY Port B Request Data: TTL input signals representing the second 4-bit data/control
symbol.
BRD3 is the most significant bit and BRD0 is the least significant bit of the second
symbol.
60
6.0 Pin Descriptions (Continued)
CONTROL BUS INTERFACE
The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides
access to 32 8-bit internal registers.
Refer to Figure 22 , Control Bus Timing Diagram, for more information.
Pin No.
I/O
Description
CE
Symbol
73
I
Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a read
or write cycle. R/W, CBAk4:0l, CBP, and CBDk7:0l must be valid at the time CE is low.
R/W
72
I
Read/ E Write: A TTL input signal which indicates a read Control Bus cycle (R/W e 1), or
a write Control Bus cycle (R/W e 0). This signal must be valid when CE is low and held
valid until ACK becomes low.
ACK
75
O
E Acknowledge: An active low, TTL, open drain output signal which indicates the
completion of a read or write cycle.
During a read cycle, CBDk7:0l are valid as long as ACK is low (ACK e 0).
During a write cycle, a microprocessor must hold CBDk7:0l valid until ACK becomes low.
Once ACK is low, it will remain low as long as CE remains low (CE e 0).
INT
74
O
E Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt
condition has occurred. The Interrupt Condition Register (ICR) should be read in order to
find out the source of the interrupt. Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR).
CBA4
CBA3
CBA2
CBA1
CBA0
80
79
78
77
76
I
Control Bus Address: TTL input signals used to select the address of the register to be
read or written.
CBA4 is the most significant bit (MSB), CBA0 is the least significant bit (LSB) of the address
signals.
These signals must be valid when CE is low and held valid until ACK becomes low.
CBPE
13
I
Control Bus Parity Enable: A TTL input signal which, during write cycles, will enable or
disable the Control Bus parity checker. Note that the Control Bus will always generate
parity during read cycles, regardless of the state of this signal.
CBP
9
I/O
Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus
data (CBDk7:0l).
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (ICR).
CBD7
CBD6
CBD5
8
7
5
I/O
CBD4
CBD3
CBD2
CBD1
CBD0
4
2
1
83
82
Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written
to a register.
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low.
61
6.0 Pin Descriptions (Continued)
CLOCK INTERFACE
The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either
the Clock Distribution Device or Clock Recovery Device.
Symbol
Pin No.
I/O
Description
LBC
57
I
Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock
Distribution Device. The Local Byte Clock is used by the PLAYER device’s internal
CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A
Interface, Port B Interface, and other miscellaneous I/Os.
RXC a
RXC b
36
37
I
Receive Bit Clock: Differential 100k ECL, 125 MHz clock input signals from the Clock
Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the
Receive Data (RXD g ).
TXC a
TXCb
48
49
I
Transmit Bit Clock: Differential 100k ECL, 125 MHz clock input signals from the Clock
Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the
Transmit Data (TXD g ).
TBC a
TBCb
51
52
I
Transmit Byte Clock: Differental 100k ECL, 12.5 MHz clock input signals from the Clock
Distribution Device. The Transmit Byte Clock is used by the PLAYER device’s internal
Shift Register Block.
62
6.0 Pin Descriptions (Continued)
MISCELLANOUS INTERFACE
The Miscellaneous Interface consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded
PLAYER devices synchronization signals, ground signals, and power signals.
Symbol
Pin No.
I/O
Description
RST
71
I
Reset: An active low, TTL, input signal which clears all registers. The signal
must be kept asserted for a minimum of 160 ns.
Once the RST signal is asserted, the PLAYER device should be allowed 960
ns to reset internal logic. Note that bit zero of the Mode Register will be set to
zero (i.e. Stop Mode). See Section 4.2, Stop Mode of Operation for more
information.
SP0
14
I
User Definable Sense Pin 0: A TTL input signal from a user defined source.
Bit zero (Sense Bit 0) of the User Definable Register (UDR) will be set to one
if the signal is asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through
the Control Bus Interface, even if the signal is deasserted. This ensures that
the Control Bus Interface will record the source of events which can cause
interrupts.
SP1
15
I
User Definable Sense Pin 1: A TTL input signal from a user defined source.
Bit one (Sense Bit 1) of the User Definable Register (UDR) will be set to one if
the signal is asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 1 can only be cleared through
the Control Bus Interface, even if the signal is deasserted. This ensures that
the Control Bus Interface will record the source of events which can cause
interrupts.
EP0
10
O
User Definable Enable Pin 0: A TTL output signal allowing control of
external logic through the CBUS Interface. EP0 is asserted/deasserted
through bit two (Enable Bit 0) of the User Definable Register (UDR). When
Enable Bit 0 is set to zero, EP0 is deasserted. When Enable Bit 0 is set to
one, EP0 is asserted.
EP1
11
O
User Definable Enable Pin 1: A TTL output signal allowing control of
external logic through the CBUS Interface. EP1 is asserted/deasserted
through bit two (Enable Bit 1) of the User Definable Register (UDR). When
Enable Bit 1 is set to zero, EP1 is deasserted. When Enable Bit 1 is set to
one, EP1 is asserted.
CS
29
I
Cascade Start: A TTL input signal used to synchronize cascaded PLAYER
devices in point-to-point applications.
The signal is asserted when all of the cascaded PLAYER devices have the
Cascade Mode (CM) bit of Mode Register (MR) set to one, and all of the
Cascade Ready pins of the cascaded PLAYER devices have been released.
For further information, refer to Section 4.4, Cascade Mode of Operation.
CR
30
O
Cascade Ready: An Open Drain output signal used to synchronize cascaded
PLAYER devices in point-to-point applications.
The signal is released (i.e. an Open Drain line is released) when all the
cascaded PLAYER devices have the Cascade Mode (CM) bit of the Mode
Register (MR) set to one and a JK symbol pair has been received.
For further information, refer to Section 4.4, Cascade Mode of Operation.
63
6.0 Pin Descriptions (Continued)
POWER AND GROUND
All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common 0V supply.
Symbol
Pin No.
I/O
Description
GND
3
Ground: Power supply return for Control Bus Interface CMOS I/Os.
VCC
6
Power: Positive 5V power supply ( g 5% relative to ground) for Control Bus Interface
CMOS I/Os.
GND
12
Ground: Power supply return for internal CMOS logic.
GND
20
Ground: Power supply return for Port A Interface CMOS I/Os.
VCC
22
Power: Positive 5V power supply ( g 5% relative to ground) for the Port A Interface
CMOS I/Os.
GND
24
Ground: Power supply return to internal CMOS logic.
VCC
38
Power: Positive 5V power supply ( g 5% relative to ground) for internal ECL logic.
GND
41
Ground: Power supply return for internal ECL logic.
VCC
44
Power: Positive 5V power supply ( g 5% relative to ground) for the Serial Interface ECL I/
Os.
GND
47
Ground: Power supply return for internal ECL logic.
VCC
50
Power: Positive 5V power supply ( g 5% relative to ground) for the Serial Interface ECL I/
Os.
GND
62
Ground: Power supply return for internal CMOS logic.
VCC
64
Power: Positive 5V power supply ( g 5% relative to ground) for the Port A Interface
CMOS I/Os.
GND
66
Ground: Power supply return for Port A Interface CMOS I/Os.
VCC
81
Power: Positive 5V power supply ( g 5% relative to ground) for internal CMOS logic.
GND
84
Ground: Power supply return for internal CMOS logic.
NO CONNECT PINS
Symbol
Pin No.
I/O
Description
N/C
31
No Connect: Not used by the PLAYER device
N/C
32
No Connect: Not used by the PLAYER device
N/C
54
No Connect: Not used by the PLAYER device
N/C
55
No Connect: Not used by the PLAYER device
64
6.0 Pin Descriptions (Continued)
6.2 DP83255
The pin descriptions for the DP83255 are divided into six functional interfaces; Serial Interface, PHY Port Interface, Control Bus
Interface, Clock Interface, and Miscellaneous Interface.
For a Pinout Summary List, refer to Table 6-2.
TL/F/10386 – 21
Order Number DP83255AVF
See NS Package Number VF132A
FIGURE 6-2. DP83255 132-Pin PQFP Pinout
65
6.0 Pin Descriptions (Continued)
TABLE 6-2. DP83255 Pinout Summary
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
1
CMOS Logic Ground
GND
2
Control Bus Datak2l
CBD2
I/O
3
Control Bus Datak3l
CBD3
I/O
4
CMOS I/O Ground
GND
5
Control Bus Datak4l
CBD4
I/O
6
Control Bus Datak5l
CBD5
I/O
7
CMOS I/O Power
VCC
8
Control Bus Datak6l
CBD6
I/O
TTL
9
Control Bus Datak7l
CBD7
I/O
TTL
10
Control Bus Data Parity
CBP
I/O
TTL
11
Enable Pin 0
EP0
O
TTL
12
Enable Pin 1
EP1
O
TTL
13
No Connect
N/C
14
No Connect
N/C
15
No Connect
N/C
16
No Connect
N/C
17
No Connect
N/C
18
No Connect
N/C
19
No Connect
N/C
20
CMOS Logic Ground
GND
21
Control Bus Data Parity Enable
CBPE
I
TTL
22
Sense Pin 0
SP0
I
TTL
23
Sense Pin 1
SP1
I
TTL
24
PHY Port A Indicate Parity
AIP
O
TTL
25
PHY Port A Request Parity
ARP
I
TTL
26
PHY Port A Indicate Control
AIC
O
TTL
27
PHY Port A Request Control
ARC
I
TTL
28
PHY Port A Indicate Datak7l
AID7
O
TTL
29
PHY Port A Request Datak7l
ARD7
I
TTL
30
PHY Port A Indicate Datak6l
AID6
O
TTL
31
PHY Port A Request Datak6l
ARD6
I
TTL
32
CMOS I/O Ground
GND
33
PHY A Indicate Datak5l
AID5
O
34
PHY A Request Datak5l
ARD5
I
35
CMOS I/O Power
VCC
66
a 0V
TTL
TTL
a 0V
TTL
TTL
a 5V
a 0V
a 0V
TTL
TTL
a 5V
6.0 Pin Descriptions (Continued)
TABLE 6-2. DP83255 Pinout Summary (Continued)
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
36
PHY A Indicate Datak4l
AID4
O
TTL
37
PHY A Request Datak4l
ARD4
I
TTL
38
CMOS Logic Ground
GND
39
PHY Port A Indicate Datak3l
AID3
40
PHY Port A Request Datak3l
41
PHY Port A Indicate Datak2l
42
a 0V
O
TTL
ARD3
I
TTL
AID2
O
TTL
PHY Port A Request Datak2l
ARD2
I
TTL
43
PHY Port A Indicate Datak1l
AID1
O
TTL
44
PHY Port A Request Datak1l
ARD1
I
TTL
45
PHY Port A Indicate Datak0l
AID0
O
TTL
46
Port A Request Datak0l
ARD0
I
TTL
47
Cascade Start
CS
I
TTL
48
Cascade Ready
CR
O
Open Drain
49
No Connect
N/C
50
No Connect
N/C
51
No Connect
N/C
52
No Connect
N/C
53
No Connect
N/C
54
No Connect
N/C
55
No Connect
N/C
56
No Connect
N/C
57
Clock Detect
CD
I
TTL
58
Signal Detect
TTLSD
I
TTL
59
External Loopback Enable
ELB
O
TTL
60
Receive Bit Clock a
RXC a
I
ECL
61
Receive Bit Clock b
RXCb
I
62
ECL Logic Power
VCC
63
Receive Data a
RXD a
I
64
Receive Data b
RXDb
I
ECL
a 5V
ECL
ECL
65
ECL Logic Ground
GND
66
External Loopback Data a
LBD a
O
67
External Loopback Data b
LBDb
O
68
ECL I/O Power
VCC
69
Transmit Data a
TXD a
O
ECL
70
Transmit Data b
TXDb
O
ECL
67
a 0V
ECL
ECL
a 5V
6.0 Pin Descriptions (Continued)
TABLE 6-2. DP83255 Pinout Summary (Continued)
Pin No.
Signal Name
Symbol
I/O
ECL/TTL/Open
Drain/Power
71
ECL Logic Ground
GND
72
Transmit Bit Clock a
TXC a
I
73
Transmit Bit Clock b
TXCb
I
74
ECL Logic Power
VCC
75
Transmit Byte Clock a
TBC a
I
ECL
76
Transmit Byte Clock b
TBCb
I
ECL
77
FOTX Enable Level
TEL
I
TTL
78
No Connect
N/C
79
No Connect
N/C
80
No Connect
N/C
81
No Connect
N/C
82
No Connect
N/C
83
No Connect
N/C
84
No Connect
N/C
85
No Connect
N/C
86
FOTX Enable
TXE
O
TTL
87
Local Byte Clock
LBC
I
TTL
88
PHY Port B Indicate Datak0l
BID0
O
TTL
89
PHY Port B Request Datak0l
BRD0
I
TTL
90
PHY Port B Indicate Datak1l
BID1
O
TTL
91
PHY Port B Request Datak1l
BRD1
I
TTL
92
PHY Port B Indicate Datak2l
BID2
O
TTL
93
PHY Port B Request Datak2l
BRD2
I
TTL
94
PHY Port B Indicate Datak3l
BID3
O
TTL
95
PHY Port B Request Datak3l
BRD3
I
TTL
96
CMOS Logic Ground
GND
97
PHY Port B Indicate Datak4l
BID4
O
TTL
98
PHY Port B Request Datak4l
BRD4
I
TTL
99
CMOS I/O Power
VCC
100
PHY Port B Indicate Datak5l
BID5
O
TTL
101
PHY Port B Request Datak5l
BRD5
I
TTL
102
CMOS I/O Ground
GND
103
PHY Port B Indicate Datak6l
BID6
104
PHY Port B Request Datak6l
105
PHY Port B Indicate Datak7l
68
a 0V
ECL
ECL
a 5V
a 0V
a 5V
a 0V
O
TTL
BRD6
I
TTL
BID7
O
TTL
6.0 Pin Descriptions (Continued)
TABLE 6-2. DP83255 Pinout Summary (Continued)
I/O
ECL/TTL/Open
Drain/Power
BRD7
I
TTL
BIC
O
TTL
PHY Port B Request Control
BRC
I
TTL
109
PHY Port B Indicate Parity
BIP
O
TTL
110
PHY Port B Request Parity
BRP
I
TTL
111
E PLAYER Device Reset
RST
I
TTL
112
Read/ E Write
R/W
I
TTL
113
Chip Enable
CE
I
TTL
114
E Interrupt
INT
O
Open Drain
115
No Connect
N/C
116
No Connect
N/C
117
No Connect
N/C
118
No Connect
N/C
119
No Connect
N/C
120
No Connect
N/C
121
No Connect
N/C
122
No Connect
N/C
123
E Acknowledge
ACK
O
Open Drain
124
Control Bus Addressk0l
CBA0
I
TTL
125
Control Bus Addressk1l
CBA1
I
TTL
126
Control Bus Addressk2l
CBA2
I
TTL
127
Control Bus Addressk3l
CBA3
I
TTL
128
Control Bus Addressk4l
CBA4
I
129
CMOS Logic Power
VCC
130
Control Bus Datak0l
CBD0
I/O
131
Control Bus Datak1l
CBD1
I/O
132
CMOS Logic Ground
GND
Pin No.
Signal Name
106
PHY Port B Request Datak7l
107
PHY Port B Indicate Control
108
Symbol
69
TTL
a 5V
TTL
TTL
a 0V
6.0 Pin Descriptions (Continued)
SERIAL INTERFACE
The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)
sublayer.
The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FORX), Clock
Recovery Device (CRD device), and Clock Distribution Device (CDD device).
Pin No.
I/O
CD
Symbol
57
I
Clock Detect: A TTL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXC g ) is properly synchronized with the Receive Data (RXD g ).
Description
TTLSD
58
I
Signal Detect: A TTL input signal from the Clock Recovery Device indicating that a
signal is being received by the Fiber Optic Receiver.
RXD a
RXDb
63
64
I
Receive Data: Differential 100K ECL, 125 Mbps serial data input signals from the Clock
Recovery Device.
TXD a
TXDb
69
70
O
Transmit Data: Differential, 100K ECL, 125 Mbps serial data output signals to the Fiber
Optic Transmitter.
ELB
59
O
External Loopback Enable: A TTL output signal to the Clock Recovery Device which
enables/disables loopback data through the Clock Recovery Device. This signal is
controlled by the Mode Register.
LBD a
LBDb
66
67
O
Loopback Data: Differential, 100K ECL, 125 Mbps, serial external loopback data output
signals to the Clock Recovery Device.
When the PLAYER device is not in external loopback mode, the LBD a signal is kept
high and the LBDb signal is kept low.
TEL
77
I
FOTX Enable Level: A TTL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level.
TXE
86
O
FOTX Enable: A TTL output signal to enable/disable the Fiber Optic Transmitter. The
output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)
bit in the Mode Register, the TM2 – TM0 bits in the Current Transmit State Register, and
also the input to the TEL pin.
The following rules summarizes the output of the TXE pin:
(1) If TE e 0 and TEL e GND, then TXE e VCC
(2) If TE e 0 and TEL e VCC, then TXE e GND
(3) If TE e 1 and OTM and TEL e GND, then TXE e VCC
(4) If TE e 1 and OTM and TEL e VCC, then TXE e GND
(5) If TE e 1 and not OTM and TEL e GND, then TXE e GND
(6) If TE e 1 and not OTM and TEL e VCC, then TXE e VCC
70
6.0 Pin Descriptions (Continued)
PHY PORT INTERFACE
The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access Control (MAC)
sublayer or other PLAYER Devices. The DP83255 Device has two PHY Port Interfaces. The AÐRequest and AÐIndicate paths
form one PHY Port Interface and the BÐRequest and BÐIndicate paths form the second PHY Port Interface. Each path
consists of an odd parity bit, a control bit, and two 4-bit symbols.
Refer to Section 3.3, the Configuration Switch, for more information.
Symbol
Pin No.
I/O
Description
AIP
24
O
PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port A Indicate signals (AIP, AIC, and AIDk7:0l).
AIC
26
O
PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(AIDk7:4l and AIDk3:0l) are either control symbols (AIC e 1) or data symbols (AIC
e 0).
AID7
AID6
AID5
AID4
28
30
33
36
O
PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control
symbol.
AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.
AID3
AID2
AID1
AID0
39
41
43
45
O
PHY Port A Indicate Data: TTL output signals representing the second 4-bit data/
control symbol.
AID3 is the most significant bit and AID0 is the least significant bit of the second symbol.
ARP
25
I
PHY Port A Request Parity: A TTL input signal representing odd parity for the 10-bit
wide Port A Request signals (ARP, ARC, and ARDk7:0l).
ARC
27
I
PHY Port A Request Control: A TTL input signal indicating that the two 4-bit symbols
(ARDk7:4l and ARDk3:0l) are either control symbols (ARC e 1) or data symbols
(ARC e 0).
ARD7
ARD6
ARD5
ARD4
29
31
34
37
I
PHY Port A Request Data: TTL input signals representing the first 4 bit data/control
symbol.
ARD7 is the most significant bit and ARD4 is the least significant bit of the first symbol.
ARD3
ARD2
ARD1
ARD0
40
42
44
46
I
PHY Port A Request Data: TTL input signals representing the second 4-bit data/control
symbol.
ARD3 is the most significant bit and ARD0 is the least significant bit of the second
symbol.
71
6.0 Pin Descriptions (Continued)
PHY PORT INTERFACE (Continued)
Pin No.
I/O
BIP
Symbol
109
O
PHY Port B Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port B Indicate signals (BIP, BIC, and BIDk7:0l).
Description
BIC
107
O
PHY Port B Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(BIDk7:4l and BIDk3:0l) are either control symbols (BIC e 1) or data symbols (BIC
e 0).
BID7
BID6
BID5
BID4
105
103
100
97
O
PHY Port B Indicate Data: TTL output signals representing the first 4-bit data/control
symbol.
BID7 is the most significant bit and BID4 is the least significant bit of the first symbol.
BID3
BID2
BID1
BID0
94
92
90
88
O
PHY Port B Indicate Data: TTL output signals representing the second 4-bit data/
control symbol.
BID3 is the most significant bit and BID0 is the least significant bit of the second symbol.
BRP
110
I
PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit
wide Port B Request signals (BRP, BRC, and BRDk7:0l).
BRC
108
I
PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols
(BRDk7:4l) and BRDk3:0l) are either control symbols (BRC e 1) or data symbols
(BRC e 0).
BRD7
BRD6
BRD5
BRD4
106
104
101
98
I
PHY Port B Request Data: TTL input signals representing the first 4-bit data/control
symbol.
BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.
BRD3
BRD2
BRD1
BRD0
95
93
91
89
I
PHY Port B Request Data: TTL input signals representing the second 4-bit data/control
symbol.
BRD3 is the most significant bit and BRD0 is the least significant bit of the second
symbol.
72
6.0 Pin Descriptions (Continued)
CONTROL BUS INTERFACE
The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMT).
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides
access to 32 8-bit internal registers.
Refer to Figure 22 , Control Bus Timing Diagram, for further information.
Pin No.
I/O
Description
CE
Symbol
113
I
Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a
read or write cycle. R/W, CBAk4:0l, CBP, and CBDk7:0l must be valid at the time CE
is low.
R/W
112
I
Read/ E Write: A TTL input signal which indicates a read Control Bus cycle (R/W e 1),
or a write Control Bus cycle (R/W e 0). This signal must be valid when CE is low and
held valid until ACK becomes low.
ACK
123
O
E Acknowledge: An active low, TTL, open drain output signal which indicates the
completion of a read or write cycle.
During a read cycle, CBDk7:0l are valid as long as ACK is low (ACK e 0).
During a write cycle, a microprocessor must hold CBDk7:0l valid until ACK becomes
low.
Once ACK is low, it will remain low as long as CE remains low (CE e 0).
INT
114
O
E Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt
condition has occurred. The Interrupt Condition Register (ICR) should be read in order to
determine the source of the interrupt. Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR)
CBA4
CBA3
CBA2
CBA1
CBA0
128
127
126
125
124
I
Control Bus Address: TTL input signals used to select the address of the register to be
read or written.
CBA4 is the most significant bit and CBA0 is the least significant bit of the address
signals.
CBPE
21
I
CBP
10
I/O
These signals must be valid when CE is low and held valid until ACK becomes low.
Control Bus Parity Enable: A TTL input signal which, during write cycles, will enable or
disable the Control Bus parity checker. Note that the Control Bus will always generate
parity during read cycles, regardless of the state of this signal.
Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control
Bus data (CBDk7:0l).
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (ICR).
CBD7
CBD6
CBD5
CBD4
CBD3
CBD2
CBD1
CBD0
9
8
6
5
3
2
131
130
I/O
Control Bus Data: Bidirectional, TTL signals containing the data to be read from or
written to a register.
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low.
73
6.0 Pin Descriptions (Continued)
CLOCK INTERFACE
The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either
the Clock Distribution Device or Clock Recovery Device.
Symbol
Pin No.
I/O
Description
LBC
87
I
Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock
Distribution Device. The Local Byte Clock is used by the PLAYER device’s internal
CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A
Interface, Port B Interface, and other miscellaneous I/Os.
RXC a
RXCb
60
61
I
Receive Bit Clock: Differential, 100k ECL, 125 MHz clock input signals from the Clock
Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the
Receive Data (RXD g ).
TXC a
TXCb
72
73
I
Transmit Bit Clock: Differential, 100k ECL, 125 MHz clock input signals from the Clock
Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the
Transmit Data (TXD g ).
TBC a
TBCb
75
76
I
Transmit Byte Clock: Differental, 100k ECL, 12.5 MHz clock input signals from the
Clock Distribution Device. The Transmit Byte Clock is used by the PLAYER device’s
internal Shift Register Block.
74
6.0 Pin Descriptions (Continued)
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded
PLAYER device’s synchronization signals, ground signals, and power signals.
Symbol
Pin No.
I/O
Description
RST
111
I
Reset: An active low, TTL, input signal which clears all registers. The signal must be kept
asserted for a minimum of 160 ns.
Once the RST signal is asserted, the PLAYER device should be allowed 960 ns to reset
internal logic. Note that bit zero of the Mode Register will be set to zero (i.e. Stop Mode).
See Section 4.2, Stop Mode of Operation for more information.
SP0
22
I
User Definable Sense Pin 0: A TTL input signal from a user defined source. Bit zero
(Sense Bit 0) of the User Definable Register (UDR) will be set to one if the signal is
asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control
Bus Interface, even if the signal is deasserted. This ensures that the Control Bus
Interface will record the source of events which can cause interrupts.
SP1
23
I
User Definable Sense Pin 1: A TTL input signal from a user defined source. Bit one
(Sense Bit 1) of the User Definable Register (UDR) will be set to one if the signal is
asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control
Bus Interface, even if the signal is deasserted. This ensures that the Control Bus
Interface will record the source of events which can cause interrupts.
EP0
11
O
User Definable Enable Pin 0: A TTL output signal allowing control of external logic
through the Control Bus Interface. EP0 is asserted/deasserted through bit two (Enable
Bit 0) of the User Definable Register (UDR). When Enable Bit 0 is set to zero, EP0 is
deasserted. When Enable Bit 0 is set to one, EP0 is asserted.
EP1
12
O
User Definable Enable Pin 1: A TTL output signal allowing control of external logic
through the Control Bus Interface. EP1 is asserted/deasserted through bit two (Enable
Bit 1) of the User Definable Register (UDR). When Enable Bit 1 is set to zero, EP1 is
deasserted. When Enable Bit 1 is set to one, EP1 is asserted.
CS
47
I
Cascade Start: A TTL input signal used to synchronize cascaded PLAYER devices in
point-to-point applications.
The signal is asserted when all of the cascaded PLAYER devices have the Cascade
Mode (CM) bit of the Mode Register (MR) set to one, and all of the Cascade Ready (CR)
pins of the cascaded PLAYER devices have been released.
For further information, refer to Section 4.4, Cascade Mode of Operation.
CR
48
O
Cascade Ready: An Open Drain output signal used to synchronize cascaded PLAYER
devices in point-to-point applications.
The signal is released when all the cascaded PLAYER devices have the Cascade Mode
(CM) bit of the Mode Register (MR) set to one and a JK symbol pair has been received.
For further information, refer to section 4.4, Cascade Mode of Operation.
75
6.0 Pin Descriptions (Continued)
POWER AND GROUND
All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common 0V ground
supply.
Symbol
Pin No.
I/O
Description
GND
1
Ground: Power supply return for internal CMOS logic.
GND
4
Ground: Power supply return for Control Bus Interface CMOS I/Os.
VCC
7
Power: Positive 5V power supply ( g 5% relative to ground) for Control Bus Interface
CMOS I/Os.
GND
20
Ground: Power supply return for internal CMOS logic.
GND
32
Ground: Power supply return for Port A Interface CMOS I/Os.
VCC
35
Power: Positive 5V power supply ( g 5% relative to ground) for the Port A Interface
CMOS I/Os.
GND
38
Ground: Power supply return for internal CMOS logic.
VCC
62
Power: Positive 5V power supply ( g 5% relative to ground) for internal ECL logic.
GND
65
Ground: Power supply return for internal ECL logic.
VCC
68
Power: Positive 5V power supply ( g 5% relative to ground) for the Serial Interface ECL I/
Os.
GND
71
Ground: Power supply return for internal ECL logic.
VCC
74
Power: Positive 5V power supply ( g 5% relative to ground) for internal ECL logic.
GND
96
Ground: Power supply return for internal CMOS logic.
VCC
99
Power: Positive 5V power supply ( g 5% relative to ground) for Port B Interface CMOS I/
Os.
GND
102
Ground: Power supply return for Port B Interface CMOS I/Os.
VCC
129
Power: 5V power supply ( g 5% relative to ground) for internal CMOS logic.
GND
132
Ground: Power supply return for internal CMOS logic.
76
6.0 Pin Descriptions (Continued)
NO CONNECT PINS
Symbol
Pin No.
N/C
13
I/O
No Connect: Not used by the PLAYER device
Description
N/C
14
No Connect: Not used by the PLAYER device
N/C
15
No Connect: Not used by the PLAYER device
N/C
16
No Connect: Not used by the PLAYER device
N/C
17
No Connect: Not used by the PLAYER device
N/C
18
No Connect: Not used by the PLAYER device
N/C
19
No Connect: Not used by the PLAYER device
N/C
49
No Connect: Not used by the PLAYER device
N/C
50
No Connect: Not used by the PLAYER device
N/C
51
No Connect: Not used by the PLAYER device
N/C
52
No Connect: Not used by the PLAYER device
N/C
53
No Connect: Not used by the PLAYER device
N/C
54
No Connect: Not used by the PLAYER device
N/C
55
No Connect: Not used by the PLAYER device
N/C
56
No Connect: Not used by the PLAYER device
N/C
78
No Connect: Not used by the PLAYER device
N/C
79
No Connect: Not used by the PLAYER device
N/C
80
No Connect: Not used by the PLAYER device
N/C
81
No Connect: Not used by the PLAYER device
N/C
82
No Connect: Not used by the PLAYER device
N/C
83
No Connect: Not used by the PLAYER device
N/C
84
No Connect: Not used by the PLAYER device
N/C
85
No Connect: Not used by the PLAYER device
N/C
115
No Connect: Not used by the PLAYER device
N/C
116
No Connect: Not used by the PLAYER device
N/C
117
No Connect: Not used by the PLAYER device
N/C
118
No Connect: Not used by the PLAYER device
N/C
119
No Connect: Not used by the PLAYER device
N/C
120
No Connect: Not used by the PLAYER device
N/C
121
No Connect: Not used by the PLAYER device
N/C
122
No Connect: Not used by the PLAYER device
77
7.0 Electrical Characteristics
7.1 ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
Supply Voltage
b 0.5
7.0
V
DCIN
Input Voltage
b 0.5
VCC a 0.5
V
DCOUT
Output Voltage
b 0.5
VCC a 0.5
V
Storage Temperature
b 65
150
§C
7.2 RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
TA
Operating Temperature
Conditions
Max
Units
4.75
Min
Typ
5.25
V
0
70
§C
7.3 DC ELECTRICAL CHARACTERISTICS
The DC characteristics are over the operating range, unless otherwise specified.
DC electrical characteristics for the TTL, TRI-STATE output signals of PHY, Port Interfaces, and CBUS Interface.
Symbol
Parameter
Conditions
IOZ1
TRI-STATE Leakage
(CBP & CBD7–0)
VOUT e VCC
IOZ2
TRI-STATE Leakage
(CBP & CBD7–0)
VOUT e VGND
IOZ3
TRI-STATE Leakage
(AID & BID)
VOUT e VCC
(Note 1)
IOZ4
TRI-STATE Leakage
(AID & BID)
VOUT e GND
Min
Typ
Max
Units
10
mA
b 10
mA
60
mA
b 500
mA
Note 1: Output buffer has a p-channel pullup device.
DC electrical characteristics for all TTL input signals and the following TTL output signals: External Loopback (ELB), Fiber Optic
Transmitter Enable (TXE), Enable Pin 0 (EP0), and Enable Pin 1 (EP1).
Symbol
Parameter
Conditions
Min
Typ
Max
VCC b 0.5
Units
VOH
Output High Voltage
IOH e b2 mA
VOL
Output Low Voltage
IOL e 4 mA
V
VIH
Input High Voltage
VIL
Input Low Voltage
0.8
V
VIC
Input Clamp Voltage
IIN e b18 mA
b 1.5
V
IIL
Input Low Current
VIN e GND
b 10
mA
IIH
Input High Current
VIN e VCC
a 10
mA
0.5
2.0
78
V
V
7.0 Electrical Characteristics (Continued)
DC electrical characteristics for all Open Drain output signals (INT, ACK and CR).
Symbol
Parameter
Conditions
VOL
Output Low Voltage
IOL e 8 mA
Min
Typ
Max
Units
0.5
V
IOZ
TRI-STATE Leakage
VOUT e VCC
10
mA
DC electrical characteristics for all 100k ECL input and output signals.
Symbol
Parameter
Conditions
Min
Max
Units
VOH
Output High Voltage
VIN e VIH (max)
VCC b 1.025
VCC b 0.880
V
VOL
Output Low Voltage
VIN e VIL(min)
VCC b 1.810
VCC b 1.620
V
VIH
Input High Voltage
VCC b 1.165
VCC b 0.880
V
VIL
Input Low Voltage
VCC b 1.810
VCC b 1.475
V
IL
Input Low Current
VIN e GND
IH
Input High Current
VIN e VCC
Typ
b 10
mA
100
mA
Supply Current electrical characteristics
Symbol
Parameter
Conditions
ICC
Total Supply
Current
LBC e 12.5 MHz
TXC e 125 MHz
Min
Typ
Max
Units
440*
mA
*Note: The PLAYER device has two pairs of differential ECL outputs, therefore 60 mA of the total supply current is actually consumed by external termination
resistors and the maximum current consumed by the PLAYER device alone is only 380 mA. The ECL termination current is calculated as follows:
VOHÐmax e VCC b 0.88V
VOLÐmax e VCC b 1.62V
Since the outputs are differential, the average output level is VCC b 1.25V. The test load per output is 50X at VCC b 2V, therefore the external load current
through the 50X resistor is:
ILOAD e [(VCC b 1.25) b (VCC b 2)]/50
e 0.015A
e 15 mA.
As result, two pairs of ECL outputs consume 60 mA.
79
7.0 Electrical Characteristics (Continued)
7.4 AC ELECTRICAL CHARACTERISTICS
The AC Electrical characteristics are over the operating range, unless otherwise specified.
AC Characteristics for the Control Bus Interface
Symbol
Parameter
Min
Max
Units
T1
CE Setup to LBC
5
ns
T2
LBC Period
80
ns
T3
LBC to ACK Low
T4
CE Low to ACK Low
T5
LBC Low to CBD(7-0) and CBP Valid
60
ns
T6
LBC to CBD(7-0) and CBP Active
60
ns
T7
CE Low to CBD(7-0) and CBP Active
225
475
ns
T8
CE Low to CBD(7-0) and CBP Valid
265
515
ns
T9
LBC Pulse Width High
35
45
ns
T10
LBC Pulse Width Low
35
T11
CE High to ACK High
T12
R/W, CBA(7-0), CBD(7-0) and
CBP Set up to CE Low
5
ns
T13
CE HIgh to R/W, CBA(7-0),
CBD(7-0) and CBP Hold Time
0
ns
T14a
R/W to LBC Setup Time
0
ns
T14b
CBA to LBC Setup Time
10
ns
T14c
CBD and CBP to LBC Setup Time
0
ns
T15
ACK Low to CE High Lead Time
0
ns
T16
CE Minimum Pulse Width High
20
ns
T17
CE High to CBD(7-0) and CBP TRI-STATE
T18
ACK High to CE Low
T19
CBD(7-0) Valid to ACK Low Setup
20
ns
T20a
LBC to R/W Hold Time
10
ns
T20b
LBC to CBA Hold Time
10
ns
T20c
LBC to CBD and CBP Hold Time
20
T21
LBC to INT Low
55
ns
T22
LBC to INT High
60
ns
290
T1 a (3 * T2) a T3
T4 (max)
T1 a (4 * T2) a T3
T7 (min)
T1 a (2 * T2) a T6
T7 (max)
T1 a (3 * T2) a T6
T8 (min)
T1 a (2 * T2) a T9 a T5
T8 (max)
T1 a (3 * T2) a T9 a T5
ns
ns
45
ns
45
ns
55
0
Asynchronous Definitions
T4 (min)
45
540
Note: Min/Max numbers are based on T2 e 80 ns and T9 e T10 e 40ns.
80
ns
ns
ns
7.0 Electrical Characteristics (Continued)
TL/F/10386 – 23
TL/F/10386 – 22
FIGURE 7-1. Control Bus Write Cycle Timing
FIGURE 7-2. Control Bus Read Cycle Timing
TL/F/10386 – 35
FIGURE 7-3. Control Bus Synchronous Write Cycle Timing
TL/F/10386 – 24
FIGURE 7-4. Control Bus Synchronous Read Cycle Timing
TL/F/10386 – 44
FIGURE 7-5. Control Bus Interrupt Timing
81
7.0 Electrical Characteristics (Continued)
AC Characteristics for the Clock Signals
Symbol
Parameter
Conditions
Min
T23
TBC to TXC Hold Time
(Note 1)
2
T24
TBC to TXC Setup Time
(Note 1)
2.5
T25
TBC to LBC Skew
T26
RXC Duty Cycle
T27
TXC Duty Cycle
T28
T29
Typ
Max
Units
ns
ns
10
22
ns
(Note 1)
3.0
5.0
ns
(Note 1)
3.5
4.5
ns
TBC Duty Cycle
37
43
ns
LBC Duty Cycle
35
45
ns
Note 1: RXC duty cycle, TXC duty cycle, and TBC to TXC setup time are not tested, but are assured by correlation with characterization data.
Note 2: When PLAYER is used in FDDI applications, TBC and LBC periods will be 80 ns and RXC and TXC periods will be 8 ns.
TL/F/10386 – 36
FIGURE 7-6. Clock Signals
82
7.0 Electrical Characteristics (Continued)
AC Characteristics for PHY Port Interfaces
Max
Units
T30
Symbol
LBC to Indicate Data Changes
from TRI-STATE to Data Valid
Parameter
Conditions
Min
Typ
70
ns
T31
LBC to Indicate Data Changes
from Active to TRI-STATE
70
ns
T32
LBC to Indicate Data Sustain
T33
LBC to Valid Indicate Data
T34
Request Data to LBC Setup Time
15
ns
T35
Request Data to LBC Hold Time
5
ns
7
ns
45
TL/F/10386 – 37
FIGURE 7-7. PHY Port Interface Timing
83
ns
7.0 Electrical Characteristics (Continued)
AC Characteristics for the Serial Interface
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T36
RXD to RXC Setup Time
2
T37
RXD to RXC Hold Time
2
ns
T38
TXC to TXD Change Time
T39
TXC to LBD Change Time
T40
CD Min Pulse Width
120
ns
T41
SD Min Pulse Width
120
ns
ns
8
8
TL/F/10386 – 38
FIGURE 7-8. Serial Interface Timing
84
ns
ns
7.0 Electrical Characteristics (Continued)
7.5 AC TEST CIRCUITS
TL/F/10386 – 28
FIGURE 7-10. Switching Test Circuit
for All TTL Output Signals
TL/F/10386 – 26
Note: S1 is closed for TPZL and TPLZ
S2 is closed for TPZH and TPHZ
S1 and S2 are open otherwise
FIGURE 7-9. Switching Test Circuit
for All TRI-STATE Output Signals
TL/F/10386 – 30
Note: CL e 30 pF includes scope and all stray capacitance without device in
test fixture
TL/F/10386 – 29
FIGURE 7-11. Switching Test Circuit
for All Open Drain Output Signals
(INT, ACK and CR)
FIGURE 7-12. Switching Test Circuit
for All ECL Input and Output Signals
85
Test Waveforms
TL/F/10386 – 39
FIGURE 7-13. ECL Output Test Waveform
TL/F/10386 – 40
Note: All CMOS inputs and outputs are TTL compatible
FIGURE 7-14. TTL Output Test Waveform
TL/F/10386 – 41
FIGURE 7-15. TRI-STATE Output Test Waveform
86
8.0 Detailed Descriptions
This section describes in detail several functions that had
been discussed previously in Section 3.0, Functional Descriptions.
8.2 NOISE EVENTS
A Noise Event is defined as follows:
A noise event is a noise byte, a byte of data which is not in
line with the current line state, indicating error or corruption.
8.1 FRAMING HOLD RULES
DETECTING JK
The JK symbol pair can be used to detect the beginning of a
frame during Active Line State (ALS) and Idle Line State
(ILS).
While the Line State Detector is in the Idle Line State the
PLAYER device ‘‘reframes’’ upon detecting a JK symbol
pair and enters the Active Line State.
During Active Line State, acceptance of a JK symbol (reframing) is allowed on any on-boundary JK which is detected at least 1.5 byte times after the previous JK.
During Active Line State, once reframed on a JK, the subsequent off-boundary JK is ignored, even if it is detected beyond 1.5 byte times after the previous JK.
During Active Line State, an Idle or Ending Delimiter (T)
symbol will allow reframing on any subsequent JK, if a JK is
detected at least 1.5 bytes times after the previous JK.
Noise Event e [SD # E CD] a
[SD # CD # PI # E (II a JK a AB)] a
[SD # CD # E PI # (PB e II) # AB]
Where:
#
a
e Logical AND
e Logical OR
E
e Logical NOT
SD e Signal Detect
CD e Clock Detect
PB e Previous Byte
PLS e Previous Line State
PI e PHY Invalid e HLS a QLS a MLS a
NLS a ÀULS # [PLS e
(ALS a ILS)] Ó
DETECTING HALT-HALT & HALT-QUIET
During Idle Line State, the detection of a Halt-Halt, or HaltQuiet symbol pair will still allow the reframing of any subsequent on-boundary JK.
Once a JK is detected during Active Line State, off-boundary Halt-Halt, or Halt-Quiet symbol pairs are ignored until the
Elasticity Buffer (EB) has an opportunity to recenter. They
are treated as violations.
After recentering on a Halt-Halt, or Halt-Quiet symbol pair,
all off-boundary Halt-Halt or Halt-Quiet symbol pairs are ignored until the EB has a chance to recenter during a line
state other than Active Line State (which may be as long as
2.8 byte times).
ILS e
ALS e
ULS e
HLS e
QLS e
MLS e
NLS e
ULS e
I
J
K
R
S
T
A
B
n
87
Idle Line State
Active Line State
Unknown Line State
Halt Line State
Quiet Line State
Master Line State
Noise Line State
Unknown Line State
e Idle symbol
e First symbol of start delimiter
e Second symbol of start delimiter
e Reset symbol
e Set symbol
e End delimiter
e n a R a S a T
e n a R a S a T a I
e Any data symbol
8.0 Detailed Descriptions (Continued)
8.3 LINK ERRORS
A Link Error is defined as follows:
Link Error Event e [ALS # (I E I a xV a Vx a
H E H)] a [ALS # E SD] a [ILS #
E (II a JK)] a [ILS # E SD)] a
[ULS # (PLS e ALS) # LinkÐErrorÐFlag # E SB # E (HH a HI a
II a JK)]
Set LinkÐErrorÐFlag e [ALS # (HH a NH a RH a
SH a TH)]
Clear LinkÐErrorÐFlag e [ALS # JK] a [ILS # JK] a
[ULS # (PLS e ALS #
LinkÐErrorÐFlag # E SB #
E (HH a HI a II a JK)]
Where:
E e Logical NOT
a e Logical OR
# e Logical AND
ILS e Idle Line State
ALS e Active Line State
ULS e Unknown Line State
x
I
H
J
K
V
R
S
T
N
e Any symbol
e Idle symbol
e Halt symbol
e First Symbol of start delimiter
e Second symbol of start delimiter
e Violation symbol
e Reset symbol
e Set symbol
e End delimiter symbol
e Data symbol converted to 0000 by the PLAY-
ER device Receiver Block in symbol pairs that
contain a data and a control symbol
PLS e Previous Line State
SD e Signal Detect
SB e Stuff Byte: Byte inserted by EB before a JK
symbol pair for recentering or due to off-axis
JK
88
8.0 Detailed Description (Continued)
8.4 REPEAT FILTER
The repeat filter prevents the propagation of code violations to the downstream station.
TL/F/10386 – 31
Note: Inputs to the Repeat Filter state machine are shown above the transition lines, while outputs from the state machine are shown below the transition lines.
Note: Abbreviations used in the Repeat Filter State Diagram are shown in Table VIII.
FIGURE 8-1. Repeat Filter State Diagram
89
8.0 Detailed Descriptions (Continued)
The Repeat Filter complies with the FDDI standard by observing the following:
1. In Repeat State, violations cause transitions to the Halt
State and two Halt symbol pairs are transmitted (unless
JK or Ix occurs) followed by transition to the Idle State.
2. When Ix is encountered, the Repeat Filter goes to the Idle
State, during which Idle symbol pairs are transmitted until
a JK is encountered.
3. The Repeat Filter goes to the Repeat State following a JK
from any state.
The END State, which is not part of the FDDI standard,
allows an R or S prior to a T within a frame to be recognized
as a violation. It also allows NT to end a frame as opposed
to being treated as a violation.
TABLE 8-1. Abreviations used in
the Repeat Filter State Diagram
FÐIDLE:
Force IdleÐTrue when not in Active
Transmit Mode
W:
Represents the symbols R, or S, or T
E TPARITY: Parity error
nn:
Data symbols (for C e 0 in the PHY-MAC
Interface)
N:
X:
VÊ :
Data portion of a control and data symbol
mixture
Any symbol (i.e. don’t care)
Violation symbols or symbols inserted by
the Receiver Block
IÊ :
Idle symbols or symbols inserted by the
Receiver Block
ALSZILSZ:
Active Line State or Idle Line State (i.e.
PHY Invalid)
E ALSZILSZ: Not in Active Line State nor in Idle Line
State (i.e. PHY Valid)
H:
Halt symbol
R:
Reset symbol
S:
Set symbol
T:
Frame ending delimiter
JK:
I:
V:
Frame start delimiter
Idle symbol (Preamble)
Code violations
90
8.0 Detailed Descriptions (Continued)
8.5 SMOOTHER
Notes:
SE: Smoother Enable
C: Preamble Counter
FÐIDLE: ForceÐIdle (Stop or ATM)
Xn: Current Byte
Xnb1: Previous Byte
W: RST
TL/F/10386 – 32
FIGURE 8-2. Smoother State Diagram
91
8.0 Detailed Descriptions (Continued)
Line State are Idle symbols, then the Symbol Decoder generates I’kILS as its output. Note that in this case the coded
byte is represented in the form Receive State (b7 – 4),
Known/Unknown Bit (b3) and the Last Known Line State
(b2 – 0). The Receive State is 4 bits long and it represents
either the PHY Invalid (0011) or the Idle Line State (1011)
condition. The Known/Unknown Bit shows if the symbols
received match the line state information in the last 3 bits.
During any line state other than Idle Line State or Active
Line State, the Symbol Decoder generates the code VÊ kLS
if the incoming symbols match the current line state. The
symbol decoder generates V’uLS if the incoming symbols
do not match the current line state.
8.6 NATIONAL BYTE-WIDE CODE FOR PHY-MAC INTERFACE
The PLAYER device outputs the National byte-wide code
from its PHY Port Indicate Output to the MAC device. Each
National byte-wide code may contain data or control codes
or the line state information of the connection. Table 8-2
lists all the possible outputs.
During Active Line State all data and control symbols are
being repeated to the PHY Port Indicate Output with the
exception of data in data-control mixture bytes. That data
sybmol is replaced by zero. If only one symbol in a byte is a
control symbol, the data symbol will be replaced by 0000
and the whole byte will be presented as control code. Note
that the Line State Detector recognizes the incoming data
to be in the Active Line State upon reception of the Starting
Delimiter (JK symbol pair).
During Idle Line State any non Idle symbols will be reflected
as the code I’uILS. If both symbols received during Idle
92
8.0 Detailed Descriptions (Continued)
Table 8-2.
Symbol 1
Control Bit
Data
Symbol 2
Control Bit
Data
National Code
Control Bit
Data
ALS
0,
n
0,
n
0,
n-n
ALS
0,
n
1,
C
1,
N-C
ALS
1,
C
0,
n
1,
C-N
ALS
1,
C
1,
C
1,
C-C
ILS
1,
I
1,
I
1,
I’-k-LS
ILS
1,
I
x,
Not I
1,
I’-u-LS
ILS
x,
Not I
1,
I
1,
I’-u-LS
ILS
x,
Not I
x,
Not I
1,
I’-u-LS
Stuff Byte during ILS
x,
x
x,
x
1,
I’-k-ILS
Not ALS and Not ILS
1,
M
1,
M
1,
V’-k-LS
Not ALS and Not ILS
1,
M
x,
Not M
1,
V’-u-LS
Not ALS and Not ILS
x,
Not M
1,
M
1,
V’-u-LS
Not ALS and Not ILS
x,
Not M
x,
Not M
1,
V’-u-LS
Stuff Byte during
Not ILS
x,
x
x,
x
1,
V’-k-LS, V’-u-LS
or I’-u-ILS
EB Overflow/Underflow
1,
0011 1011
SMT PI Connnection (LSU)
1,
0011 1010
Current Line State
Where:
n e Any data symbol in À0, 1, 2, ... F Ó
C e Any control symbol in ÀV, R, S, T, I, H Ó
N e 0000 e Code for data symbol in a data control mixture byte
I e Idle Symbol
M e Any symbol that matches the current line state
I’ e 1011 e First symbols of the byte in Idle Line State
V’ e 0011 e PHY Invalid
LS e Line State
ALS e 000
ILS e 001
NSD e 010
MLS e 100
HLS e 101
QLS e 110
NLS e 111
u e 1 e Indicates symbol received does not match current line state
k e 0 e Indicates symbol received matches current line state
x e Don’t care
93
8.0 Detailed Descriptions (Continued)
Example:
Incoming 5B Code
Decoded 4B Code
National Byte-Wide Code (w/o parity)
98765 43210
C3210 C 3210
C 7653 3210
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)*
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
11000 10001 (JK)
1 1101 1 1101 (JK)
1 1101 1101 (JK Symbols)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
(More data ...)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
-----
- - - - - (xx)
0 - - - - 0 - - - - (xx)
0----
- - - - (Data Symbols)
01101 00111 (TR)
1 0101 1 0110 (TR)
1 0101 0110 (T and R Symbols)
00111 00111 (RR)
1 0110 1 0110 (RR)
1 0110 0110 (Two R Symbols)
11111 11111 (II)
1 1010 1 1010 (II)
1 1010 1010 (Idle Symbols)
11111 11111 (II)
1 1010 1 1010 (II)
1 1010 1010 (Idle Symbols)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 1011 1001 (I’-u-ILS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 0011 0101 (V’-k-HLS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 0011 0101 (V’-k-HLS)
00100 00100 (HH)
1 0001 1 0001 (HH)
1 0011 0101 (V’-k-HLS)
11111 11111 (II)
1 1010 1 1010 (II)
1 0011 1101 (V’-u-HLS)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
11111 11111 (II)
1 1010 1 1010 (II)
1 1011 0001 (I’-k-ILS)
*Assume the receiver is in the Idle Line State.
94
Physical Dimensions inches (millimeters)
Plastic Leaded Chip Carrier
Order Number DP83251V
NS Package Number V84A
95
DP83251/DP83255 PLAYER Device (FDDI Physical Layer Controller)
Physical Dimensions inches (millimeters) (Continued)
Plastic Quad Pack (VF)
Order Number DP83255AVF
NS Package Number VF132A
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