19-4898; Rev 3; 8/09 Low-Voltage SPI/3-Wire RTCs with Trickle Charger The low-voltage serial-peripheral interface (SPI™) DS1390/DS1391/DS1394 and the low-voltage 3-wire DS1392/DS1393 real-time clocks (RTCs) are clocks/calendars that provide hundredths of a second, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. One programmable time-of-day alarm is provided. A temperature-compensated voltage reference monitors the status of VCC and automatically disables the bus interface and switches to the backup supply if a power failure is detected. On the DS1390, a single open-drain output provides a CPU interrupt or a square wave at one of four selectable frequencies. The DS1391 replaces the SQW/INT pin with a RST output/ debounced input. The DS1390, DS1391, and DS1394 are programmed serially through an SPI-compatible, bidirectional bus. The DS1392 and DS1393 communicate over a 3-wire serial bus, and the extra pin is used for either a separate interrupt pin or a RST output/debounced input. All five devices are available in a 10-pin µSOP package, and are rated over the industrial temperature range. ♦ Reset Output/Debounced Input (DS1391/DS1393) ♦ Separate SQW and INT Output (DS1392) ♦ Trickle-Charge Capability ♦ SPI Supports Modes 0 and 2 (DS1394) ♦ SPI Supports Modes 1 and 3 (DS1390/DS1391) ♦ 3-Wire Interface (DS1392/DS1393) ♦ 4MHz at 3.0V and 3.3V ♦ 1MHz at 1.8V ♦ Three Operating Voltages: 1.8V ±5%, 3.0V ±10%, and 2.97 to 5.5V (DS1394: 3.3V ±10%) ♦ Industrial Temperature Range: -40°C to +85°C ♦ Underwriters Laboratories (UL) Recognized Ordering Information PART DS1390U-18+ TYP PINOPERATING PACKAGE VOLTAGE (V) 1.8 10 μSOP TOP MARK† 1390 rr-18 DS1390U-3+ 3.0 10 μSOP 1390 rr-3 DS1390U-33+ 3.3 10 μSOP 1390 rr-33 DS1390U-33/V+ 3.3 10 μSOP 1390 rr-33 DS1391U-18+ 1.8 10 μSOP 1391 rr-18 DS1391U-3+ 3.0 10 μSOP 1391 rr-3 DS1391U-33+ 3.3 10 μSOP 1391 rr-33 DS1392U-18+ 1.8 10 μSOP 1393 rr-18 DS1392U-3+ 3.0 10 μSOP 1392 rr-3 Embedded Time Stamping DS1392U-33+ 3.3 10 μSOP 1392 rr-33 Medical Devices DS1393U-18+ 1.8 10 μSOP 1393 rr-18 DS1393U-3+ 3.0 10 μSOP 1393 rr-3 DS1393U-33+ 3.3 10 μSOP 1393 rr-33 DS1394U-33+ 3.3 10 μSOP 1394 rr-33 Applications Hand-Held Devices GPS/Telematics Devices Features ♦ Real-Time Clock Counts Hundredths of Seconds, Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap-Year Compensation Valid Up to 2100 ♦ Output Pin Configurable as Interrupt or Square Wave with Programmable Frequency of 32.768kHz, 8.192kHz, 4.096kHz, or 1Hz (DS1390/DS1393/DS1394 Only) DS1390–DS1394 General Description Note: All devices are rated for the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. †A “+” anywhere on the top mark denotes a lead(Pb)free/RoHS-compliant package. rr = Revision code on second line of top mark. ♦ One Time-of-Day Alarm ♦ Power-Fail Detect and Switch Circuitry Typical Operating Circuits and Pin Configurations appear at end of the data sheet. SPI is a trademark of Motorola, Inc. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Voltage Range on Inputs Relative to Ground ...............................................-0.3V to (VCC + 0.3V) Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage (Note 2) SYMBOL VCC MIN 2.97 TYP 3.3 MAX 5.50 UNITS DS139x-33 CONDITIONS DS139x-3 2.7 3.0 3.3 V DS139x-18 1.71 1.8 VCC + 0.5 V +0.3 x VCC V 5.5 V Logic 1 VIH (Note 2) 0.7 x VCC Logic 0 VIL (Note 2) -0.3 Supply Voltage, Pullup SQW/INT, SQW, INT, VCC = 0V VPU (Note 2) VBACKUP Voltage (Note 2) Power-Fail Voltage (Note 2) Trickle-Charge Current-Limiting Resistors Input Leakage I/O Leakage VBACKUP VPF 1.89 -33 1.3 3.0 VCC(MAX) -3 1.3 3.0 3.7 -18 1.3 3.0 3.7 -33 2.70 2.88 2.97 -3 2.45 2.6 2.70 -18 1.51 1.6 1.71 R1 (Notes 3, 4) 250 R2 (Notes 3, 5) 2000 R3 (Notes 3, 6) ILI (Note 7) V V 4000 -1 +1 μA ILO (Note 8) -1 +1 μA RST Pin I/O Leakage ILORST (Note 9) -200 +10 μA DOUT Logic 1 Output IOHDOUT DOUT Logic 0 Output IOHDOUT Logic 0 Output (DS1390/DS1393/DS1394 SQW/INT; DS1392 SQW, INT; DS1391/DS1393 RST) VCC Active Supply Current (Note 10) 2 -33, -3 (VOH = 0.85 x VCC) -18 (VOH = 0.80 x VCC) -1 0.750 -33, -3 (VOL = 0.15 x VCC) 3 -18 (VOL = 0.20 x VCC) 2 mA mA VCC > 1.71V; VOL = 0.4V 3.0 mA 1.3V < VCC < 1.71V; VOL = 0.4V 250 μA IOLSIR ICCA -33 2 -3 2 -18 500 _____________________________________________________________________ mA μA Low-Voltage SPI/3-Wire RTCs with Trickle Charger (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER VCC Standby Current (Note 11) VBACKUP Leakage Current (VBACKUP = 3.7V, VCC = VCC(MAX)) SYMBOL ICCS TYP 115 MAX 175 UNITS -33 CONDITIONS MIN -3 80 125 μA -18 60 100 15 100 nA TYP MAX UNITS IBACKUPLKG DC ELECTRICAL CHARACTERISTICS (VCC = 0V, VBACKUP = 3.7V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN VBACKUP Current OSC On, SQW Off IBACKUP1 (Note 12) 500 1000 nA VBACKUP Current OSC On, SQW On (32kHz) IBACKUP2 (Note 12) 600 1150 nA VBACKUP Current OSC On, SQW On, VBACKUP = 3.0V, TA = +25°C IBACKUP3 (Note 12) 600 1000 nA IBACKUPDR (Note 12) 25 100 nA TYP MAX UNITS VBACKUP Current, OSC Off (Data Retention) AC ELECTRICAL CHARACTERISTICS—SPI INTERFACE (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SCLK Frequency (Note 13) SYMBOL f SCLK CONDITION MIN 2.7V VCC 5.5V 0 4 1.71V VCC 1.89V 0 1 MHz Data to SCLK Setup tDC (Notes 13, 14) 30 ns SCLK to Data Hold tCDH (Notes 13, 14) 30 ns SCLK to Data Valid (Notes 13, 14, 15) tCDD SCLK Low Time (Note 13) tCL SCLK High Time (Note 13) tCH SCLK Rise and Fall 2.7V VCC 5.5V 80 1.71V VCC 1.89V 160 2.7V VCC 5.5V 110 1.71V VCC 1.89V 400 2.7V VCC 5.5V 110 1.71V VCC 1.89V 400 tR, tF ns ns ns 200 ns CS to SCLK Setup (Note 13) tCC 400 ns SCLK to CS Hold (Note 13) tCCH 100 ns CS Inactive Time (Note 13) tCWH CS to Output High Impedance tCDZ 2.7V VCC 5.5V 400 1.71V VCC 1.89V 500 (Notes 13, 14) ns 40 ns _____________________________________________________________________ 3 DS1390–DS1394 RECOMMENDED DC OPERATING CONDITIONS (continued) DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger CS tCC tR tF tCH SCLK tCL tCDH W/R DIN tCDZ tCDD tDC A6 DOUT A0 D7 HIGH IMPEDANCE D0 CPHA = 1 WRITE ADDRESS BYTE READ DATA BYTE NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 1a. Timing Diagram—SPI Read Transfer (Mode 3) CS tCC tR tF tCL SCLK tCDH tCH tCDD tDC DIN DOUT W/R A6 tCDZ A0 HIGH IMPEDANCE D7 D0 CPHA = 0 WRITE ADDRESS BYTE NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 0. Figure 1b. Timing Diagram—SPI Read Transfer (Mode 0) 4 _____________________________________________________________________ READ DATA BYTE Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 CPHA = 1 tCWH CS tCC tR tCCH tF tCL SCLK tCH tCDH tDC DIN A6 W/R A0 D7 WRITE ADDRESS BYTE D0 READ DATA BYTE DOUT HIGH IMPEDANCE NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 2a. Timing Diagram—SPI Write Transfer (Mode 3) CPHA = 0 tCWH CS tCC tR tCCH tF tCL SCLK tCDH tCH tDC DIN W/R A6 A0 WRITE ADDRESS BYTE D7 D0 READ DATA BYTE HIGH IMPEDANCE DOUT NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 0. Figure 2b. Timing Diagram—SPI Write Transfer (Mode 0) _____________________________________________________________________ 5 DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger AC ELECTRICAL CHARACTERISTICS—3-WIRE INTERFACE (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C.) (Note 1) (Figures 3, 4) PARAMETER SCLK Frequency (Note 13) SYMBOL f SCLK CONDITION MIN TYP MAX 2.7V VCC 5.5V 0 4 1.71V VCC 1.89V 0 1 UNITS MHz Data to SCLK Setup tDC (Notes 13, 14) 30 ns SCLK to Data Hold tCDH (Notes 13, 14) 30 ns SCLK to Data Valid (Notes 13, 14, 15) tCDD SCLK Low Time (Note 13) tCL SCLK High Time (Note 13) tCH SCLK Rise and Fall 2.7V VCC 5.5V 80 1.71V VCC 1.89V 160 2.7V VCC 5.5V 110 1.71V VCC 1.89V 400 2.7V VCC 5.5V 110 1.71V VCC 1.89V 400 ns ns ns tR, tF 200 ns CS to SCLK Setup tCC (Note 13) 400 ns SCLK to CS Hold tCCH (Note 13) 100 ns CS Inactive Time (Note 13) tCWH CS to Output High Impedance tCDZ 2.7V VCC 5.5V 400 1.71V VCC 1.89V 500 ns (Note 13, 14) 40 ns TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Pushbutton Debounce SYMBOL CONDITIONS MIN PBDB 160 200 ms Reset Active Time tRST 160 200 ms Oscillator Stop Flag (OSF) Delay tOSF 6 (Note 16) _____________________________________________________________________ 100 ms Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 CE tCC tR tF SCLK tCL tCDZ tCH tCDH tCDD tDC I/O A0 A1 R/W D0 D7 READ DATA BYTE WRITE ADDRESS BYTE Figure 3. Timing Diagram—3-Wire Read Transfer tCWH CE tCC tR tCCH tF SCLK tCL tCH tCDH tDC I/O A0 A1 R/W WRITE ADDRESS BYTE D0 D7 WRITE DATA BYTE Figure 4. Timing Diagram—3-Wire Write Transfer _____________________________________________________________________ 7 DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40°C to +85°C) (Figures 5, 6) PARAMETER SYMBOL VCC Detect to Recognize Inputs (VCC Rising) tRST CONDITIONS MIN (Note 17) TYP MAX UNITS 160 200 ms VCC Fall Time; VPF(MAX) to VPF(MIN) tF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tR 0 µs VCC VPF(MAX) VPF VPF VPF(MIN) tF tR tRPU tRST RST RECOGNIZED INPUTS DON'T CARE RECOGNIZED HIGH IMPEDANCE OUTPUTS VALID VALID Figure 5. Power-Up/Down Timing RST PBDB tRST Figure 6. Pushbutton Reset Timing 8 _____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger (TA = +25°C) MAX UNITS Capacitance on All Input Pins PARAMETER CIN 10 pF Capacitance on All Output Pins (High Impedance) CIO 10 pF WARNING: Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: SYMBOL CONDITIONS MIN TYP Negative undershoots below -0.3V while the part is in battery-backed mode can cause loss of data. Limits at -40°C are guaranteed by design and not production tested. All voltages are referenced to ground. The use of the 250Ω trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Use of the diode is not recommended for VCC < 3.0V. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A5h. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A6h. Measured at VCC = typ, VBACKUP = 0V, register 0Fh = A7h. SCLK, DIN, CS on DS1390/DS1391/DS1394; SCLK, and CE on DS1392/DS1393. DOUT, SQW/INT (DS1390/DS1393/DS1394), SQW, and INT (DS1392). The RST pin has an internal 50kΩ (typ) pullup resistor to VCC. ICCA—SCLK clocking at max frequency = 4MHz for 3V and 3.3V versions; 1MHz for 1.8V version; RST (DS1391/DS1393) inactive. Outputs are open. Specified with bus inactive. Measured with a 32.768kHz crystal attached to X1 and X2. Typical values measured at +25°C and 3.0VBACKUP. With 50pF load. Measured at VIH = 0.7 x VDD or VIL = 0.2 x VDD, 10ns rise/fall times. Measured at VOH = 0.7 x VDD or VOL = 0.2 x VDD. Measured from the 50% point of SCLK to the VOH minimum of SDO. The parameter tOSF is the time that the oscillator must be stopped for the OSF flag to be set over the voltage range of 0 ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBACKUP ≤ 5.5V. This delay applies only if the oscillator is enabled and running. If the EOSC bit is 1, the startup time of the oscillator is added to this delay. _____________________________________________________________________ 9 DS1390–DS1394 CAPACITANCE Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) IBACKUP vs. VBACKUP, BBSQ1 = 0 DS1390 TOC01 VCC= 0 SUPPLY CURRENT (nA) 500 450 400 350 300 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 VCC = 0V 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3 VBACKUP (V) VBACKUP (V) IBACKUP vs. TEMPERATURE VBACKUP = 3.0V OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 32768.00 DS1390 toc03 600 VCC = 0V 550 DS1390 toc04 SUPPLY CURRENT (nA) 550 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 300 DS1390 toc02 IBACKUP vs. VBACKUP, BBSQ1 = 1 600 32767.95 500 FREQUENCY (Hz) SUPPLY CURRENT (nA) DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger 450 400 350 32767.90 32767.85 300 250 32767.80 -40 -20 0 20 40 60 80 1.3 1.8 TEMPERATURE (°C) 10 ____________________________________________________________________ 2.3 2.8 3.3 3.8 SUPPLY (V) 4.3 4.8 5.3 Low-Voltage SPI/3-Wire RTCs with Trickle Charger PIN DS1390/ DS1391 DS1394 DS1392 DS1393 NAME 1 1 1 1 X1 2 2 2 2 X2 3 3 3 3 4 4 — — — — 4 5 5 5 6 6 — — — 6 CS SPI Chip-Select Input. This pin is used to select or deselect the part. 4 CE Chip Enable for 3-Wire Interface 5 GND Ground — DIN SPI Data Input. This pin is used to shift address and data into the part. INT Interrupt Output. This pin is used to output the interrupt signal, if enabled by the control register. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, INT functions when the device is powered by either VCC or VBACKUP. Reset. This active-low, open-drain output indicates the status of VCC relative to the V PF specification. As Vcc falls below V PF, the RST pin is driven low. When Vcc exceeds VPF, for tRST, the RST pin is driven high impedance. This pin is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. This pin has an internal, 50k (typ) pullup resistor to VCC. No external pullup resistors should be connected. If the crystal oscillator is disabled, the startup time of the oscillator is added to the tRST delay. — 9 — 6 RST 7 7 — — DOUT — — 7 7 I/O 8 8 8 8 SCLK — — Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a 6pF specified load capacitance (CL). Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. DC Backup Power Input for Primary Cell. This pin is a rechargeable battery/super cap or a secondary supply. UL recognized to ensure against VBACKUP reverse charging current when used with a lithium battery (www.maximic.com/qa/info/w/). This pin must be grounded if not used. Diodes in series between the battery and the VBACKUP pin may prevent proper operation. — 9 FUNCTION 9 SPI Data Output. Data is output on this pin when the part is in read mode. CMOS push-pull driver. Input/Output for 3-Wire Interface. CMOS push-pull driver. Serial Clock Input. This pin is used to control the timing of data into and out of the part. Square-Wave/Interrupt Output. This pin is used to output the programmable square wave or interrupt signal. When enabled by setting the ESQW bit to logic 1, the SQW/INT pin outputs one of four frequencies: 32.768kHz, SQW/INT 8.192kHz, 4.096kHz, or 1Hz. This pin is open drain and requires an external pullup resistor. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, SQW/INT functions when the device is powered by either VCC or VBACKUP. If not used, this pin can be left open. — — 9 — SQW Square-Wave Output. This pin is open drain and requires an external pullup resistor. The maximum voltage on this pin is 5.5V, independent of VCC or VBACKUP. If enabled, SQW functions when the device is powered by either VCC or VBACKUP. If not used, this pin can be left open. 10 10 10 10 VCC DC Power Pin for Primary Power Supply ____________________________________________________________________ 11 DS1390–DS1394 Pin Description Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 Functional Diagram X1 CL HUNDREDTHS-OFSECONDS GENERATOR CL X2 VCC GND VBACKUP VCC LEVEL DETECT, POWER SWITCH, WRITE PROTECT, TRICKLE CHARGER SQUARE-WAVE RATE SELECTOR, INT, MUX, RST OUTPUT SQW/INT (DS1390/93/94) N RST (DS1391) SQW (DS1392) REAL-TIME CLOCK WITH HUNDREDTHS OF SECONDS (DS1390/91/94) CS (DS1392/93) (CE) SCLK (DS1390/91/94) DIN ALARM REGISTERS BUS INTERFACE (DS1390/91/94) DOUT CONTROL/STATUS REGISTERS (DS1392/93) I/O TRICKLE REGISTER DS1390/DS1391/ DS1392/DS1393/DS1394 Detailed Description The DS1390–DS1394 RTCs are low-power clocks/calendars with alarms. Address and data are transferred serially through a 4-wire SPI interface for the DS1390 and DS1391 and through a 3-wire interface for the DS1392, DS1393, and DS1394. The DS1390/DS1391 operate as a slave device on the SPI serial bus. The DS1392/DS1393 operate using a 3-wire synchronous serial bus. Access is obtained by selecting the part by the CS pin (CE on DS1392/DS1393) and clocking data into/out of the part using the SCLK and DIN/DOUT pins (I/O on DS1392/DS1393). Multiple-byte transfers are supported within one CS low period (see the SPI Serial-Data Bus 12 section). The clocks/calendars provide hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The alarm functions are performed off all timekeeping registers, allowing the user to set high resolution alarms. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clocks operate in either the 24-hour or 12-hour format with an AM/PM indicator. All five devices have a built-in temperature-compensated voltage reference that detects power failures and automatically switches to the battery supply. Additionally, the devices can provide trickle charging of the backup voltage source, with selectable charging resistance and diode voltage drops. ____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the V CC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when V CC drops below V PF . If V PF is greater than VBACKUP, the device power is switched from VCC to V BACKUP when V CC drops below V BACKUP . Timekeeping operation and register data are maintained from the VBACKUP source until VCC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed after RST goes high (Figure 5). Oscillator Circuit All five devices use an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. If a crystal is used with the specified characteristics, the startup time is usually less than one second. Table 2. Crystal Specifications* PARAMETER SYMBOL Nominal Frequency fO Series Resistance ESR Load Capacitance CL MIN TYP MAX 32.768 kHz 55 6 UNITS kΩ pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Maxim Real-Time Clocks for additional specifications. Table 1. Power Control Clock Accuracy SUPPLY CONDITION READ/WRITE ACCESS) POWERED BY VCC < V PF, VCC < VBACKUP No VBACKUP VCC < V PF, VCC > VBACKUP No VCC VCC > V PF, VCC < VBACKUP Yes VCC VCC > V PF, VCC > VBACKUP Yes VCC The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 7 shows a typical PC board layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Maxim Real-Time Clocks for detailed information. LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE. GND Figure 7. Layout Example ____________________________________________________________________ 13 DS1390–DS1394 Power Control DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger Address Map The first method is to synchronize enabling the device (CE or CS) with the square wave or interrupt output (DS1390–DS1394). Enabling the device, either after detecting the falling edge of the interrupt output or the rising edge of the square-wave output, ensures that the two events are not simultaneous. Table 3 shows the address map for the DS1390– DS1393 RTC and RAM registers. The RTC registers are located in address locations 00h to 0Fh in read mode, and 80h to 8Fh in write mode. During a multibyte access, when the address pointer reaches 0Fh, it wraps around to location 00h. On the falling edge of the CS pin (DS1390/DS1391/DS1394) or the rising edge of CE (DS1392/DS1393), the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers if the main registers update during a read. To avoid rollover issues when writing to the time and date registers, all registers should be written before the hundredths-of-seconds registers reaches 99 (BCD). The second method is to read the hundredths of seconds register until the data for two consecutive reads match. With this method, the master must be able to read the register at least twice within the 10ms update period of the hundredths of seconds register. Either of the described methods ensures that the data in all the registers is correct. If the hundredths of seconds register is not used, it is also possible for the same problem to occur when reading the seconds register. The probability of an error is inversely proportional to the rate of the register's update frequency in relation to the hundredth of seconds register, so the error rate for the seconds register would be approximately 1.7ppb. The same methods used for the hundredth of seconds register would be used for the seconds register. When reading from the hundredths of seconds register, there is a possibility that the data transfer happens at the same time as an increment of the register. If this occurs, the data in the buffer may be incorrect. The chances of this happening is approximately 170ppb. There are two ways to deal with this. Table 3. Address Map WRITE READ ADDRESS ADDRESS 14 BIT 7 BIT 6 BIT 5 80h 00h 81h 01h 0 10 Seconds 82h 02h 0 10 Minutes BIT 4 BIT 3 Tenths of Seconds 83h 03h 0 12/24 84h 04h 0 0 85h 05h 0 0 86h 06h Century 0 87h 07h 88h 08h 89h 09h AM1 8Ah 0Ah AM2 AM/PM 10 Hour 10 Hour 0 0 BIT 2 BIT 1 BIT 0 FUNCTION RANGE Hundredths of Seconds Hundredths of Seconds 0–99 BCD Seconds Seconds 00–59 BCD Minutes Minutes 00–59 BCD Hours 1–12 +AM/PM 00–23 BCD Hour Day 1–7 BCD Date Date 01–31 BCD Month Month/ Century 01–12 + Century BCD 10 Year Year Year 00–99 BCD Tenths of Seconds Hundredths of Seconds Alarm Hundredths of Seconds 0–99 BCD 10 Seconds Seconds Alarm 00–59 BCD 10 Minutes Minutes Alarm 00–59 BCD 10 Date 0 10 Month 0 Day ____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger WRITE READ ADDRESS ADDRESS 8Bh 0Bh BIT 7 BIT 6 AM3 12/24 BIT 5 BIT 4 AM/PM 10 Hour BIT 3 BIT 2 BIT 1 BIT 0 Hour FUNCTION RANGE Alarm Hours 1–12 + AM/PM 00–23 BCD 10 Hour 8Ch 0Ch AM4 DY/DT 0 8Dh 8Eh 8Fh 0Dh 0Eh 0Fh EOSC OSF TCS3 10 Date BBSQI RS2 RS1 Day Alarm Day 1–7 BCD Date Alarm Date 01–31 BCD INTCN 0 AIE 0 X X X X 0 X 0 BBSQI RS2 RS1 ESQW 0 AIE 0 0 0 0 0 0 AF TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 DS1390/93/94 Control DS1391 DS1392 Status — Trickle Charger — Note: Unless otherwise specified, the state of the registers is not defined when power (VCC and VBACKUP) is first applied. X = General-purpose read/write bit. 0 = Always reads as zero. Hundredths-of-Seconds Generator The hundredths-of-seconds generator circuit shown in the functional diagram is a state machine that divides the incoming frequency (4096Hz) by 41 for 24 cycles and 40 for one cycle. This produces a 100Hz output that is slightly off during the short term, and is exactly correct every 250ms. The divide ratio is given by: Ratio = [41 x 24 + 40 x 1] / 25 = 40.96 Thus, the long-term average frequency output is exactly the desired 100Hz. Clock and Calendar The time and calendar information is obtained by reading the appropriate register bytes. See Table 3 for the RTC registers. The time and calendar are set or initial- ized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day-of-week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. The DS1390–DS1393 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to 23 hours). Changing the 12/24-hour modeselect bit requires that the hours data be re-entered, including the alarm register (if used). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. ____________________________________________________________________ 15 DS1390–DS1394 Table 3. Address Map (continued) DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger Alarms All five devices contain one time-of-day/date alarm. Writing to registers 88h through 8Ch sets the alarm. The alarm can be programmed (by the alarm enable and INTCN bits of the control register) to activate the SQW/INT or INT output on an alarm-match condition. The alarm can activate the SQW/INT or INT output while the device is running from V BACKUP if BBSQI is enabled. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 4). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 4 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to a logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the alarm-flag (AF) bit is set to logic 1. If the alarm-interrupt enable (AIE) is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the SQW/INT signal. Since the contents of register 08h are expected to normally contain a match value of 00–99 decimal, the codes F[0–9], and FF have been used to tell the part to mask the tenths or hundredths of seconds accordingly. Power-Up/Down, Reset, and Pushbutton Reset Functions A precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-of-tolerance condition occurs, an internal power-fail signal is generated that blocks read/write access to the device and forces the RST pin (DS1391/DS1393 only) low. When VCC returns to an in-tolerance condition, the internal power-fail signal is held active for tRST to allow the power supply to stabilize, and the RST (DS1391/ DS1393 only) pin is held low. If the EOSC bit is set to logic 1 (to disable the oscillator in battery-backup mode), the internal power-fail signal and the RST pin is kept active for tRST plus the startup time of the oscillator. The DS1391/DS1393 provide for a pushbutton switch to be connected to the RST output pin. When the DS1391/DS1393 are not in a reset cycle, it continuously monitors the RST signal for a low-going edge. If an edge is detected, the part debounces the switch by pulling the RST pin low and inhibits read/write access. After PBDB has expired, the part continues to monitor the RST line. If the line is still low, it continues to monitor the line looking for a rising edge. Upon detecting release, the part forces the RST pin low and holds it low for an additional PBDB. Table 4. Alarm Mask Bits REGISTE R 08H DY/DT ALARM REGISTER MASK BITS (BIT 7) AM4 AM3 AM2 AM1 ALARM RATE FFh X 1 1 1 1 Alarm every 1/100th of a second F[0–9]h X 1 1 1 1 Alarm when hundredths of seconds match [0–9][0–9] X 1 1 1 1 Alarm when tenths, hundredths of seconds match [0–9][0–9] X 1 1 1 0 Alarm when seconds, tenths, and hundredths of seconds match [0–9][0–9] X 1 1 0 0 Alarm when minutes, seconds, tenths, and hundredths of seconds match [0–9][0–9] X 1 0 0 0 Alarm when hours, minutes, seconds, tenths, and hundredths of seconds match [0–9][0–9] 0 0 0 0 0 Alarm when date, hours, minutes, seconds, tenths, and hundredths of seconds match [0–9][0–9] 1 0 0 0 0 Alarm when day, hours, minutes, seconds, tenths, and hundredths of seconds match 16 ____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger The DS1390–DS1394 have three additional registers (control, status, and trickle charger) that control the RTC, alarms, square-wave output, and trickle charger. Control Register (0D/8Dh) (DS1390/DS1393/DS1394 Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC 0 BBSQI RS2 RS1 INTCN 0 AIE Bit 7: Enable Oscillator (EOSC). When set to logic 0, this bit starts the oscillator. When this bit is set to logic 1, the oscillator is stopped whenever the device is powered by V BACKUP. The oscillator is always enabled when VCC is valid. This bit is enabled (logic 0) when VCC is first applied. Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI). This bit when set to logic 1 enables the square wave or interrupt output when VCC is absent and the DS1390/DS1392/DS1393/DS1394 are being powered by the VBACKUP pin. When BBSQI is logic 0, the SQW/INT pin (or SQW and INT pins) goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied. RS2 RS1 Bit 2: Interrupt Control (INTCN). This bit controls the SQW/INT signal. When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin. The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers then activates the SQW/INT (provided the alarm is also enabled). The corresponding alarm flag is always set, regardless of the state of the INTCN bit. The INTCN bit is set to logic 0 when power is first applied. Bit 0: Alarm Interrupt Enable (AIE). When set to logic 1, this bit permits the alarm flag (AF) bit in the status register to assert SQW/INT (when INTCN = 1). When the AIE bit is set to logic 0 or INTCN is set to logic 0, the AF bit does not initiate the SQW/INT signal. The AIE bit is disabled (logic 0) when power is first applied. SQUARE-WAVE OUTPUT FREQUENCY 0 0 1Hz 0 1 4.096kHz 1 0 8.192kHz 1 1 32.768kHz Control Register (0D/8Dh) (DS1391 Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC 0 X X X X 0 X Control bits used in the DS1390 become general-purpose, battery-backed, nonvolatile SRAM bits in the DS1391. ____________________________________________________________________ 17 DS1390–DS1394 Special-Purpose Registers DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger Control Register (0D/8Dh) (DS1392 Only) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC 0 BBSQI RS2 RS1 ESQW 0 AIE The INTCN bit used in the DS1390/DS1393/DS1394 becomes the SQW pin-enable bit in the DS1392. This bit powers up a zero, making SQW active. Status Register (0E/8Eh) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 0 0 0 AF Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time and may be used to judge the validity of the clock and calendar data. This bit is edge-triggered and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltage present on VCC and VBACKUP is insufficient to support oscillation. 3) The EOSC bit is turned off. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Bit 6: Alarm Flag (AF). A logic 1 in the AF bit indicates that the time matched the alarm registers. If the AIE bit is logic 1 and the INTCN bit is set to logic 1, the SQW/INT pin is also asserted. AF is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Trickle-Charge Register (0F/8Fh) The simplified schematic in Figure 8 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diode-select (DS) bits (bits 2 and 3) select whether or not a diode is connected between VCC and VBACKUP. If DS is 01, no diode is selected or if DS is 10, a diode is selected. The ROUT bits (bits 0 and 1) select the value of the resistor connected between V CC and VBACKUP. Table 5 shows the resistor selected by the resistor-select (ROUT) bits and the diode selected by the diode-select (DS) bits. Table 5. Trickle-Charge Register 18 TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 FUNCTION X X X X 0 0 X X X X X X 1 1 X X Disabled X X X X X X 0 0 Disabled 1 0 1 0 0 1 0 1 No diode, 250Ω resistor 1 0 1 0 1 0 0 1 One diode, 250Ω resistor 1 0 1 0 0 1 1 0 No diode, 2kΩ resistor 1 0 1 0 1 0 1 0 One diode, 2kΩ resistor 1 0 1 0 0 1 1 1 No diode, 4kΩ resistor 1 0 1 0 1 0 1 1 One diode, 4kΩ resistor 0 0 0 0 0 0 0 0 Initial default value—disabled Disabled ____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 TRICKLE-CHARGE REGISTER (8Fh WRITE, 0Fh READ) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 TCS3 TCS2 TCS1 TCS0 DS1 DS0 1 0F 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER BIT 1 BIT 0 ROUT1 ROUT0 TCS[3:0] = TRICKLE-CHARGE SELECT DS[1:0] = DIODE SELECT ROUT[1:0] = RESISTOR SELECT 1 OF 3 SELECT 1 OF 2 SELECT R1 250Ω R2 2kΩ VCC VBACKUP R3 4kΩ Figure 8. DS1390–DS1394 Programmable Trickle Charger Table 6. SPI Pin Function MODE CPHA CS SCLK SDI SDO Disable X High Input Disabled Input Disabled High-Z Write 0 Low CPOL* = 0, SCLK Rising; CPOL = 1, SCLK Falling Data Bit Latch High-Z Read 0 Low CPOL = 0, SCLK Falling; CPOL = 1, SCLK Rising X Next Data Bit Shift** Write 1 Low CPOL* = 1, SCLK Rising; CPOL = 0, SCLK Falling Data Bit Latch High-Z Read 1 Low CPOL = 1, SCLK Falling; CPOL = 0, SCLK Rising X Next Data Bit Shift** *CPOL is the clock-polarity bit set in the control register of the host microprocessor. **SDO remains at high-Z until 8 bits of data are ready to be shifted out during a read. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 3.3V is applied to V CC and a super cap is connected to VBACKUP. Also, assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) / 2kΩ ≈ 1.3mA As the super cap changes, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases. ____________________________________________________________________ 19 DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger SPI Serial-Data Bus The DS1390/DS1391/DS1394 provide a 4-wire SPI serial-data bus to communicate in systems with an SPI host controller. The DS1390/DS1391 support SPI modes 1 and 3, while the DS1394 supports SPI modes 0 and 2. Both devices support single-byte and multiple-byte data transfers for maximum flexibility. The DIN and DOUT pins are the serial-data input and output pins, respectively. The CS input initiates and terminates a data transfer. The SCLK pin synchronizes data movement between the master (microcontroller) and the slave (DS1390/DS1391) devices. The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. Input data (DIN) is latched on the internal strobe edge and output data (DOUT) is shifted out on the shift edge (Figure 9). There is one clock for each bit transferred. Address and data bits are transferred in groups of eight. Address and data bytes are shifted MSB first into the serial-data input (DIN) and out of the serial-data output (DOUT). Any transfer requires the address of the byte to specify a write or read, followed by one or more bytes of data. Data is transferred out of the DOUT pin for a read operation and into the DIN for a write operation (Figures 10 and 11). The address byte is always the first byte entered after CS is driven low. The most significant bit (W/R) of this byte determines if a read or write takes place. If W/R is 0, one or more read cycles occur. If W/R is 1, one or more write cycles occur. Data transfers can occur one byte at a time or in multiple-byte burst mode. After CS is driven low, an address is written to the DS1390/DS1391/DS1394. After the address, one or more data bytes can be written or read. For a single-byte transfer, one byte is read or written and then CS is driven high. For a multiple-byte transfer, however, multiple bytes can be read or written after the address has been written. Each read or write cycle causes the RTC register address to automatically increment. Incrementing continues until the device is disabled. The address wraps to 00h after incrementing to 0Fh (during a read) and wraps to 80h after incrementing to 8Fh (during a write). Note, however, that an updated copy of the time is only loaded into the useraccessible copy upon the falling edge of CS. Reading the RTC registers in a continuous loop does not show the time advancing. CPHA = 1 CPHA = 0 CS MODE 0 SHIFT DATA OUT (READ) DATA LATCH/SAMPLE (WRITE) MODE 1 DATA LATCH/SAMPLE (WRITE) SHIFT DATA OUT (READ) SCLK WHEN CPOL = 0 MODE 2 SHIFT DATA OUT (READ) DATA LATCH/SAMPLE (WRITE) SCLK WHEN CPOL = 1 Figure 9. Serial Clock as a Function of Microcontroller Clock-Polarity Bit 20 ____________________________________________________________________ MODE 3 DATA LATCH/SAMPLE (WRITE) SHIFT DATA OUT (READ) Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 CS SCLK (MODE 0) SCLK (MODE 1) DIN W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 HIGH IMPEDANCE DOUT Figure 10. SPI Single-Byte Write CS SCLK (MODE 0) SCLK (MODE 1) DIN W/R A6 DOUT A5 A4 A3 HIGH IMPEDANCE A2 A1 A0 D7 D6 D5 Figure 11. SPI Single-Byte Read ____________________________________________________________________ 21 DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger CS SCLK DIN WRITE ADDRESS BYTE DATA BYTE 0 DATA BYTE 1 DATA BYTE N DIN ADDRESS BYTE READ DOUT HIGH-IMPEDANCE DATA BYTE 0 DATA BYTE 1 DATA BYTE N Figure 12. SPI Multiple-Byte Burst Transfer CE SCLK I/O A0 A1 A2 A3 A4 A5 A6 W/R D0 D1 D2 D3 D4 D5 D6 D7 A3 A4 A5 A6 W/R D0 D1 D2 D3 D4 D5 D6 D7 Figure 13. 3-Wire Single-Byte Read CE SCLK I/O A0 A1 A2 Figure 14. 3-Wire Single-Byte Write 22 ____________________________________________________________________ Low-Voltage SPI/3-Wire RTCs with Trickle Charger The DS1392/DS1393 provide a 3-wire serial-data bus, and support both single-byte and multiple-byte data transfers for maximum flexibility. The I/O pin is the serial-data input/output pin. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1392/DS1393) devices. Input data is latched on the SCLK rising edge and output data is shifted out on the SCLK falling edge. There is one clock for each bit transferred. Address and data bits are transferred in groups of eight. Address and data bytes are shifted LSB first into the I/O pin. Data is transferred out LSB first on the I/O pin for a read operation. The address byte is always the first byte entered after CE is driven high. The MSB (W/R) of this byte determines if a read or write takes place. If W/R is 0, one or more read cycles occur. If W/R is 1, one or more write cycles occur. Data transfers can be one byte at a time or in multiplebyte burst mode. After CE is driven high, an address is written to the DS1392/DS1393. After the address, one or more data bytes can be written or read. For a singlebyte transfer, one byte is read or written and then CE is driven low (Figures 13 and 14). For a multiple-byte transfer, however, multiple bytes can be read or written after the address has been written (Figure 15). Each read or write cycle causes the RTC register address to automatically increment. Incrementing continues until the device is disabled. The address wraps to 00h after CE SCLK I/O ADDRESS DATA BYTE BYTE 0 DATA BYTE 1 DATA BYTE N Figure 15. 3-Wire Multiple-Byte Burst Transfer incrementing to 0Fh (during a read) and wraps to 80h after incrementing to 8Fh (during a write). Note, however, that an updated copy of the time is only loaded into the user-accessible copy upon the rising edge of CE. Reading the RTC registers in a continuous loop does not show the time advancing. Chip Information TRANSISTOR COUNT: 11,525 PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND Thermal Information Theta-JA: 180°C/W Theta-JC: 41.9°C/W ____________________________________________________________________ 23 DS1390–DS1394 3-Wire Serial-Data Bus Low-Voltage SPI/3-Wire RTCs with Trickle Charger DS1390–DS1394 Pin Configurations TOP VIEW X1 1 10 VCC X2 2 VBACKUP 3 DS1390/ DS1394 CS 4 GND 5 9 SQW/INT X1 1 X2 2 1 X2 2 VBACKUP 3 CE 4 GND 5 3 7 DOUT CS 4 7 DOUT GND 5 6 DIN 8 SCLK μSOP 10 VCC 9 SQW X1 1 X2 2 10 VCC DS1393 9 SQW/INT VBACKUP 3 7 I/O CE 4 7 I/O 6 INT GND 5 6 RST 8 SCLK μSOP 24 9 RST 8 SCLK 6 DIN DS1392 DS1391 VBACKUP μSOP X1 10 VCC ____________________________________________________________________ μSOP 8 SCLK Low-Voltage SPI/3-Wire RTCs with Trickle Charger CRYSTAL CRYSTAL VCC VCC VCC VCC X1 X2 VCC X1 SQW/INT SCLK SCLK DOUT VCC CS CS CPU X2 CPU DS1390/ DS1394 DOUT VBACKUP DS1391 VBACKUP DIN DIN RST RST GND GND CRYSTAL VCC CRYSTAL VCC VCC VCC X1 X2 VCC X1 CE X2 CE SQW SQW/INT SCLK CPU I/O VCC SCLK CPU DS1392 I/O INT VBACKUP DS1393 VBACKUP RST GND RST GND Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 µSOP — 21-0061 ____________________________________________________________________ 25 DS1390–DS1394 Typical Operating Circuits DS1390–DS1394 Low-Voltage SPI/3-Wire RTCs with Trickle Charger Revision History REVISION NUMBER REVISION DATE 0 7/04 DESCRIPTION Initial release. — Added text to the General Description section to indicate that the bus interface is disabled when the part switches to VBACKUP; replaced Ordering Information table with lead-free packages. 1 Added 0MHz (min) spec for SCLK frequency for SPI, 3-wire AC timing. 1 2 3 1/07 8/08 8/09 PAGES CHANGED Added the “High Impedance” label for DOUT to Figure 1 and added DOUT trace to Figure 2. 3, 5 4 Changed all references of VBAT to VBACKUP. 8, 10 Replaced the Operation section with the Power Control section and added new Table 1. 11, 12 Added the DS1394. All In the Address Map section, added the description on how to avoid misreads of the time registers. 15 Added DS1390U-33/V+ to the Ordering Information table. 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.