DS1868
Dual Digital Potentiometer Chip
www.dalsemi.com
PIN ASSIGNMENT
FEATURES
§ Ultra-lowpower consumption, quiet, pumpless
design
§ Two digitally controlled, 256-position
potentiometers
§ Serial port provides means for setting and
reading both potentiometers
§ Resistors can be connected in series to
provide increased total resistance
§ 20-pin TSSOP, 16-pin SOIC, and 14-pin DIP
packages are available.
§ Resistive elements are temperature
compensated to ±0.3 LSB relative linearity
§ Standard resistance values:
- DS1868-10 ∼ 10 kΩ
- DS1868-50 ∼ 50 kΩ
- DS1868-100 ∼ 100 kΩ
§ +5V or ±3V operation
§ Operating Temperature Range:
- Industrial: -40°C to 85°C
VB
1
20
VCC
DNC
2
19
DNC
H1
3
18
DNC
L1
4
17
SOUT
W1
5
16
W0
RST
6
15
H0
CLK
7
14
L0
DNC
8
13
COUT
DNC
9
12
DNC
GND
10
11
DQ
VB
1
14
VCC
H1
2
13
SOUT
L1
VCC
NC
W1
SOUT
W0 RST
H0
L0 CLK
COUT
DQ GND
3
12
W0
4
11
H0
5
10
L0
6
9
COUT
7
8
DQ
20-Pin TSSOP (173-mil)
VB
NC
H1
L1
W1
RST
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DS1868S 16-Pin SOIC (300-mil)
14-Pin DIP (300-mil)
PIN DESCRIPTION
L0, L1
H0, H1
W0, W1
SOUT
- Low End of Resistor
- High End of Resistor
- Wiper Terminal of Resistor
- Stacked Configuration Output
RST
- Serial Port Reset Input
DQ
- Serial Port Data Input
CLK
- Serial Port Clock Input
COUT
- Cascade Port Output
VCC
- +5 Volt Supply
GND
- Ground Connections
NC
- No Internal Connection
VB
- Substrate Bias Voltage
DNC
- Do Not Connect
*All GND pins must be connected to ground.
DESCRIPTION
The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
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DS1868
wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device is accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same
resolution. For multiple-device, single-processor environments, the DS1868 can be cascaded or daisy
chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1868 is offered in three standard resistance values which include 10, 50, and 100 kohm versions.
The part is available in 16-pin SOIC (300-mil), 14-pin DIP, and 20-pin (173-mil) TSSOP packages.
OPERATION
The DS1868 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper
positions and the stack select bit when the device is powered. A block diagram of the DS1868 is
presented in Figure 1.
Communication and control of the DS1868 is accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST ,
CLK, and DQ.
The RST control signal is used to enable the 3-wire serial port operation of the device. The RST signal is
an active high input and is required to begin any communication to the DS1868. The CLK signal input is
used to provide timing synchronization for data input and output. The DQ signal line is used to transmit
potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the
DS1868.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST
signal input is low. Communication with the DS1868 requires the transition of the RST input from a low
state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to
high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing
diagrams of Figure 9(b),(c).
Data written to the DS1868 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit. This bit will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position
with the MSB for the wiper position occupying bit 9 and the LSB bit 16.
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DS1868
DS1868 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1868, 17 bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed the RST signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a RST transition to the inactive state. On device power-up,
wiper position will be random.
STACKED CONFIGURATION
The potentiometers of the DS1868 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration and allows the user to double the total end-to-end resistance of the part. The
resolution of the combined potentiometers will remain the same as a single potentiometer but with a total
of 512 wiper positions available. Device resolution is defined as RTOT /256 (per potentiometer); where
RTOT equals the total potentiometer resistance.
The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the
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DS1868
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S OUT, will be that of the
potentiometer-1 wiper.
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DS1868
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1868 is the ability to control multiple devices from a single processor. Multiple
DS1868s can be linked or daisy chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1868 a bit will appear at the COUT output after a minimum delay of 50 nanoseconds. The
stack select bit of the DS1868 will always be the first out the part at the beginning of a transaction. The
COUT pin will always have the value of the stack select bit (b0) when RST is inactive.
CASCADING MULTIPLE DEVICES Figure 4
The COUT output of the DS1868 can be used to drive the DQ input of another DS1868. When connecting
multiple devices, the total number of bits transmitted is always 17 times the number of DS1868s in the
daisy chain.
An optional feedback resistor can be placed between the COUT terminal of the last device and the first
DS1868 DQ, input thus allowing the controlling processor to read, as well as, write data, or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2 to 10 kohms.
When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading
device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After
17 bits (or 17 times the number of DS1868s in the daisy chain), the data has shifted completely around
and back to its original position. When RST transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
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DS1868
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between the actual measured output voltage and the
expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute
linearity is given in terms of a minimum increment or expected output when the wiper is moved one
position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 5/256 volts.
The equation for absolute linearity is given as follows:
(1)
ABSOLUTE LINEARITY
AL={VO(actual) - VO(expected)}/MI
Relative linearity is a measure of error between two adjacent wiper position points and is given in terms
of MI by equation (2).
(2)
RELATIVE LINEARITY
RL={VO(n+1) - VO(n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1868 at 25°C.
The specification for absolute linearity of the DS1868 is ±0.75 MI typical. The specification for relative
linearity of the DS1868 is ±0.3 MI typical.
LINEARITY MEASUREMENT CONFIGURATION Figure 5
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DS1868
DS1868 ABSOLUTE AND RELATIVE LINEARITY Figure 6
TYPICAL APPLICATION CONFIGURATIONS
Figures 7 and 8 show two typical application configurations for the DS1868. By connecting the wiper
terminal of the part to a high impedance load, the effects of the wiper resistance is minimized, since the
wiper resistance can vary from 400 to 1000 ohms, depending on wiper voltage. Figure 7 presents the
device connected in a variable gain amplifier. The gain of the circuit on Figure 7 is given by the following
equation:
AV =
+ 256
256 - n
where n = 0 to 255
Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to
attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper
resistance to minimize its effect on circuit gain.
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DS1868
VARIABLE GAIN AMPLIFIER Figure 7
FIXED GAIN ATTENUATOR Figure 8
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DS1868
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground (VB=GND)
Voltage on Any Pin when VB=-3.3V
Operating Temperature
Storage Temperature
Soldering Temperature
*
-1.0V to +7.0V
-3.3V to +4.7V
-40°C to +85°C
-55°C to +125°C
260°C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC
OPERATING CONDITIONS
(-40°C to +85°C; VCC=5.0V ± 10%)
PARAMETER
SYMBOL
MIN
Supply Voltage
VCC
Input Logic 1
Input Logic 0
MAX
UNITS
NOTES
4.5
2.7
5.5
3.3
V
1
15
VIH
2.0
VCC+0.5
V
1, 2
VIL
-0.5
+0.8
V
1, 2
GND
GND
GND
V
1
Resistor Inputs
L, H, W
VB-0.5
VCC+0.5
V
2, 15
Substrate Bias
VB
-3.3
GND
V
1, 15
Ground
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Supply Current
ICC
Input Leakage
ILI
Wiper Resistance
RW
Wiper Current
IW
Logic 1 Output @ 2.4 Volts
IOH
Logic 0 Output @ 0.4 Volts
IOL
ISTBY
Standby Current
ANALOG RESISTOR CHARACTERISTICS
PARAMETER
End-to-End Resistor Tolerance
SYMBOL
TYP
(-40°C to +85°C; VCC=5.0V ± 10%)
MIN
TYP
-1
400
MAX
UNITS
NOTES
400
µA
12
+1
µA
1000
Ω
1
mA
-1
mA
8, 9
4
mA
8, 9
1
µA
14
(-40°C to +85°C; VCC=5.0V ± 10%)
MIN
-20
TYP
MAX
+20
UNITS
%
NOTES
16
Absolute Linearity
±0.75
LSB
4
Relative Linearity
±0.3
LSB
5
Hz
7
-3 dB Cutoff Frequency
FCUTOFF
Noise Figure
11
Temperature Coefficient
750
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ppm/C
DS1868
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DS1868
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
(tA=25°C)
SYMBOL
CIN
TYP
COUT
AC ELECTRICAL CHARACTERISTICS
PARAMETER
CLK Frequency
MIN
MAX
5
UNITS
pF
NOTES
3, 6
7
pF
3, 6
(-40°C to +85°C; VCC=5.0V ± 10%)
SYMBOL
fCLK
MIN
DC
Width of CLK Pulse
tCH
Data Setup Time
TYP
MAX
10
UNITS
MHz
NOTES
10
50
ns
10
tDC
30
ns
10
Data Hold Time
tCDH
10
ns
10
Propagation Delay Time Low to High Level
Clock to Output
tPLH
50
ns
10, 13
Propagation Delay Time High to Low Level
tPLH
50
ns
10, 13
RST
High to Clock Input High
tCC
50
ns
10
RST
Low from Clock Input High
tHLT
50
ns
10
RST
Inactive
tRLT
125
ns
10
Clock Low to Data Valid on a Read
tCDD
30
ns
10
CLK Rise Time, CLK Fall Time
tCR
50
ns
10
NOTES:
1.
2.
3.
4.
All voltages are referenced to ground.
Resistor inputs cannot exceed VB - 0.5V in the negative direction.
Capacitance values apply at 25°C.
Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits ±1.6 LSB.
5. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
6. Typical values are for tA = 25°C and nominal supply voltage.
7. -3 dB cutoff frequency characteristics for the DS1868 depend on potentiometer total resistance:
DS1868-010; 1 MHz, DS1868-050; 200 kHz; and DS1868-100; 80 kHz.
8. Cout is active regardless of the state of RST .
9. VREF = 1.5 volts.
10. See Figure 9(a), (b), and (c).
11. Noise < -120 dB/ Hz . Reference 1 volt (thermal).
12. Supply current is dependent on clock rate (see Figure 11).
13. See Figure 10.
14. Standby currents apply when RST , LLIC, DQ are in the low-state.
15. When biasing the substrate minimum VB = -3.0V ± 10% and maximum VCC = 3.0V ± 10%.
16. Valid at 25°C only.
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DS1868
TIMING DIAGRAMS Figure 9
(a) 3-Wire Serial Interface General Overview
(b) Start of Communication Transaction
(c) End of Communication Transaction
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DS1868
DIGITAL OUTPUT LOAD SCHEMATIC Figure 10
TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure 11
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DS1868
DS1868 20-PIN TSSOP
DIM
MIN
MAX
A MM
-
1.10
A1 MM
0.05
-
A2 MM
0.75
1.05
C MM
0.09
0.18
L MM
0.50
0.70
e1 MM
0.65 BSC
B MM
0.18
0.30
D MM
6.40
6.90
E MM
4.40 NOM
G MM
0.25 REF
H MM
6.25
6.55
phi
0°
8°
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