DS2423 4kbit 1-Wire RAM with Counter www.maxim-ic.com FEATURES § § § § § § § § § § § 4096 bits of SRAM Four 32-bit, read-only counters Active-low external trigger inputs for two of the counters with on-chip debouncing compatible with reed and Wiegand switches Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike Memory partitioned into 16 256-bit pages in for packetizing data 256-bit scratchpad with strict read/write protocols ensures integrity of data transfer On-chip 16-bit CRC generator for safeguarding data transfers Built-in multidrop controller ensures compatibility with other MicroLAN products Directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbits per second Overdrive mode boosts communication speed to 142kbits per second 8-bit family code specifies device communication requirements to reader § § § Presence detector acknowledges when reader first applies voltage Compact, low cost 6-pin TSOC surface mount package Reads, writes and counts over a wide voltage range of 2.8V to 5.5V from -40°C to +85°C PIN ASSIGNMENT TSOC PACKAGE 1 2 3 6 5 4 TOP VIEW 3.7mm x 4.0mm x 1.5mm SIDE VIEW PIN DESCRIPTION Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Ground Data Vbat NC Input channel B Input channel A ORDERING INFORMATION DS2423P DS2423P/T&R DS2423X 6-pin TSOC package Tape & Reel Version of DS2423P Chip Scale Pkg., Tape & Reel DESCRIPTION The DS2423 1-Wire® RAM with Counters is a fully static, read/write memory for battery operation in a low-cost, six-lead TSOC, surface-mount package. The memory is organized as 16 pages of 256 bits each. In addition, the device has four counters, two of them with external trigger inputs called A and B. Each of the counters is associated with a memory page. A counter without external trigger input increments each time data is written to the page it is associated with (write cycle counter). The counters triggered by inputs A and B, respectively, increment with every low-going pulse on their input. All counters are readonly. They are automatically cleared to 0 when the battery is connected. 1-Wire is a registered trademark of Dallas Semiconductor. 1 of 25 060603 DS2423 The battery-backed memory offers a simple solution to storing and retrieving information pertaining to the equipment where the DS2423 is installed and its frequency of use. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it may be read back for verification. A copy scratchpad command will then transfer the data to memory. This process ensures data integrity when modifying the memory. A 64-bit registration number is factory lasered into each DS2423 to provide a guaranteed unique identity which allows for absolute traceability and acts as node address if multiple DS2423 are connected in parallel to form a local network. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2423 1-Wire RAM with Counters can store encrypted data. The unique registration number and the page write cycle counter(s) prevent unauthorized manipulation of data stored in a page with a write cycle counter associated. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2423. The DS2423 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit SRAM, and 4) four 32-bit read-only counters. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. Each of these counters is associated with one of the 256-bit memory pages. The four counters of the DS2423 are associated with pages 12 to 15. The contents of the counter is read together with the memory data using a special command. The bus master must first provide one of the six ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 9. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the five memory function commands. The protocol for these memory function commands is described in Figure 7. All data is read and written least significant bit first. PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved, and 2) if the battery is exhausted for any reason, the ROM may still be read normally. 64-BIT LASERED ROM Each DS2423 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton® Standards. The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s. iButton is a registered trademark of Dallas Semiconductor. 2 of 25 DS2423 BLOCK DIAGRAM Figure 1 ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS2423 employs three address registers called TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore, the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S register, called PF or “partial byte flag,” is set if the number of data bits sent by the master is not an integer multiple of 8. Bit 6 has no function; it always reads 0. Note that the lowest 5 bits of the target address also determine the address within the scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target address (TA1) for a Write command is 03CH for example, then the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only 4 bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or several contiguous bytes somewhere within a page. The ending offset together with the Partial Flag support the master checking the data integrity after a Write command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. 3 of 25 DS2423 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 DS2423 DS2423 SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) 64-BIT LASERED ROM Figure 3 MSB LSB 8-BIT CRC CODE MSB 8-BIT FAMILY CODE (1DH = DS2423) 48-BIT SERIAL NUMBER LSB MSB LSB 1-WIRE CRC GENERATOR Figure 4 4 of 25 MSB LSB DS2423 WRITING WITH VERIFICATION To write data to the DS2423, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16 of the command, address and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the communication was successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to verify data integrity. As preamble to the scratchpad data, the DS2423 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the device. If everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After the master has verified the data, it has to send the Copy Scratchpad command. This command must be followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS2423 has received these bytes correctly, it will copy the data to the requested location beginning at the target address. MEMORY FUNCTION COMMANDS The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory. An example follows the flowchart. The communication between master and DS2423 takes place either at regular speed (default, OD = 0) or at Overdrive speed (OD = 1). If not explicitly set into the Overdrive mode the DS2423 assumes regular speed. Write Scratchpad Command [0FH] After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be ignored and the partial byte flag PF will be set. When executing the Write Scratchpad command the CRC generator inside the DS2423 (see Figure 12) calculates a CRC over the entire data stream, starting at the command code and ending at the last data byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive the CRC generated by the DS2423. The memory address range of the DS2423 is 0000H to 01FFH. If the bus master sends a target address higher than this, the internal circuitry of the chip will set seven most significant address bits to 0 as they are shifted into the internal address register. The Read Scratchpad command will reveal the target address as it will be used by the DS2423. The master will identify such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent Copy Scratchpad command will not work since the most significant bits of the target address the master sends will not match the value the DS2423 expects. 5 of 25 DS2423 Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ending offset/data status byte (E/S) followed by the scratchpad data beginning at the byte offset (T4: T0). The master may read data until the end of the scratchpad after which the data read will be all logic 1s. Copy Scratchpad [5AH] This command is used to copy data from the scratchpad to memory. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern which can be obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin. A pattern of alternating 1s and 0s will be transmitted after the data has been copied until a Reset Pulse is issued by the master. Any attempt to reset the part will be ignored while the copy is in progress. Copy typically takes 30µs. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes may be copied to memory with this command. The AA flag will be cleared only by executing a Write Scratchpad command. 6 of 25 DS2423 DS2423 MEMORY MAP Figure 5 ADDRESS REGISTERS Figure 6 7 of 25 DS2423 Read Memory [F0H] The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS2423 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See the Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure.) Read Memory + Counter [A5H] The Read Memory + Counter command is used to read memory data together with the write cycle counter or externally triggered counter associated with the addressed page of data memory. The additional information is transmitted by the DS2423 as the end of a memory page is encountered. Following the current value of the counter the DS2423 transmits 32 0-bits and a 16-bit CRC generated by the DS2423. After having sent the command code of the Read Memory + Counter command, the bus master sends a two-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. With the subsequent read data time slots the master receives data from the DS2423 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 80 additional read data time slots and receive the contents of the 32-bit counter associated with the addressed page, 32 0-bits and a 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next page followed by the contents of the counter associated with the page, 0-bits and CRC for that page. This sequence will continue until the final page and its accompanying data is read by the bus master. When applying the Read Memory + Counter command to a page that does not have a counter associated, the master will read FFFFFFFFH instead of a valid count. With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes, the contents of the data memory, the counter and the 0-bits. Subsequent passes through the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page, its associated counter and 0-bits. After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2423 until a Reset Pulse is issued. The Read Memory + Counter command sequence can be ended at any point by issuing a Reset Pulse. 8 of 25 DS2423 MEMORY FUNCTION FLOW CHART Figure 7 1) Master TX Memory Function Command 0FH Write Scratchpad From ROM Functions Flow Chart (Figure 9) Y 1) Master TX TA2 (T15:T8) Master RX Ending Offset with Data Status (E/S) Master RX Data Byte from Scratchpad Offset 2) 2) Y DS2423 Increments Scratchpad Offset Scratchpad Offset = 11111b? Partial Byte Written? Y Y N N Scratchpad Offset = 11111b? Y Master RX "1"s N 2) 1) Y Master TX Reset? N Master TX Reset? 1) DS2423 sets Scratchpad Offset = (T4:T0) 1) DS2423 sets (E4:E0) = Scratchpad Offset Y 1) Master RX TA2 (T15:T8) 1) Master TX Data Byte to Scratchpad Offset N 1) Master RX TA1 (T7:T0) DS2423 sets Scratchpad Offset = (T4:T0) and Clears (PF, AA) DS2423 Increments Scratchpad Offset N Y Master TX TA1 (T7:T0) Master TX Reset? To Figure 7 2nd Part AAH Read Scratchpad N 1) PF = 1 N Master RX CRC16 of Command, Address, Data Y Master TX Reset? 1) 2) N Master RX "1"s 1) 1) To be transmitted or received at Overdrive speed if OD = 1. 2) Reset Pulse to be transmitted at Overdrive speed if OD = 1. Reset Pulse to be transmitted at normal speed if OD = 0 or if the DS2423 is to be reset from Overdrive speed to regular speed. 9 of 25 To ROM Functions Flow Chart (Figure 9) From Figure 7 2nd Part DS2423 MEMORY FUNCTION FLOW CHART Figure 7 cont’d From Figure 7 1st Part 55H Copy Scratchpad To Figure 7 3rd Part F0H Read Memory N Y N Y 1) Master TX TA1 (T7:T0) Master TX TA2 (T15:T8) 1) Master TX TA1 (T7:T0) 1) Master TX TA1 (T7:T0) 1) Master TX E/S Byte 1) DS2423 sets Memory Address = (T15:T0) Authorization Code Match? N Master RX Data Byte from Memory Address DS2423 Increments Address Counter Y AA = 1 DS2423 Copies Scratchpad Data to Memory Y 1) 2) Master TX Reset? N Master RX "1"s N Master RX "1"s 1) N 1) Copying Finished End of Memory? Y Master TX Reset? Y DS2423 TX "0" 1) 2) Master TX Reset? N N 1) Master RX "0"s Y Y 1) DS2423 TX "1" N Master TX Reset? 2) Y To Figure 7 1st Part 1) To be transmitted or received at Overdrive speed if OD = 1. 2) Reset Pulse to be transmitted at Overdrive speed if OD = 1. Reset Pulse to be transmitted at normal speed if OD = 0 or if the DS2423 is to be reset from Overdrive speed to regular speed. 10 of 25 From Figure 7 3rd Part DS2423 MEMORY FUNCTION FLOW CHART Figure 7 cont’d From Figure 7 2nd Part A5H Read Memory + Counter N Y Master TX TA1 (T7:T0) 1) Master TX TA2 (T15:T8) 1) DS2423 Sets Memory Address = (T15:T0) 1) Master RX Data From Memory Y Master TX Reset? 2) DS2423 Increments Address Counter N End of Page? N Y Master RX Counter Value of Memory Page Master RX 32 Zero Bits 2) 1) Master TX Reset? N 1) Master RX CRC 16 of Command, Address, Data, Counter, Zero Bits (1st Pass) CRC 16 of Data, Counter, Zero Bits (Subsequent Passes) Master TX Reset 2) N Y 1) CRC Correct? Y N End of Memory? Y Master RX "1"s 2) Master TX Reset? 1) N Y To Figure 7 2nd Part 1) To be transmitted or received at Overdrive speed if OD = 1. 2) Reset Pulse to be transmitted at Overdrive speed if OD = 1. Reset Pulse to be transmitted at normal speed if OD = 0 or if the DS2423 is to be reset from Overdrive speed to regular speed. 11 of 25 DS2423 MEMORY FUNCTION EXAMPLE Example: Write two data bytes to memory location 0026 and 0027. Read entire memory. MASTER MODE TX RX TX TX TX TX TX TX RX TX TX RX RX RX RX TX RX TX TX TX TX TX TX RX TX TX TX TX RX TX RX DATA (LSB FIRST) Reset Presence CCh 0Fh 26h 00h <2 data bytes> Reset Presence CCh AAh 26h 00h 07h <2 data bytes> Reset Presence CCh 5Ah 26h 00h 07h Reset Presence CCh F0h 00h 00h <512 bytes> Reset Presence COMMENTS Reset pulse (480-960 µs) Presence pulse Issue “skip ROM” command Issue “write scratchpad” command TA1, beginning offset=26h TA2, address=0026h Write 2 bytes of data to scratchpad Reset pulse Presence pulse Issue “skip ROM” command Issue “read scratchpad” command Read TA1, beginning offset=26h Read TA2, address=0026h Read E/S, ending offset=7h, flags=0h Read scratchpad data and verify Reset pulse Presence pulse Issue “skip ROM” command Issue “copy scratchpad” command TA1 TA2 AUTHORIZATION CODE E/S Reset pulse Presence pulse Issue “skip ROM” command Issue “read memory” command TA1, beginning offset=0 TA2, address=0000h Read entire memory Reset pulse Presence pulse, done 12 of 25 DS2423 MEMORY FUNCTION EXAMPLE Read page 14 and counts of Input A. Rewrite page 14 with 32 bytes. Read Memory + Counter, Write Scratchpad, Copy Scratchpad. MASTER MODE TX RX TX TX TX TX RX RX RX RX TX RX TX TX TX TX TX RX TX RX TX TX TX TX TX RX TX RX DATA (LSB FIRST) Reset Presence CCh A5h C0h 01h <32 data bytes> <4 data bytes> <4 data bytes> <2 data bytes> Reset Presence CCh 0Fh C0h 01h <32 data bytes> <2 data bytes> Reset Presence CCh 5Ah C0h 01h 1Fh <1 data byte> Reset Presence COMMENTS Reset pulse (480-960 µs) Presence pulse Issue “skip ROM” command Issue “read memory + counter” command TA1, beginning offset=C0h TA2, address=01C0h Read 32 bytes of data Read Counts of Input A Read 32 Zero Bits Read (inverted) CRC16 Reset pulse Presence pulse Issue “skip ROM” command Issue “write scratchpad” command TA1, beginning offset=C0h TA2, address=01C0h Read 32 bytes of data to scratchpad Read (inverted) CRC16 Reset pulse Presence pulse Issue “skip ROM” command Issue “copy scratchpad” command TA1 TA2 AUTHORIZATION CODE E/S Read Copy Scratchpad response Reset pulse Presence pulse, done 13 of 25 DS2423 HARDWARE CONFIGURATION Figure 8 DS2423 RPU Note: Depending on the 1-Wire communication speed and the bus load characteristics, the optimal pullup resistor (RPU) value will be in the 1.5kW to 5kW range. 1-WIRE BUS SYSTEM The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the DS2423 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have opendrain or 3-state outputs. The 1-Wire port of the DS2423 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3kbits per second. The speed can be boosted to 142kbits per second by activating the Overdrive mode. The 1-Wire bus requires a pullup resistor of approximately 5kΩ. The 1-Wire bus requires a pullup resistor range of 1.5kW to 5kW, depending on the bus load characteristics. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (Overdrive speed) or more than 120µs (regular speed), one or more devices on the bus may be reset. TRANSACTION SEQUENCE The protocol for accessing the DS2423 via the 1-Wire port is as follows: § Initialization § ROM Function Command § Memory Function Command § Transaction/Data 14 of 25 DS2423 INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2423 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the six ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 9): Read ROM [33H] This command allows the bus master to read the DS2423’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS2423 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number will result in a mismatch of the CRC. Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2423 on a multidrop bus. Only the DS2423 that exactly matches the 64-bit ROM sequence will respond to the following memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the bus. Skip ROM [CCH] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. Overdrive Skip ROM [3CH] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive Skip ROM sets the DS2423 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a Reset Pulse of minimum 480µs duration resets all devices on the bus to regular speed (OD = 0). 15 of 25 DS2423 When issued on a multidrop bus this command will set all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a Reset Pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This will speed up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result). Overdrive Match ROM [69H] The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive speed, allows the bus master to address a specific DS2423 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS2423 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a Reset Pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 16 of 25 DS2423 ROM FUNCTIONS FLOW CHART Figure 9 (First Part) Master TX Reset Pulse From Memory Functions Flow Chart (Figure 7) N Short Reset Pulse? OD = 0 Y 33H Read ROM? N Y DS2423 TX Family Code 1 Byte DS2423 TX Presence Pulse 2) Master TX ROM Function Command 1) 55H Match ROM? F0H Search ROM? N Y DS2423 TX Bit 0 Bit 0 Match? 1) N N 1) Master TX Bit 0 1) Bit 0 Match? Y 1) Master TX Bit 1 Bit 1 Match? 1) N N DS2423 TX Bit 1 1) DS2423 TX Bit 1 1) Master TX Bit 1 1) Bit 1 Match? Y DS2423 TX CRC Byte Y 1) DS2423 TX Bit 63 1) Master TX Bit 63 1) DS2423 TX Bit 63 1) Master TX Bit 63 Bit 63 Match? N N 2) To be transmitted or received at Overdrive speed if OD = 1. The Presence Pulse will be short if OD = 1. 1) Bit 63 Match? Y 1) To Figure 9 2nd Part 1) DS2423 TX Bit 0 Y DS2423 TX Serial Number 6 Bytes N Y 1) Master TX Bit 0 From Figure 9 2nd Part Y To Memory Functions Flow Chart (Figure 7) 17 of 25 To Figure 9 2nd Part From Figure 9 2nd Part DS2423 ROM FUNCTIONS FLOW CHART Figure 9 cont’d To Figure 9 1st Part From Figure 9 1st Part N CCH Skip ROM? 3CH Overdrive Skip ROM? Y N 69H Overdrive Match? Y OD = 1 N Y OD = 1 Master TX Bit 0 Bit 0 Match? 3) N Y Master TX Bit 1 3) Y Master TX Reset Pulse? Bit 1 Match? N Y Master TX Bit 63 Bit 63 Match? From Figure 9 1st Part To Figure 9 1st Part Y 3) Always to be transmitted at Overdrive speed. 18 of 25 N 3) N DS2423 1-WIRE SIGNALING The DS2423 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. The bus master initiates all these signals except Presence Pulse. The DS2423 can communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the Overdrive mode, the DS2423 will communicate at regular speed. While in Overdrive mode the fast timing applies to all waveforms. The initialization sequence required to begin any communication with the DS2423 is shown in Figure 10. A Reset Pulse followed by a Presence Pulse indicates the DS2423 is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (TX) a Reset Pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at Overdrive speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After detecting the rising edge on the data pin, the DS2423 waits (tPDH, 15-60µs at regular speed, 2-6µs at Overdrive speed) and then transmits the Presence Pulse (tPDL, 60-240µs at regular speed, 8-24µs at Overdrive speed). A Reset Pulse of 480µs or longer will exit the Overdrive mode returning the device to regular speed. If the DS2423 is in Overdrive mode and the Reset Pulse is no longer than 80µs the device will remain in Overdrive mode. Read/Write Time Slots The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS2423 to the master by triggering a delay circuit in the DS2423. During write time slots, the delay circuit determines when the DS2423 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the DS2423 will hold the data line low overriding the 1 generated by the master. If the data bit is a “1”, the device will leave the read data time slot unchanged. INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10 DS2423 19 of 25 DS2423 READ/WRITE TIMING DIAGRAM Figure 11 Write-One Time Slot VPUP TLOW1 VPUPMIN VTH VLOW1 0V tREC tSLOT RESISTOR MASTER DS2423 Write-Zero Time Slot tSLOT VPUP VPUPMIN VIHMIN VILMAX 0V tREC tL0W0 RESISTOR MASTER 20 of 25 DS2423 DS2423 Read-Data Time Slot tRDV tSU VPUP VPUPMIN VIHMIN Master Sampling Window VILMAX 0V tLOWR tRELEASE tREC tSLOT RESISTOR MASTER DS2423 CRC GENERATION With the DS2423 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2423 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non-inverted) form when reading the ROM of the DS2423. It is computed at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x16 + x15 + x2 + 1. This CRC is used for error detection when reading Data Memory using the Read Memory + Counter command and for fast verification of a data transfer when writing to the scratchpad. It is the same type of CRC as is used with NV RAM based iButtons for error detection within the iButton Extended File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned or sent in the complemented (inverted) form. A CRC-generator inside the DS2423 chip (Figure 12) will calculate a new 16-bit CRC as shown in the command flow chart of Figure 7. The bus master compares the CRC value read from the device to the one it calculates from the data and decides whether to continue with an operation or re-read the portion of the data with the CRC error. With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes, data bytes, value of the counter associated with the page and zero bits. Subsequent passes through the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the data bytes, the value of the counter and the zero bits. With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS2423 will transmit this CRC only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. The data may start at any location within the scratchpad. For more details on generating CRC values including example implementations in both hardware and software, see the Book of DS19xx iButton Standards. 21 of 25 DS2423 CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 12 22 of 25 DS2423 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * -0.5V to +7.0V -40°C to +85°C -55°C to +125°C See J-STD-020A Specifications This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS (VPUP = 2.8V to 6.0V; VBAT = 2.8 to 5.5V;-40°C to +85°C) PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Output Logic High Input Load Current Standby Current I/O Operate Charge SYMBOL VIH VIL VOL VOH IL IBATS QBATO MIN 2.2 -0.3 TYP VPUP 5 MAX +0.8 0.4 6.0 200 200 UNITS V V V V µA nA nC CAPACITANCE PARAMETER I/O (1-Wire) NOTES 1, 8 1, 9 1 1, 2 3 12, 16 (tA = 25°C) SYMBOL CIN/OUT MIN TYP 100 MAX 800 UNITS pF NOTES 6, 16 COUNTER INPUT CHARACTERISTICS (VPUP = 2.8V to 6.0V; VBAT = 2.8 to 5.5V;-40°C to +85°C) PARAMETER SYMBOL MIN Trip Point VTRIP Logic 1 VINH VTRIP Logic 0 Internal Pullup Resistor Debounce Time Pulse Width (Active Low) VINL RPI TDEB TPW -0.3 23 of 25 170 1 TYP ½ VBAT MAX NOTES V VBAT +0.3 VTRIP 28 290 UNITS 460 V 1, 10 V MV µs µs 1 11, 16 13 16 DS2423 AC CHARACTERISTICS REGULAR SPEED (VPUP = 2.8V to 6.0V; VBAT = 2.8 to 5.5V;-40°C to +85°C) PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 60 1 60 1 0 TYP 15 15 1 480 480 15 60 MAX 120 15 120 15 45 1 960 60 240 UNITS µs µs µs µs µs µs µs µs µs µs µs µs NOTES 15 15 14, 16 5 4 7 AC CHARACTERISTICS OVERDRIVE SPEED (VPUP = 2.8V to 6.0V; VBAT = 2.8 to 5.5V;-40°C to +85°C) PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL 24 of 25 MIN 6 1 6 1 0 1 48 48 2 8 TYP 2 1.5 MAX 16 2 16 2 4 1 80 6 24 UNITS µs µs µs µs µs µs µs µs µs µs µs µs NOTES 15 15 14, 16 5 4 DS2423 NOTES: 1) All voltages are referenced to ground. 2) VPUP = external pullup voltage. 3) Input load is to ground. 4) An additional reset or communication sequence cannot begin until the reset high time has expired. 5) Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1µs of this falling edge. 6) Capacitance on the data pin could be 800pF when power is first applied. If a 5kΩ resistor is used to pull up the data line to VPUP, 5µs after power has been applied the parasite capacitance will not affect normal communications. 7) The reset low time (tRSTL) should be restricted to a maximum of 960µs, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 8) VIH is a function of the external pullup resistor and VPUP. 9) Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always guarantee a Presence Pulse. 10) The counter inputs are designed for interfacing to mechanical switches and piezo sensors. If interfacing to digital circuits, one should use an open drain driver. 11) A lower impedance pullup, e. g., for reed switches, can be achieved by connecting an external resistor from the counter input to VBAT. 12) Read and write scratchpad (all 32 bytes) at VBAT of 3.0 V. 13) Each low-going edge on a counter input resets the channel’s debounce timer. The debounce time starts as the input voltage rises beyond the trip point. In order for the next pulse to be counted the debounce time must have expired. 14) The optimal sampling point for the master is as close as possible to the end time of the tRDV period without exceeding tRDV. For the case of a Read-One Time slot, this maximizes the amount of time for the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read will occur before the fastest 1-Wire device(s) releases the line. 15) The duration of the low pulse sent by the master should be a minimum of 1µs with a maximum value as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1Wire device samples in the case of a Write-One Time or before the master samples in the case of a Read-One Time. 16) Guaranteed by design; not production tested. 25 of 25