Abridged Data Sheet
DS28CN01
1Kbit I²C/SMBus EEPROM
with SHA-1 Engine
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS28CN01 combines 1024 bits of EEPROM
with challenge-and-response authentication security
implemented
with
the
Federal
Information
Publications (FIPS) 180-1/180-2 and ISO/IEC 101183 Secure Hash Algorithm (SHA-1). The memory is
organized as four pages of 32 bytes each. Data
copy-protection and EPROM emulation features are
supported for each memory page. Each DS28CN01
has a guaranteed unique factory-programmed 64-bit
registration number. Communication with the
DS28CN01 is accomplished through an industry
standard I²C- and SMBus™-compatible interface.
The SMBus timeout feature resets the device’s
interface if a bus-timeout fault condition is detected.
APPLICATIONS
Printed Circuit Board (PCB) Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License Management
Network Node Identification
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
ORDERING INFORMATION
TYPICAL OPERATING CIRCUIT
VCC
RP
VCC
RP
To additional
devices
SDA
SCL
µC
PART
DS28CN01U+
-40°C to +85°C
TEMP RANGE
DS28CN01U+T
-40°C to +85°C
PIN-PACKAGE
8 µSOP
8 µSOP
Tape-and-Reel
+ Denotes a lead-free package.
Request full data sheet at:
www.maxim-ic.com/fullds/DS28CN01
VCC
DS28CN01
GND
1024 Bits of EEPROM Memory Partitioned
Into Four Pages of 256 Bits
Dedicated Hardware-Accelerated SHA Engine
for Generating SHA-1 MACs
EEPROM Memory Pages can be Individually
Copy-Protected or Put Into an EPROM Mode
(Program from 1 to 0 Only)
Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting a 160-Bit MAC as Authorization
Unique, Factory-Programmed, and Tested
64-Bit Registration Number Assures Absolute
Traceability Because No Two Parts are Alike
Endurance 200k Cycles at +25°C
Serial Interface User Programmable for I²C
Bus and SMBus Compatibility
Supports 100kHz and 400kHz I²C
Communication Speeds
5.5V Tolerant Interface Pins
Operating Range: 1.62V to 5.5V,
-40°C to +85°C
8-Pin µSOP Package
SDA
SCL
PIN CONFIGURATION
AD1
AD0 GND
Registers, Modes, and Commands are capitalized for
clarity.
SMBus is a trademark of Intel Corp.
AD0 1
8
VCC
AD1 2
7
NC
NC 3
6
SCL
GND 4
5
SDA
µSOP
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REV: 061907
Abridged Data Sheet
DS28CN01
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Maximum Current Any Pin
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +6V
±20mA
-40°C to +85°C
+150°C
-55°C to +125°C
See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (see Note 1)
(TA = -40°C to +85°C)
PARAMETER
SYMBOL
Supply Voltage
Standby Current
VCC
ICCS
Operating Current
ICCA
Power-Up Wait Time
tPOIP
CONDITIONS
MIN
1.62
Bus idle, VCC = 5.5V
Bus active at 400kHz,
VCC = 5.5V
(Note 2)
TYP
MAX
UNITS
5.50
5.5
V
µA
500
µA
5
µs
EEPROM
Programming Time
tPROG
Programming Current
IPROG
Endurance (Notes 3, 4, 5)
NCY
Data Retention (Notes 6, 7, 8)
tDR
VCC ≥ 2.0V
VCC < 2.0V
VCC = 5.5V
At +25°C
At +85°C
At +85°C
10
45
1.2
200k
50k
40
ms
mA
—
years
SHA-1 Engine
SHA Computation Time
tCSHA
SHA Computation Current
ILCSHA
See full version of data
sheet
See full version of data
sheet
ms
mA
SCL, SDA, AD1, AD0 Pins (Note 9) (See Figure 3)
LOW Level Input Voltage
HIGH Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs (Note 2)
LOW Level Output Voltage at
4mA Sink Current, Open Drain
Output Fall Time from VIHmin to
VILmax with a Bus Capacitance
from 10pF to 400pF
(Notes 2, 10)
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current with an Input
Voltage Between 0.1VCC and
0.9VCCmax
VIL
VIH
VHYS
VOL
VCC ≥ 2.0V
-0.3
VCC < 2.0V
-0.3
VCC ≥ 2.0V
0.7 ×
VCC
0.8 ×
VCC
0.05 ×
VCC
0.1 ×
VCC
VCC < 2.0V
VCC ≥ 2.0V
VCC < 2.0V
VCC ≥ 2.0V
VCC < 2.0V
VCC ≥ 2.0V
tOF
VCC < 2.0V
tSP
(Note 2)
Ii
(Note 11)
2 of 9
0.3 × VCC
0.25 ×
VCC
VCCmax
+0.3V
VCCmax
+0.3V
-10
V
V
0.4
0.2 × VCC
20 +
0.1CB
20 +
0.1CB
V
V
250
300
ns
50
ns
+10
µA
Abridged Data Sheet
PARAMETER
SYMBOL
Input Capacitance
SCL Clock Frequency
Bus Timeout
Hold-Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
CI
fSCL
CONDITIONS
DS28CN01
MIN
tTIMEOUT
(Note 2)
(Note 12)
(Note 12)
25
tHD:STA
(Note 13)
0.6
1.3
1.5
1.9
0.6
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
tHIGH
VCC ≥ 2.7V
VCC ≥ 2.0V
VCC < 2.0V
(Note 13)
tSU:STA
(Note 13)
0.6
Data Hold Time
(Notes 14, 15)
tHD:DAT
VCC ≥ 2.7V
VCC ≥ 2.0V
VCC < 2.0V
(Notes 2, 13, 16)
(Note 13)
0.3
0.3
0.3
100
0.6
tBUF
(Note 13)
1.3
CB
(Notes 2, 13)
LOW Period of the SCL Clock
(Note 13)
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
tLOW
tSU:DAT
tSU:STO
TYP
MAX
UNITS
10
400
75
pF
kHz
ms
µs
µs
µs
µs
0.9
1.1
1.5
µs
ns
µs
µs
400
pF
Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Guaranteed by design, characterization and/or simulation only, and not production tested.
This specification is valid for each 8-byte memory row.
Write-cycle endurance is degraded as TA increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as TA increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
All values are referred to VIHmin and VILmax levels.
CB = total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall-times according to I²C-Bus
Specification v2.1 are allowed.
The DS28CN01 does not obstruct the SDA and SCL lines if VCC is switched off.
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 and SCL stays at the same logic level
or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition.
System requirement.
The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by design,
characterization and/or simulation only, and not production tested.
A Fast-Mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement tSU:DAT ≥ 250ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU:DAT = 1000 + 250 = 1250ns
(according to the Standard-mode I²C-bus specification) before the SCL line is released.
3 of 9
Abridged Data Sheet
DS28CN01
PIN DESCRIPTION
PIN
NAME
1
AD0
2
AD1
3, 7
4
5
6
8
N.C.
GND
SDA
SCL
VCC
FUNCTION
Device Address Input Pin to Select the Slave Address. Sets slave address bits A1:A0;
must be tied to either GND, SDA, SCL, or VCC.
Device Address Input Pin to Select the Slave Address. Sets slave address bits A3:A2;
must be tied to either GND, SDA, SCL, or VCC.
No Connection
Ground Supply
I²C/SMBus Bidirectional Serial Data Line. Must be tied to VCC through a pullup resistor.
I²C/SMBus Serial Clock Input. Must be tied to VCC through a pullup resistor.
Power-Supply Input
OVERVIEW
The DS28CN01 features a serial I²C/SMBus interface, 1Kbits of SHA-1 secure EEPROM, a register page, and a
unique registration number, as shown in the Block Diagram. The device communicates with a host processor
through its I²C interface in Standard-mode or in Fast-mode. The user can switch the interface from I²C Bus to
SMBus Mode. Two 4-level address pins allow 16 DS28CN01s to reside on the same bus segment.
DS28CN01 BLOCK DIAGRAM
MAC Output
Buffer
VCC
ADx
SCL
SDA
I²C/SMBus
Function
Control
64-bit Unique
Number
Memory and
SHA-1 Engine
Control
MAC
Comparator
8-Byte
Write Buffer
SHA-1
Engine
Secret
Memory
Register
Page
User EEPROM
4 Pages
of 32 Bytes
4 of 9
Abridged Data Sheet
DS28CN01
DEVICE OPERATION
Read and write access to the DS28CN01 is controlled through the I²C/SMBus serial interface. Since the
DS28CN01 has memory areas and registers of different characteristics there are several special cases to consider.
See the Read and Write section for details.
Serial Communication Interface
General Characteristics
The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the
Standard-mode, up to 400kbps in the Fast-mode. The DS28CN01 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” The DS28CN01 is a slave device.
Slave Address/Direction Byte
To be individually accessed, each device must have a slave address that does not conflict with other devices on
the bus. The slave address to which the DS28CN01 responds is shown in Figure 1. The slave address is part of
the slave-address/direction byte. The upper 3 bits of the slave address of the DS28CN01 are set to 101b. The AD0
pin controls address A0 and A1; AD1 controls A2 and A3. AD0 and AD1 can be tied to GND, VCC, SCL, or SDA.
Table 1 shows the translation of these four pin states to binary addresses. To be selected the device must be
addressed with A0 to A3 matching the binary address of the respective pins.
Figure 1. DS28CN01 Slave Address
7-Bit Slave Address
A6
A5
A4
1
0
1
Most Significant Bit
A3
A2
AD1
A1
A0
AD0
4-Level Pin States
See Text
R/W
Determines
Read or Write
Table 1. Pin State to Binary Translation
AD1
A3
A2
AD0
A1
A0
GND
0
0
GND
0
0
VCC
0
1
VCC
0
1
SCL
1
0
SCL
1
0
SDA
1
1
SDA
1
1
The last bit of the slave-address/direction byte (R/W) defines the data direction. When set to a 0, subsequent data
flows from master-to-slave (Write-Access Mode); when set to a 1, data flows from slave-to-master (Read-Access
Mode).
5 of 9
Abridged Data Sheet
DS28CN01
I²C/SMBus Protocol
Data transfers can be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls
the bus access, generates the START and STOP conditions, and determines the number of bytes transferred on
the data line (SDA) between START and STOP. Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line while
SCL is high are interpreted as a START or a STOP. The protocol is illustrated in Figure 2. See Figure 3 for detailed
timing references .
Figure 2. I²C/SMBus Protocol Overview
MS-bit
R/W
ACK
bit
ACK
bit
SDA
Slave Address
Acknowledgment
from Receiver
SCL
1
Idle
START
Condition
2
6
7
8
9
ACK
Repeated if more bytes
are transferred
1
2
8
9
ACK
STOP Condition
Repeated START
Condition
Bus Idle or Not Busy
Both SDA and SCL are inactive, i.e., in their logic HIGH states.
START Condition
To initiate communication with a slave the master must generate a START condition. A START condition is defined
as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition
To end communication with a slave the master must generate a STOP condition. A STOP condition is defined as a
change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition
Repeated starts are commonly used for read accesses after having specified a memory address to read from in a
preceding write access. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without a preceding STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 3).
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 3) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
6 of 9
Abridged Data Sheet
DS28CN01
Acknowledged by Slave
A slave device, when addressed, is usually obliged to generate an acknowledge after the receipt of each byte. The
master must generate the clock pulse for each acknowledge bit. A slave that acknowledges must pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock
pulse. Setup and hold times tSU:DAT and tHD:DAT must be taken into account.
Acknowledged by Master
To continue reading from a slave, the master is obliged to generate an acknowledge after the receipt of each byte.
The master must generate the clock pulse for each acknowledge bit. A master that acknowledges must pull down
the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this
clock pulse. Setup and hold times tSU:DAT and tHD:DAT must be taken into account.
Not Acknowledged by Slave
A slave device can be unable to receive or transmit data either because of an invalid access mode, because the
SHA-1 engine is running, or because an EEPROM write cycle is in progress. In this case, the DS28CN01 does not
acknowledge any bytes that it refuses by leaving SDA HIGH during the HIGH period of the acknowledge-related
clock pulse. See the Read and Write section for a detailed list of situations where the DS28CN01 does not
acknowledge.
Not Acknowledged by Master
At some time when receiving data, the master must terminate a read access. To achieve this, the master does not
acknowledge the last byte that it has received from the slave by leaving SDA high during the HIGH period of the
acknowledge-related clock pulse. In response, the slave stops transmitting, allowing the master to generate a
STOP condition.
Figure 3. I²C/SMBus Timing Diagram
SDA
tBUF
tHD:STA
tF
tLOW
tSP
SCL
tHD:STA
tR
tSU:STA
tHIGH
tHD:DAT
Spike
Suppression
tSU:STO
tSU:DAT
Repeated
START
STOP START
NOTE: Timing is referenced to VILMAX and VIHMIN.
Data Memory and Registers
For this section including Figures 4 to 5 and Tables 2 to 3 please refer to the full version of the data sheet.
Read and Write
This section discusses the read and write behavior of the EEPROM and the various registers. Please refer to the
full data sheet for details including Tables 4 to 13.
SHA-1 COMPUTATION ALGORITHM
This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document that can be
downloaded from the NIST website (http://www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are found in the
full version of the data sheet.
7 of 9
Abridged Data Sheet
DS28CN01
Application Information
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS28CN01 that requires a pullup resistor (Figure 6) to realize high logic levels.
Because the DS28CN01 uses SCL only as input (no clock stretching), the master can drive SCL either through an
open-drain/collector output with a pullup resistor or a push-pull output.
Pullup Resistor RP Sizing
According to the I²C specification, a slave device must be able to sink at least 3mA at a VOL of 0.4V. The SMBus
specification requires a current sink capability of 4mA at 0.4V. The DS28CN01 can sink at least 4mA at 0.4V VOL
over its entire operating voltage range. This DC characteristic determines the minimum value of the pullup resistor:
RPmin = (VCC - 0.4V)/4mA. With a maximum operating voltage of 5.5V, the minimum value for the pullup resistor is
1.275kΩ. The "Minimum RP" line in Figure 7 shows how the minimum pullup resistor changes with the operating
(pullup) voltage.
Figure 6. Application Schematic
VCC
RP
VCC
RP
To additional
devices
SDA
SCL
µC
VCC
DS28CN01
GND
SDA
SCL
AD1
AD0 GND
For I²C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum
bus capacitance CB is 400pF. The maximum rise time must not exceed 300ns. Assuming maximum rise time, the
maximum resistor value at any given capacitance CB is calculated as: RPmax = 300ns / (CB × ln(7/3)). For a bus
capacitance of 400pF the maximum pullup resistor would be 885Ω.
Since an 885Ω pullup resistor, as would be required to meet the rise time specification and 400pF bus capacitance,
is lower than RPmin at 5.5V, a different approach is necessary. The "Max Load…" line in Figure 7 is generated by
first calculating the minimum pullup resistor at any given operating voltage ("Minimum RP" line) and then calculating
the respective bus capacitance that yields a rise time of 300ns.
Only for pullup voltages of 4V and lower can the maximum permissible bus capacitance of 400pF be maintained. A
reduced bus capacitance of 300pF is acceptable for the entire operating voltage range. The corresponding pullup
resistor value at the voltage is indicated by the "Minimum RP" line.
8 of 9
Abridged Data Sheet
DS28CN01
Figure 7. I²C Fast Speed Pullup Resistor Selection Chart
Max. Load at Min. Rp fast mode
1200
600
1000
500
800
400
600
300
400
200
200
100
0
0
1.5
2
2.5
3
3.5
4
Pullup Voltage
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
9 of 9
4.5
5
5.5
Load (pF)
Minimum Rp (Ohms)
Mimimum Rp