DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 DS90LV031A 3V LVDS Quad CMOS Differential Line Driver Check for Samples: DS90LV031A FEATURES DESCRIPTION • • • • • • • • • The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. 1 23 • • • >400 Mbps (200 MHz) switching rates 0.1 ns typical differential skew 0.4 ns maximum differential skew 2.0 ns maximum propagation delay 3.3V power supply design ±350 mV differential signaling Low power dissipation (13mW at 3.3V static) Interoperable with existing 5V LVDS devices Compatible with IEEE 1596.3 SCI LVDS standard Compatible with TIA/EIA-644 LVDS standard Industrial operating temperature range Available in SOIC and TSSOP surface mount packaging The DS90LV031A accepts low voltage LVTTL/LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE® function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. Connection Diagram Figure 1. Dual-In-Line See Package Number D (R-PDSO-G16) or PW (R-PDSO-G16) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Functional Diagram Truth Table Enables Input Outputs EN EN* DIN DOUT+ DOUT− L H X Z Z L L H H H L All other combinations of ENABLE inputs These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) Input Voltage (DIN) −0.3V to (VCC + 0.3V) Enable Input Voltage (EN, EN*) −0.3V to (VCC + 0.3V) −0.3V to +3.9V Output Voltage (DOUT+, DOUT−) Short Circuit Duration (DOUT+, DOUT−) Continuous Maximum Package Power Dissipation @ +25°C D Package 1088 mW PW Package 866 mW Derate D Package 8.5 mW/°C above +25°C Derate PW Package 6.9 mW/°C above +25°C −65°C to +150°C Storage Temperature Range Lead Temperature Range Soldering (4 sec.) +260°C Maximum Junction Temperature ESD Rating +150°C (2) ≥ 6 kV (HBM, 1.5 kΩ, 100 pF) (1) (2) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. Electrical Characteristics specifies conditions of device operation. ESD Ratings: HBM (1.5 kΩ, 100 pF) ≥ 6 kV Recommended Operating Conditions Supply Voltage (VCC) Min Typ Max Units +3.0 +3.3 +3.6 V −40 +25 +85 °C Operating Free Air Temperature (TA) Industrial Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A 3 DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Conditions VOD1 Differential Output Voltage ΔVOD1 Change in Magnitude of VOD1 for Complementary Output States VOS Offset Voltage ΔVOS Change in Magnitude of VOS for Complementary Output States VOH Output Voltage High VOL Output Voltage Low VIH Input Voltage High VIL Input Voltage Low IIH Input Current VIN = VCC or 2.5V IIL Input Current VIN = GND or 0.4V VCL Input Clamp Voltage ICL = −18 mA IOS Output Short Circuit Current ENABLED, (4) DIN = VCC, DOUT+ = 0V or DIN = GND, DOUT− = 0V IOSD Differential Output Short Circuit Current ENABLED, VOD = 0V IOFF Power-off Leakage VOUT = 0V or 3.6V, VCC = 0V or Open IOZ Output TRI-STATE Current EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC ICC No Load Supply Current Drivers Enabled DIN = VCC or GND ICCL Loaded Supply Current Drivers Enabled ICCZ No Load Supply Current Drivers Disabled (1) (2) (3) (4) 4 RL = 100Ω (Figure 2) (1) (2) (3) Pin Min Typ Max DOUT− DOUT+ 250 350 450 mV 4 35 |mV| 1.25 1.375 V 5 25 |mV| 1.38 1.6 V 1.125 0.90 DIN, EN, EN* 1.03 Units V 2.0 VCC GND 0.8 V ±1 +10 μA −10 ±1 +10 μA −1.5 −0.8 −6.0 −9.0 mA −6.0 −9.0 mA −20 ±1 +20 μA −10 ±1 +10 μA 5.0 8.0 mA RL = 100Ω All Channels, DIN = VCC or GND (all inputs) 23 30 mA DIN = VCC or GND, EN = GND, EN* = VCC 2.6 6.0 mA −10 DOUT− DOUT+ (4) VCC V V Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and ΔVOD1. All typicals are given for: VCC = +3.3V, TA = +25°C. The DS90LV031A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90Ω to 110Ω) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Switching Characteristics - Industrial VCC = +3.3V ±10%, TA = −40°C to +85°C Symbol (1) (2) (3) Parameter Conditions tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD1 Differential Pulse Skew |tPHLD − tPLHD| tSKD2 Channel-to-Channel Skew RL = 100Ω, CL = 10 pF (Figure 3 and Figure 4) (4) (5) Min Typ Max Units 0.8 1.18 2.0 ns 0.8 1.25 2.0 ns 0 0.07 0.4 ns 0 0.1 0.5 ns tSKD3 Differential Part to Part Skew (6) tSKD4 Differential Part to Part Skew (7) tTLH Rise Time tTHL Fall Time tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High 7 tPZL Enable Time Z to Low 7 fMAX Maximum Operating Frequency (1) (2) (3) (4) (5) (6) (7) (8) 0 1.0 ns 0 1.2 ns 0.38 1.5 ns 0.40 1.5 ns 5 ns 5 ns ns RL = 100Ω, CL = 10 pF (Figure 5 and Figure 6) (8) 200 250 ns MHz All typicals are given for: VCC = +3.3V, TA = +25°C. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, and tf ≤ 1 ns. CL includes probe and jig capacitance. tSKD1, |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. tSKD2 is the Differential Channel-to-Channel Skew of any event on the same device. tSKD3, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. fMAX generator input conditions: tr = tf < 1ns, (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD > 250mV, all channels switching. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A 5 DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Parameter Measurement Information Figure 2. Driver VOD and VOS Test Circuit Figure 3. Driver Propagation Delay and Transition Time Test Circuit Figure 4. Driver Propagation Delay and Transition Time Waveforms 6 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Parameter Measurement Information (continued) Figure 5. Driver TRI-STATE Delay Test Circuit Figure 6. Driver TRI-STATE Delay Waveforms Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A 7 DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual (SNLA187), AN-808 (SNLA028), AN-1035 (SNOA355), AN-977 (SNLA166), AN971 (SNLA165), AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 8. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS90LV031A differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.5 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 8. AC or unterminated configurations are not allowed. The 3.5 mA loop current will develop a differential voltage of 350 mV across the 100Ω termination resistor which the receiver detects with a 250 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV – 100 mV = 250 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 7. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. The footprint of the DS90LV031A is the same as the industry standard 26LS31 Quad Differential (RS-422) Driver and is a step down replacement for the 5V DS90C031 Quad Driver. Power Decoupling Recommendations Bypass capacitors must be used on power pins. High frequency ceramic (surface mount is recommended) 0.1µF in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC Board considerations Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals. Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (LVDS port side) connectors as possible. 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Differential Traces Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. Lab experiments show that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is greater with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the auto-route function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable. Termination Use a resistor which best matches the differential impedance of your transmission line. The resistor should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS will not work without resistor termination. Typically, connect a single resistor across the pair at the receiver end. Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). Probing LVDS Transmission Lines Always use high impedance (> 100kΩ), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. Cables and Connectors, General Comments When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation as common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. Fail-safe of an LVDS Interface If the LVDS link as shown in Figure 8 needs to support the case where the Line Driver is disabled, powered off, or removed (un-plugged) and the Receiver device is powered on and enabled, the state of the LVDS bus is unknown and therefore the output state of the Receiver is also unknown. If this is of concern, please consult the respective LVDS Receiver data sheet for guidance on Failsafe Biasing options for the LVDS interface to set a known state on the inputs for these conditions. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A 9 DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com Figure 7. Driver Output Levels TYPICAL APPLICATION Figure 8. Point-to-Point Application Typical Performance Curves Figure 9. Typical DS90LV031A, DOUT (single ended) vs RL, TA = 25°C 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A DS90LV031A www.ti.com SNLS020C – JULY 1999 – REVISED APRIL 2013 Typical Performance Curves (continued) Figure 10. Typical DS90LV031A, DOUT vs RL, VCC = 3.3V, TA = 25°C PIN DESCRIPTIONS Pin No. Name Description 1, 7, 9, 15 DIN 2, 6, 10, 14 DOUT+ Driver input pin, TTL/CMOS compatible Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DOUT− Inverting driver output pin, LVDS levels 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +3.3V ± 0.3V 8 GND Ground pin Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A 11 DS90LV031A SNLS020C – JULY 1999 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DS90LV031A PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS90LV031ATM ACTIVE SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS90LV031A TM DS90LV031ATM/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV031A TM DS90LV031ATMTC ACTIVE TSSOP PW 16 92 TBD Call TI Call TI -40 to 85 DS90LV 031AT DS90LV031ATMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV 031AT DS90LV031ATMTCX ACTIVE TSSOP PW 16 TBD Call TI Call TI -40 to 85 DS90LV 031AT DS90LV031ATMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV 031AT DS90LV031ATMX ACTIVE SOIC D 16 2500 TBD Call TI Call TI -40 to 85 DS90LV031A TM DS90LV031ATMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS90LV031A TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DS90LV031ATMTCX/NO PB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 DS90LV031ATMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DS90LV031ATMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSSOP PW 16 2500 349.0 337.0 45.0 DS90LV031ATMX SOIC D 16 2500 367.0 367.0 35.0 DS90LV031ATMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 DS90LV031ATMTCX/NOP B Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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