TI SN75HVD1176

SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D – JULY 2003 – REVISED DECEMBER 2007
PROFIBUS RS-485 TRANSCEIVERS
FEATURES
APPLICATIONS
•
•
1
•
•
•
•
•
•
•
•
•
Optimized for PROFIBUS Networks
– Signaling Rates Up to 40 Mbps
– Differential Output Exceeds 2.1 V
(54 Ω Load)
– Low Bus Capacitance of 10 pF (Max)
Meets the Requirements of TIA/EIA-485-A
ESD Protection Exceeds ±10 kV HBM
Failsafe Receiver for Bus Open, Short, Idle
Up to 160 Transceivers on a Bus
Low Skew During Output Transitions and
Driver Enabling / Disabling
Common-Mode Rejection Up to 50 MHz
Short-Circuit Current Limit
Hot Swap Capable
Thermal Shutdown Protection
•
•
Process Automation
– Chemical Production
– Brewing and Distillation
– Paper Mills
Factory Automation
– Automobile Production
– Rolling, Pressing, Stamping Machines
– Networked Sensors
General RS-485 Networks
– Motor/Motion Control
– HVAC and Building Automation Networks
– Networked Security Stations
DESCRIPTION
These devices are half-duplex differential transceivers, with characteristics optimized for use in PROFIBUS (EN
50170) applications. The driver output differential voltage exceeds the Profibus requirements of 2.1 V with a 54 Ω
load. A signaling rate of up to 40 Mbps allows technology growth to high data transfer speeds. The low bus
capacitance provides low signal distortion.
The SN65HVD1176 and SN75HVD1176 meet or exceed the requirements of ANSI standard TIA/EIA-485-A
(RS-485) for differential data transmission across twisted-pair networks. The driver outputs and receiver inputs
are tied together to form a half-duplex bus port, with one-fifth unit load, allowing up to 160 nodes on a single bus.
The receiver output stays at logic high when the bus lines are shorted, left open, or when no driver is active. The
driver outputs are in high impedance when the supply voltage is below 2.5 V to prevent bus disturbance during
power cycling or during live insertion to the bus. An internal current limit protects the transceiver bus pins in
short-circuit fault conditions by limiting the output current to a constant value. Thermal shutdown circuitry protects
the device against damage due to excessive power dissipation caused by faulty loading and drive conditions.
The SN75HVD1176 is characterized for operation at temperatures from 0°C to 70°C. The SN65HVD1176 is
characterized for operation at temperatures from -40°C to 85°C.
LOGIC DIAGRAM (POSITIVE LOGIC)
D PACKAGE
(TOP VIEW)
D
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
A
B
DE
RE
R
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D – JULY 2003 – REVISED DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
(2)
TA
PACKAGED DEVICES (1)
PACKAGE MARKING (2)
0C to 70C
SN75HVD1176D
VN1176
-40°C to 85°C
SN65HVD1176D
VP1176
The D package is available taped and reeled. Add an R suffix to the device type (for example, SN65HVD1176DR).
For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted (1)
VCC
IO
SN65HVD1176
SN75HVD1176
UNIT
Supply voltage (2)
–0.5 to 7
V
Voltage at any bus I/O terminal
–9 to 14
V
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 15)
–40 to 40
V
Voltage input at any D, DE or RE terminal
–0.5 to 7
V
Receiver output current
Human Body Model,
(HBM) (3)
Electrostatic discharge
TJ
(1)
(2)
(3)
–10 to 10
mA
All pins
4
kV
Bus terminals and
GND
10
kV
150
°C
Junction temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal..
Tested in accordance with JEDEC standard 22. test method A114-A..
RECOMMENDED OPERATING CONDITIONS
VCC
Voltage at either bus I/O terminal
VIH
High-level input voltage
VIL
Low-level input voltage
VIL
Differential input voltage
IO
Output current
MAX
UNIT
5
5.25
V
–7
12
V
2
VCC
V
0
0.8
V
A with respect to B
-12
12
V
Driver
-70
70
mA
-8
8
mA
-40
130
Ω
0
130
Ω
40
Mbps
A, B
D, DE, RE
SN65HVD1176
(1)
Junction temperature
RL
Differential load resistance
1/tU1
Signaling rate
2
TYP
Receiver
TJ
(1)
MIN
4.75
Supply voltage
SN75HVD1176
Ω
54
See the Thermal Characteristics table for more information on maintenance of this requirement.
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
VCC
V
DRIVER
VO
Open-circuit output voltage
A or B,
No load
RL = 54 Ω
See Figure 1
|VOD(SS)|
Steady-state differential output voltage
magnitude
Δ|VOD(SS)|
Change in steady-state differential output
voltage between logic states
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode output
See Figure 5
voltage
VOC(PP)
Peak-to-peak common-mode output voltage
VOD(RING)
Differential output voltage over and under
shoot
RL = 54 Ω, CL = 50 pF, See Figure 6
II
Input current
D, DE
IO(OFF)
Output current with power off
VCC ≤ 2.5 V
IOZ
High impedance state output current
DE at 0 V
IOS(P)
Peak short-circuit output current
IOS(SS)
COD
0
With common-mode loading,
(VTEST from -7 V to 12 V)
See Figure 2
See Figure 1 and Figure 6
2.9
V
2.1
2.7
V
–0.2
0
0.2
V
2
2.5
3
V
–0.2
0
0.2
V
0.5
DE at VCC, See
Figure 8
V
10%
VOD(PP)
50
µA
250
mA
-50
See receiver line input
VOS = –7 V to 12 V
Steady-state short-circuit output current
2.1
-250
VOS > 4 V,
Output driving low
VOS < 1 V,
Output driving high
Differential output capacitance
60
90
135
mA
-135
-90
-60
mA
See receiver CID
pF
RECEIVER
VIT(+)
Positive-going differential input voltage
threshold
VIT(–)
Negative-going differential input voltage
threshold
VHYS
Hysteresis voltage (VIT+ – VIT-)
VOH
High-level output voltage
VID = 200 mV, IOH = –8 mA, See Figure 9
VOL
Low-level output voltage
VID = –200 mV, IOL = 8 mA, See Figure 9
IA, IB
SeeFigure 9
VO = 2.4 V, IO = –8 mA
–80
VO = 0.4 V, IO = 8 mA
IA(OFF)
IB(OFF)
Bus pin input current
VI = - 7 V to 12 V,
Other input = 0 V
II
Receiver enable input current
RE
IOZ
High-impedance - state output current
RE = VCC
RI
Input resistance
mV
-200
-120
mV
40
mV
4
4.6
0.2
V
0.4
V
–160
200
µA
–50
50
µA
–1
1
µA
VCC = 4.75 V to 5.25 V
VCC = 0 V
60
CID
Differential input capacitance
Test input signal is a 1.5 MHz sine wave with
amplitude 1 Vpp, capacitance measured across A
and B
CMR
Common mode rejection
See Figure 11
(1)
–20
kΩ
7
4
10
pF
V
All typical values are at VCC = 5 V and 25°C.
Copyright © 2003–2007, Texas Instruments Incorporated
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP ( MAX
1)
UNIT
DRIVER
tPLH
Propagation delay time low-level-to-high-level output
4
7
10
ns
tPHL
Propagation delay time high-level-to-low-level output
4
7
10
ns
tsk(p)
Pulse skew | tPLH – tPHL |
0
2
ns
tr
Differential output rise time
2
3
7.5
ns
tf
Differential output fall time
2
3
7.5
ns
tt(MLH), tt(MHL)
Output transition skew
0.2
1
ns
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active
output
10
20
ns
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-to- high-impedance
output
10
20
ns
|tp(AZL) – tp(BZH)|
|tp(AZH) – tp(BZL)|
Enable skew time
0.55
1.5
ns
|tp(ALZ) – tp(BHZ)|
|tp(AHZ) – tp(BLZ)|
Disable skew time
2.5
ns
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active
output (from sleep mode)
1
4
µs
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-output-to
high-impedance (to sleep mode)
30
50
ns
t(CFB)
Time from application of short-circuit to current
foldback
See Figure 8
t(TSD)
Time from application of short-circuit to thermal
shutdown
TA = 25°C, See Figure 8
RL = 54 Ω, CL = 50 pF,
See Figure 3
See Figure 4
RE at 0 V
RL = 110 Ω,
CL = 50 pF
See Figure 7
RE at 5 V
µs
0.5
µs
100
RECEIVER
tPLH
Propagation delay time, low-to-high level output
20
25
ns
tPHL
Propagation delay time, high-to-low level output
tsk(p)
Pulse skew | tPLH – tPHL |
20
25
ns
1
2
tr
ns
Receiver output voltage rise time
2
4
ns
tf
Receiver output voltage fall time
2
4
ns
tPZH
Propagation delay time, high-impedance-to-high-level
output
20
ns
tPHZ
Propagation delay time, high-level-to-high-impedance
output
tPZL
Propagation delay time, high-impedance-to-low-level
output
tPLZ
Propagation delay time, low-level-to-high-impedance
output
tPZH
Propagation delay time, high-impedance-to-high-level
output (standby to active)
tPHZ
Propagation delay time, high-level-to-high-impedance
output (active to standby)
tPZL
Propagation delay time, high-impedance-to-low-level
output (standby to active)
tPLZ
Propagation delay time, low-level-to-high-impedance
output (active to standby)
(1)
4
See Figure 10
DE at VCC,
See Figure 13
20
20
DE at VCC,
See Figure 14
DE at 0 V,
See Figure 12
DE at 0 V,
See Figure 12
20
ns
ns
ns
1
4
µs
13
20
ns
2
4
µs
13
20
ns
All typical values are at VCC = 5 V and 25°C.
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
Table 1. SUPPLY CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
Driver and receiver, RE at 0 V, DE at VCC, All other inputs open, no load
ICC
(1)
Supply
Current (1)
MAX
UNIT
4
6
mA
Driver only, RE at VCC, DE at VCC, All other inputs open, no load
3.8
6
mA
Receiver only, RE at 0 V, DE at 0 V, All other inputs open, no load
3.6
6
mA
Standby only, RE at VCC, DE at 0 V, All other inputs open
0.2
5
µA
TYP (2)
MAX
Over recommended operating conditions
THERMAL CHARACTERISTICS (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
θJA
Junction-to-ambient thermal resistance (3)
θJB
Junction-to-board thermal resistance
θJC
Junction-to-case thermal resistance
PD
Ambient air temperature
SN75HVD1176
SN65HVD1176
SN75HVD1176
TSD
(1)
(2)
(3)
(4)
(5)
°C/W
High-K board (5), no air flow
128.7
°C/W
77.6
°C/W
43.9
°C/W
RL = 54 Ω, CL = 50 pF, 0 V to 3 V,
15 MHz, 50% duty cycle square wave
input, driver and receiver enabled
Device power dissipation
UNIT
208.3
High-K board
SN65HVD1176
TA
MIN
, no air flow
Low-K board
(4)
277
Low-K board, no air flow,
PD = 318 mW
–40
High-K board, no air flow,
PD = 318 mW
–40
318
mW
64
°C
°C
0
89
Thermal shut down junction temperature
°C
°C
0
150
°C
See Application Information section for an explanation of these parameters.
All typical values are with VCC = 5 V and TA = 25°C.
The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
PARAMETER MEASUREMENT INFORMATION
NOTE:
Test load capacitance includes probe and jig capacitance (unless otherwise
specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50%
duty cycle, Zo = 50 Ω (unless otherwise specified).
II
A
IO
27 Ω
VOD
0 V or 3 V
D
B
IO
50 pF
27 Ω
VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
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PARAMETER MEASUREMENT INFORMATION (continued)
375 Ω
A
VOD
0 V or 3 V
VTEST = −7 V to 12 V
60 Ω
D
375 Ω
B
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V
INPUT
0V
VOD
RL = 54 Ω
Signal
Generator
CL = 50 pF
50 Ω
90%
VOD(H)
10%
VOD(L)
OUTPUT
tr
tf
Figure 3. Driver Switching Test Circuit and Rise/Fall Time Measurement
D
1.5 V
1.5 V
tPLH
tPHL
A,B
50%
A
50%
tt(MLH)
tt(MHL)
50%
B
50%
Figure 4. Driver Switching Waveforms for Propagation Delay and Output Midpoint Time Measurements
27 Ω
A
VA
D
Signal
Generator
50 Ω
27 Ω
B
≈ 3.25 V
VB
50 pF
≈ 1.75 V
VOC(PP)
VOC
∆VOC(SS)
VOC
Figure 5. Driver VOC Test Circuit and Waveforms
6
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VOD(SS)
VOD(RING)
VOD(PP)
0 V Differential
VOD(RING)
VOD(SS)
(1)
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
VOD(H) and VOD(L) steady state values.
Figure 6. VOD(RING) Waveform and Definitions
3V
DE
RL = 110 Ω
0V
D
DE
Signal
Generator
A
CL = 50 pF
RL = 110 Ω
B
50 Ω
VCC
1.5 V
tp(AZL)
tp(ALZ)
A
0V
50%
VOL +0.5 V
tp(BHZ)
tp(BZH)
CL = 50 pF
50%
B
VOL −0.5 V
a) D at Logic Low
3V
DE
1.5 V
1.5 V
RL = 110 Ω
0V
3V
D
DE
Signal
Generator
A
CL = 50 pF
tp(AZH)
A
50%
VOH −0.5 V
RL = 110 Ω
B
VCC
50 Ω
tp(AHZ)
tp(BLZ)
tp(BZL)
CL = 50 pF
50%
B
VOH +0.5 V
b) D at Logic High
Figure 7. Driver Enable/Disable Test
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PARAMETER MEASUREMENT INFORMATION (continued)
250
Output
Current |mA|
IOS
D
135
VOS
60
Voltage
Source
time
t(CFB)
t(TSD)
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t = 0)
IA
VA + VB
VIC
A
R
VA
VID
IO
B
VB
VO
IB
2
Figure 9. Receiver DC Parameter Definitions
Signal
Generator
50 Ω
Input B
VID
A
B
Signal
Generator
R
CL = 15 pF
50 Ω
IO
1.5 V
50%
Input A
tPLH
VO
Output
90%
1.5 V
0V
tPHL
VOH
10% V
OL
tr
tf
Figure 10. Receiver Switching Test Circuit and Waveforms
50 Ω
100 nF
VI = A sin 2 ft
1 MHz < f < 50 MHz
50 Ω
A
R
470 nF
RE
B
DE
2.2 kΩ
Voffset =
−2 V to 7 V
2.2 kΩ
VR
Scope
D
Scope
GND
VCC
100 nF
VR shall be greater than
2 V throughout this test.
Figure 11. Receiver Common-Mode Rejection Test Circuit
8
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
3V
A
0 V or 1.5 V
R
B
1.5 V or 0 V
RE
Input
Generator
VI
A
1 kΩ ± 1%
VO
S1
CL = 15 pF ±20%
B
50 Ω
3V
VI
1.5 V
0V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL(2)
3V
1.5 V
VO
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 12. Receiver Enable Time From Standby (Driver Disabled)
VCC
VCC
D
DE
A
54 Ω
B
R
3V
0V
RE
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
1 kΩ
tPHZ
tPZH
VOH
50 Ω
R
1.5 V
VOH −0.5 V
GND
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output High (Driver Active)
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PARAMETER MEASUREMENT INFORMATION (continued)
Ω
1 kΩ
Ω
Figure 14. Receiver Enable Test Circuit and Waveforms, Data Output Low (Driver Active)
VTEST
100 Ω
0V
Pulse Generator,
15 ms Duration,
1% Duty Cycle
1.5 ms
15 ms
−VTEST
Figure 15. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
Table 2. Driver Function Table (1)
(1)
INPUT
ENABLE
OUTPUTS
D
DE
A
H
H
H
L
L
H
L
H
X
L
Z
Z
X
OPEN
Z
Z
OPEN
H
H
L
B
H = high level, L = low level, X = don’t care,
Z = high impedance (off)
Table 3. Receiver Function Table (1)
(1)
10
DIFFRENTIAL INPUT
VID = (VA – VB)
ENABLE
RE
OUTPUT
R
VID ≥ 0.02 V
L
H
H = high level, L = low level, X = don’t care,
Z = high impedance (off), ? = indeterminate
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
Table 3. Receiver Function Table (continued)
DIFFRENTIAL INPUT
VID = (VA – VB)
ENABLE
RE
OUTPUT
R
–0.2 V < VID < –0.02 V
L
?
VID ≤ –0.2 V
L
L
X
H
Z
X
OPEN
Z
Open Circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
200 kΩ
500 Ω
500 Ω
Input
Input
200 kΩ
9V
9V
A Input
B Input
VCC
VCC
18 kΩ
16 V
18 kΩ
16 V
90 kΩ
90 kΩ
Input
Input
16 V
18 kΩ
16 V
18 kΩ
A and B Outputs
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
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SLLS563D – JULY 2003 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS
DRIVER SUPPLY CURRENT
vs
SIGNALING RATE
DIFFERENTIAL OUTPUT VOLTAGE
vs
LOAD CURRENT
5
66
VOD − Differential Output Voltage − V
4.5
100 Ω
VCC = 5.25 V
4
I DD − Driver Supply Current − mArms
VCC = 5 V
3.5
50 Ω
3
VCC = 4.75 V
2.5
2
1.5
1
64
62
60
VCC = 5 V
TA = 25°C
RL = 56 Ω,
DE and RE at 5 V
Input 0 V to 3 V PRBS
See NO TAG
58
56
0.5
TA = 25 C
0
0
20
40
60
IL − Load Current − mA
54
0
80
10
20
Figure 16.
4
3.75
VCC = 4.75 V
Driver Rise, Fall Time − ns
Driver Output Transition Skew − ns
RL = 54 Ω,
CL = 50 pF
See NO TAG
0.25
VCC = 5 V
0.15
VCC = 5.25 V
0.1
0.05
0
−40
RL = 54 Ω,
CL = 50 pF
See NO TAG
VCC = 4.75 V
3.5
VCC = 5 V
3.25
3
VCC = 5.25 V
2.75
2.5
2.25
−15
10
35
60
TA − Free-Air Temperature − °C
85
2
−40
−15
10
35
60
TA − Free-Air Temperature − °C
Figure 18.
12
50
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
0.35
0.2
40
Figure 17.
DRIVER OUTPUT TRANSITION SKEW
vs
FREE-AIR TEMPERATURE
0.3
30
Signaling Rate − Mbps
Submit Documentation Feedback
85
Figure 19.
Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1176 SN75HVD1176
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D – JULY 2003 – REVISED DECEMBER 2007
TYPICAL CHARACTERISTICS (continued)
DRIVER ENABLE SKEW
vs
FREE-AIR TEMPERATURE
0.7
VCC = 4.75 V
Driver Enable Skew − ns
0.6
0.5
VCC = 5.25 V
0.4
VCC = 5 V
0.3
0.2
0.1
RL = 110 Ω,
CL = 50 pF
See NO TAG
0
−40
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 20.
Copyright © 2003–2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SN65HVD1176 SN75HVD1176
13
SN65HVD1176
SN75HVD1176
www.ti.com
SLLS563D – JULY 2003 – REVISED DECEMBER 2007
APPLICATION INFORMATION
Thermal Characteristics of IC Packages
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
• PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card. θJB provides an overall thermal resistance between the die
and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA’s with thermal balls) and can be
used for simple 1-dimensional network analysis of package system (see Figure 21).
Ambient Node
q
CA
Calculated
Surface Node
qJC Calculated/Measured
Junction
qJB Calculated/Measured
PC Board
Figure 21. Thermal Resistance
14
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Copyright © 2003–2007, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD1176 SN75HVD1176
PACKAGE OPTION ADDENDUM
www.ti.com
28-Nov-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD1176D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1176DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1176DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD1176DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD1176D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD1176DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD1176DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75HVD1176DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD1176DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD1176DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD1176DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD1176DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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