NSC DS96F175MW/883

DS96F173M/DS96F175C/DS96F175M
EIA-485/EIA-422 Quad Differential Receivers
General Description
Features
The DS96F173 and the DS96F175 are high speed quad differential line receivers designed to meet the EIA-485 standard. The DS96F173 and the DS96F175 offer improved performance due to the use of L-FAST bipolar technology. The
use of LFAST technology allows the DS96F173 and
DS96F175 to operate at higher speeds while minimizing
power consumption.
The DS96F173 and the DS96F175 have TRI-STATE ® outputs and are optimized for balanced multipoint data bus
transmission at rates up to 15 Mbps. The receivers feature
high input impedance, input hysteresis for increased noise
immunity, and input sensitivity of 200 mV over a common
mode input voltage range of −7V to +12V. The receivers are
therefore suitable for multipoint applications in noisy environments. The DS96F173 features an active high and active
low Enable, common to all four receivers. The DS96F175
features separate active high Enables for each receiver pair.
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Logic Diagrams
Function Tables
Meets EIA-485, EIA-422A, EIA-423A standards
Designed for multipoint bus applications
TRI-STATE outputs
Common mode input voltage range: −7V to +12V
Operates from single +5.0V supply
Reduced power consumption (ICC = 50 mA max)
Input sensitivity of ± 200 mV over common mode range
Input hysteresis of 50 mV typical
High input impedance
Military temperature range available
Qualified for MIL STD 883C
Available to standard military drawings (SMD)
Available in DIP(J), LCC(E), and FlatPak (W) packages
DS96F173 and DS96F175 are lead and function
compatible with SN75173/175 or the
AM26LS32/MC3486
(Each Receiver) DS96F173
Differential Inputs
Output
A–B
E
E
Y
VID ≥ 0.2V
H
X
H
X
L
H
H
X
L
X
L
L
VID ≤ −0.2V
DS009627-10
DS96F175
Enable
X
L
X
Z
X
X
H
Z
H = High Level
L = Low Level
Z = High Impedance (off)
X = Don’t Care
(Each Receiver) DS96F175
DS009627-11
Differential Inputs
Enable
A–B
E
Output
Y
VID ≥ 0.2V
H
H
VID ≤ −0.2V
H
L
X
L
Z
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation
DS009627
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DS96F173M/DS96F175C/DS96F175M EIA-485/EIA-422 Quad Differential Receivers
July 2000
DS96F173M/DS96F175C/DS96F175M
COMMERCIAL
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 2)
Specifications for the 883 version of this product are
listed separately.
Supply Voltage (VCC)
DS96F175C
Common Mode Input
Voltage (VCM)
Differential Input Voltage
(VID)
Output Current HIGH (IOH)
Output Current LOW (IOL)
Operating Temperature (TA)
DS96F175C
Storage Temperature Range (TSTG)
−65˚C to +175˚C
Lead Temperature
(Soldering, 60 sec.)
300˚C
Max. Package Power Dissipation (Note 1) at 25˚C
Ceramic DIP (J)
1500 mW
Supply Voltage
7.0V
± 25V
Input Voltage, A or B Inputs
± 25V
Differential Input Voltage
Enable Input Voltage
7.0V
Low Level Output Current
50 mA
Min
Typ
Max
Units
4.75
5.0
5.25
V
+12
|12|
V
V
−400
11
µA
mA
70
˚C
−7
0
25
Note 1: Derate package 10 mW/˚C above 25˚C.
Electrical Characteristics (Notes 3, 4)
Over recommended supply voltage and operating temperature ranges, unless otherwise specified
Symbol
VTH
Parameter
Differential-Input
Conditions
Min
Typ
VO = VOH
Max
Units
0.2
V
High Threshold Voltage
VTL
Differential-Input (Note 5)
VO = VOL
−0.2
V
Low Threshold Voltage
VTH − VTL
Hysteresis (Note 6)
VIH
Enable Input Voltage HIGH
VIL
Enable Input Voltage LOW
VIC
Enable Input Clamp Voltage
II = −18 mA
VOH
Output Voltage HIGH
VID = 200 mV
0˚C to +70˚C
2.8
IOH = −400 µA
−55˚C to +125˚C
2.5
VID = −200 mV
IOL = 8.0 mA
0.45
IOL = 11 mA
0.50
VOL
Output Voltage LOW
VCM = 0V
50
mV
2.0
V
0.8
V
−1.5
V
V
V
± 20
µA
VI = 12V
1.0
mA
VI = −7.0V
−0.8
IOZ
High-Impedance State Output
VO = 0.4V to 2.4V
II
Line Input Current (Note 7)
Other Input = 0V
IIH
Enable Input Current HIGH
VIH = 2.7V
20
µA
IIL
Enable Input Current LOW
VIL = 0.4V
−100
µA
RI
Input Resistance
IOS
Short Circuit Output Current
(Note 8)
ICC
Supply Current
No Load
14
18
−15
ICCX
22
kΩ
−85
mA
Outputs Enabled
50
Outputs Disabled
50
mA
COMMERCIAL
Switching Characteristics
VCC = 5.0V, TA = 25˚C
Symbol
Parameter
Conditions
tPLH
Propagation Delay Time,
Low to High Level Output
CL = 15 pF, Figure 1
tPHL
Propagation Delay Time,
VCM = 0V
VID = −2.5V to +2.5V,
Min
Typ
Max
Units
5.0
15
22
ns
5.0
15
22
ns
High to Low Level Output
tZH
Output Enable Time to High Level
CL = 15 pF, Figure 2
12
16
ns
tZL
Output Enable Time to Low Level
CL = 15 pF, Figure 3
13
18
ns
tHZ
Output Disable Time from High Level
CL = 5.0 pF, Figure 2
14
20
ns
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2
(Continued)
VCC = 5.0V, TA = 25˚C
Typ
Max
tLZ
Symbol
Output Disable Time from Low Level
Parameter
CL = 5.0 pF, Figure 3
Conditions
Min
14
18
Units
ns
|tPLH–tPHL|
Pulse Width Distortion (SKEW)
Figure 1
1.0
3.0
ns
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the 0˚C to +70˚C range for the DS96F175C. All typicals are given for VCC = 5V and TA = 25˚C.
Note 4: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise specified.
Note 5: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 6: Hysteresis is the difference between the positive-going input threshold voltage. VTH, and the negative going input threshold voltage, VTL.
Note 7: Refer to EIA-485 Standard for exact conditions.
Note 8: Only one output at a time should be shorted.
Order Number: DS96F175CJ
See NS Package Number J16A
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DS96F173M/DS96F175C/DS96F175M
Switching Characteristics
DS96F173M/DS96F175C/DS96F175M
MIL-STD-883C
Recommended Operating
Conditions
Absolute Maximum Ratings (Note 2)
Min Typ Max Units
For complete Military Specifications, refer to the appropriate SMD or MDS.
Supply Voltage (VCC)
DS96F173M/DS96F175M
Storage Temperature Range (TSTG)
−65˚C to +175˚C
Lead Temperature
(Soldering, 60 sec.)
300˚C
Max. Package Power Dissipation (Note 9) at 25˚C
Ceramic DIP (J)
1500 mW
Ceramic Flatpak (W)
1034 mW
Ceramic LCC (E)
1500 mW
Supply Voltage
7.0V
± 25V
Input Voltage, A or B Inputs
± 25V
Differential Input Voltage
Enable Input Voltage
7.0V
Low Level Output Current
50 mA
4.50 5.0 5.50
Common Mode
Input Voltage (VCM)
−7
Differential Input Voltage (VID)
Output Current HIGH (IOH)
V
+12
V
|12|
V
−400
µA
11
mA
125
˚C
Output Current LOW (IOL)
Operating Temperature (TA)
DS96F173M/DS96F175M
−55
25
Note 9: Above TA = 25˚C derate J package 10 mW/˚C, W package
6.90 mW/˚C, E package 11.11 mW/˚C.
Electrical Characteristics (Notes 3, 4)
Over recommended supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Conditions
VTH
Differential-Input
High Threshold Voltage
VCC = 4.5V, 5.5V
VCM = 0V, 12V, −12V
VTL
Differential-Input (Note 5)
Low Threshold Voltage
VCC = 4.5V, 5.5V
VCM = 0V, 12V, −12V
Min
Max
Units
0.2
V
−0.2
V
VIH
Enable Input Voltage HIGH
VIL
Enable Input Voltage LOW
VIC
Enable Input Clamp Voltage
II = −18 mA, VCC = 4.5V
VOH
Output Voltage HIGH
VID = 200 mV
IOH = −400 µA
−55˚C to +125˚C
VOL
Output Voltage LOW
VID = −200 mV
IOL = 8.0 mA
0.45
V
IOZ
High-Impedance State Output
VO = 0.4V, 2.4V, VCC = 5.5V
± 20
µA
II
Line Input Current (Note 7)
Other Input = 0V
VI = 12V
1.0
VI = −7.0V
−0.8
2.0
V
0.8
V
−1.5
V
2.5
V
mA
IIH
Enable Input Current HIGH
VIH = 2.7V, VCC = 5.5V
20
µA
IIL
Enable Input Current LOW
VIL = 0.4V, VCC = 5.5V
−100
µA
−85
mA
50
mA
RI
Input Resistance
IOS
Short Circuit Output Current
(Note 8)
ICC
Supply Current
No Load
10
−15
Outputs Enabled
or Disabled
ICCX
kΩ
MIL-STD-883C
Switching Characteristics
VCC = 5.0V
Symbol
tPLH
Parameter
Conditions
TA = 25˚C
TA = −55˚C
TA =
125˚C
Units
Typ
Max
Max
Max
15
22
30
30
ns
Propagation Delay Time,
VID = −2.5V to +2.5V,
Low to High Level Output
CL = 15 pF, Figure 1
tPHL
Propagation Delay Time,
VCM = 0V
15
22
30
30
ns
tZH
Output Enable Time to High
Level
CL = 15 pF, Figure 2
12
16
27
27
ns
High to Low Level Output
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(Continued)
VCC = 5.0V
Symbol
Parameter
Conditions
TA = 25˚C
TA = −55˚C
TA =
125˚C
Typ
Max
Max
Max
Units
tZL
Output Enable Time to Low
Level
CL = 15 pF, Figure 3
13
18
27
27
ns
tHZ
Output Disable Time from High
Level
CL = 5.0 pF, Figure 2(Note 15)
14
20
27
27
ns
CL = 20 pF, Figure 2(Note 15)
14
30
37
37
ns
tLZ
Output Disable Time from Low
Level
CL = 5.0 pF, Figure 3
14
18
30
30
ns
Figure 1
1
3
5.0
5.0
ns
|tPLH–tPHL| Pulse Width Distortion (SKEW)
SMD Number:
DS96F173MJ
5962-9076602 MEA
DS96F173MW
5962-9076602 MFA
DS96F173ME
5962-9076602 M2A
DS96F175MJ
5962-9076601 MEA
DS96F175MW
5962-9076601 MFA
DS96F175ME
Order Number:
883 Marking
5962-9076601 M2A
SMD Marking
DS96F173MJ/883
DS96F173MJ-SMD
DS96F175MJ/883
DS96F175MJ-SMD
See NS Package Number
J16A
DS96F173ME/883
DS96F173ME-SMD
DS96F175ME/883
DS96F175ME-SMD
See NS Package Number
E20A
DS96F173MW/883
DS96F173MW-SMD
DS96F175MW/883
DS96F175MW-SMD
See NS Package Number
W16A
For complete Military Product Specifications, refer
to the appropriate SMD or MDS.
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DS96F173M/DS96F175C/DS96F175M
Switching Characteristics
DS96F173M/DS96F175C/DS96F175M
Connection Diagrams
16-Lead Ceramic Dual-In-Line Package
NS Package Number J16A
DS96F173
DS96F175
DS009627-1
DS009627-2
Top View
Top View
20-Lead Ceramic Leadless Chip Carrier
NS Package Number E20A
DS009627-12
DS009627-13
*NC — No Connection
Top View
Top View
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DS96F173M/DS96F175C/DS96F175M
Connection Diagrams
(Continued)
16-Lead Ceramic Flatpak
NS Package Number W16A
DS009627-14
DS009627-15
Top View
Top View
Order Numbers are located at the end of the respective Electrical Tables.
Parameter Measurement Information
DS009627-4
DS009627-3
FIGURE 1. tPLH, tPHL (Notes 10, 11)
DS009627-6
DS009627-5
FIGURE 2. tHZ, tZH (Notes 10, 11, 13, 14)
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DS96F173M/DS96F175C/DS96F175M
Parameter Measurement Information
(Continued)
DS009627-8
DS009627-7
FIGURE 3. tZL, tLZ (Notes 10, 11, 13, 14)
Note 10: The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, 50% duty cycle, tr ≤ 6.0 ns, tf ≤ 6.0 ns, ZO = 50Ω.
Note 11: CL includes probe and stray capacitance.
Note 12: DS96F173 with active high and active low Enables are shown. DS96F175 has active high Enable only.
Note 13: All diodes are 1N916 or equivalent.
Note 14: To test the active low Enable E of DS96F173, ground E and apply an inverted input waveform to E . DS96F175 has active high enable only.
Note 15: Testing at 20 pF assures conformance to 5 pF specification.
Typical Application
DS009627-9
FIGURE 4.
Note: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as possible.
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DS96F173M/DS96F175C/DS96F175M
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Ceramic Leadless Chip Carrier (E)
Order Number DS96F173ME/883 or DS96F175ME/883
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DS96F175CJ, DS96F173MJ/883 or DS96F175MJ/883
NS Package Number J16A
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DS96F173M/DS96F175C/DS96F175M EIA-485/EIA-422 Quad Differential Receivers
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Ceramic FlatPak (W)
Order Number DS96F173MW/883 or DS96F175MW/883
NS Package Number W16A
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