MOTOROLA DSP56001FC33

MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
24-Bit General Purpose
Digital Signal Processor
Order this document
by DSP56001/D
DSP56001
Pin Grid Array (PGA)
Available in an 88 pin ceramic
through-hole package.
Ceramic Quad Flat Pack (CQFP)
The DSP56001 is a member of Motorola’s family of
Available in a 132 pin, small footprint,
HCMOS, low-power, general purpose Digital Signal
surface mount package.
Processors. The DSP56001 features 512 words of full
speed, on-chip program RAM (PRAM) memory, two
Plastic Quad Flat Pack (PQFP)
256 word data RAMs, two preprogrammed data
Available in a 132 pin, small footprint,
ROMs, and special on-chip bootstrap hardware to persurface mount package.
mit convenient loading of user programs into the program RAM. It is an off-the-shelf part since the program
memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,
the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data
memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, compact code, straightforward.
The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer
and audio applications. The key features which facilitate this throughput are:
• Speed
At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute
a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).
• Precision
The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results
held in the 56-bit accumulators can range over 336 dB.
• Parallelism
The data ALU, address arithmetic units, and program controller operate in parallel so that an instruction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address
pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be
executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Response (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single
multiplier architecture.
• Integration
In addition to the three independent execution units, the DSP56001 has six on-chip memories,
three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Interface, and Host Interface), a clock generator and seven buses (three address and four data), making the overall system functionally complete and powerful, but also very low cost, low power, and
compact.
• Invisible Pipeline
The three-stage instruction pipeline is essentially invisible to the programmer thus allowing
straightforward program development in either assembly language or a high-level language such
as ANSI C.
• Instruction Set
The 62 instruction mnemonics are MCU-like making the transition from programming microprocessors to programming the DSP56001 digital signal processor as easy as possible. The orthogonal syntax supports control of the parallel execution units. This syntax provides 12,808,830 different instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction
and the REPEAT (REP) instruction make writing straight-line code obsolete.
• DSP56000/DSP56001
The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program
RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM
from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y
Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and
a full, four quadrant sine wave table, respectively.
Compatibility
• Low Power
As a CMOS part, the DSP56001 is inherently very low power; however, three other features can
reduce power consumption to an exceptionally low level.
— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.
— The STOP instruction halts the internal oscillator.
— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency
reduces power consumption.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
 MOTOROLA INC., 1992
Rev. 3
May 4, 1998
YAB
XAB
PAB
PORT B
OR HOST
15
9
BOOTSTRAP
ROM
32X24
ON-CHIP
PERIPHERALS:
HOST, SSI,
SCI, PI/O
PROGRAM
RAM
512X24
PORT C
AND/OR
SSI, SCI
X MEMORY
RAM
256X24
µ/A ROM
256X24
Y MEMORY
RAM
256X24
SINE ROM
256X24
BUS
CONTROL
7
EXTERNAL
DATA BUS
SWITCH
DATA
YDB
INTERNAL DATA
BUS SWITCH
AND BIT
MANIPULATION
UNIT
CLOCK
GENERATOR
EXTERNAL ADDRESS
ADDRESS
BUS
SWITCH
XDB
PDB
GDB
PROGRAM
ADDRESS
GENERATOR
PROGRAM
DECODE
CONTROLLER
DATA ALU
24X24+56→56-BIT MAC
TWO 56-BIT ACCUMULATORS
PROGRAM
INTERRUPT
CONTROLLER
MODB/IRQB
EXTAL
PORT A
ADDRESS
GENERATION
UNIT
XTAL
MODA/IRQA
16 BITS
24 BITS
RESET
Figure 1. DSP56001 Block Diagram
In the USA:
For technical assistance call:
DSP Applications Helpline (512) 891-3230
For availability and literature call your local Motorola Sales Office or Authorized Motorola Distributor.
For free application software and information call the Dr. BuB electronic bulletin board:
9600/4800/2400/1200/300 baud
(512) 891-3771
(8 data bits, no parity, 1 stop)
In Europe, Japan and Asia Pacific
Contact your regional sales office or Motorola distributor.
MOTOROLA
2
DSP56001
SIGNAL DESCRIPTION
Read Enable (RD)
This three-state output is asserted to read external memory on the
data bus D0-D23. This pin is three-stated during RESET.
The DSP56001 is available in 132 pin surface mount (CQFP and
PQFP) or an 88-pin pin-grid array packaging. Its input and output signals are organized into seven functional groups which are listed below
and shown in Figure 1.
Write Enable (WR)
This three-state output is asserted to write external memory on the
data bus D0-D23. This pin is three-stated during RESET.
Port A Address and Data Buses
Port A Bus Control
Interrupt and Mode Control
Power and Clock
Host Interface or Port B I/O
Serial Communications Interface or Port C I/O
Synchronous Serial Interface or Port C I/O
Bus Request (BR/WT)
The bus request input BR allows another device such as a processor
or DMA controller to become the master of external data bus D0-D23
and external address bus A0-A15. When operating mode register
(OMR) bit 7 is clear and BR is asserted, the DSP56001 will always release the external data bus D0-D23, address bus A0-A15, and bus
control pins PS, DS, X/Y, RD, and WR (i. e., Port A), by placing these
pins in the high-impedance state after execution of the current instruction has been completed. The BR pin should be pulled up when not
in use.
PORT A ADDRESS AND DATA BUS
Address Bus (A0-A15)
These three-state output pins specify the address for external program
and data memory accesses. To minimize power dissipation, A0-A15
do not change state when external memory spaces are not being accessed.
If OMR bit 7 is set, this pin is an input that allows an external device to
force wait states during an external Port A operation for as long as WT
is asserted.
Bus Grant (BG/BS)
Data Bus (D0-D23)
If OMR bit 7 is clear, this output is asserted to acknowledge an external
bus request after Port A has been released. If OMR bit 7 is set, this pin
is bus strobe and is asserted when the DSP accesses Port A. This pin
is three-stated during RESET.
These pins provide the bidirectional data bus for external program and
data memory accesses. D0-D23 are in the high-impedance state when
the bus grant signal is asserted.
PORT A BUS CONTROL
INTERRUPT AND MODE CONTROL
Program Memory Select (PS)
Mode Select A/External Interrupt Request A (MODA/IRQA),
This three-state output is asserted only when external program memory is referenced. This pin is three-stated during RESET.
Mode Select B/External Interrupt Request B (MODB/IRQB)
These two inputs have dual functions: 1) to select the initial chip operating mode and 2) to receive an interrupt request from an external
source. MODA and MODB are read and internally latched in the DSP
when the processor exits the RESET state. Therefore these two pins
should be forced into the proper state during reset. After leaving the
RESET state, the MODA and MODB pins automatically change to external interrupt requests IRQA and IRQB. After leaving the reset state
the chip operating mode can be changed by software. IRQA and IRQB
may be programmed to be level sensitive or negative edge triggered.
When edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal, however, the probability of noise on IRQA or IRQB generating multiple interrupts increases with increasing fall time of the interrupt signal. These pins are inputs
during RESET.
Data Memory Select (DS)
This three-state output is asserted only when external data memory is
referenced. This pin is three-stated during RESET.
X/Y Select (X/Y)
This three-state output selects which external data memory space (X
or Y) is referenced by data memory select (DS). This pin is three-stated during RESET.
ADDRESS
DATA
HACK
HREQ
HEN
HR/W
HA2
HA1
HA0
HOST DATA
BUS
H0-H7
HOST CONTROL
Reset (RESET)
RXD
A0-A15
PORT B
D0-D23
TXD
PS
DS
SC0
PORT C
PORT A
RD
WR
X/Y
SC1
SCK
DSP56001
SRD
BR/WT
STD
MODA/
IRQA
MODB/
IRQB
RESET
EXTAL
XTAL
VDD
BG/BS
VSS
BUS
CONTROL
SCI
SCLK
SSI
This Schmitt trigger input pin is used to reset the DSP56001. When
RESET is asserted, the DSP56001 is initialized and placed in the reset
state. When the RESET signal is deasserted, the initial chip operating
mode is latched from the MODA and MODB pins. When coming out of
reset, deassertion occurs at a voltage level and is not directly related
to the rise time of the reset signal; however, the probability of noise on
RESET generating multiple resets increases with increasing rise time
of the reset signal.
POWER AND CLOCK
Power (Vcc), Ground (GND)
There are five sets of power and ground pins used for the four groups
of logic on the chip, two pairs for internal logic, one power and two
ground for Port A address and control pins, one power and two ground
for Port A data pins, and one pair for peripherals. Refer to the pin assignments in the LAYOUT PRACTICES section.
Figure 2. Functional Signal Groups
DSP56001
MOTOROLA
3
External Clock/Crystal Input (EXTAL)
Transmit Data (TXD)
EXTAL may be used to interface the crystal oscillator input to an external crystal or an external clock.
This output transmits serial data from the SCI Transmit Shift Register.
Data changes on the negative edge of the transmit clock. This output
is stable on the positive edge of the transmit clock. TXD may be programmed as a general purpose I/O pin called PC1 when the SCI is not
being used. This pin is configured as a GPIO input pins during hardware reset.
Crystal Output (XTAL)
This output connects the internal crystal oscillator output to an external
crystal. If an external clock is used, XTAL should not be connected.
SCI Serial Clock (SCLK)
HOST INTERFACE
Host Data Bus (H0-H7)
This bidirectional data bus is used to transfer data between the host
processor and the DSP56001. This bus is an input unless enabled by
a host processor read. H0-H7 may be programmed as general purpose parallel I/O pins called PB0-PB7 when the Host Interface is not
being used. These pins are configured as a GPIO input pins during
hardware reset.
This bidirectional pin provides an input or output clock from which the
transmit and/or receive baud rate is derived in the asynchronous mode
and from which data is transferred in the synchronous mode. SCLK
may be programmed as a general purpose I/O pin called PC2 when
the SCI is not being used. This pin is configured as a GPIO input pins
during hardware reset.
SYNCHRONOUS SERIAL INTERFACE (SSI)
Host Address (HA0-HA2)
Serial Control Zero (SC0)
These inputs provide the address selection for each Host Interface
register. HA0-HA2 may be programmed as general purpose parallel
I/O pins called PB8-PB10 when the Host Interface is not being used.
These pins are configured as a GPIO input pins during hardware reset.
This bidirectional pin is used for control by the SSI. SC0 may be programmed as a general purpose I/O pin called PC3 when the SSI is not
being used. This pin is configured as a GPIO input pins during hardware reset.
Host Read/Write (HR/W)
Serial Control One (SC1)
This input selects the direction of data transfer for each host processor
access. HR/W may be programmed as a general purpose I/O pin
called PB11 when the Host Interface is not being used. This pin is configured as a GPIO input pins during hardware reset.
This bidirectional pin is used for control by the SSI. SC1 may be programmed as a general purpose I/O pin called PC4 when the SSI is not
being used. This pin is configured as a GPIO input pins during hardware reset.
Host Enable (HEN)
Serial Control Two (SC2)
This input enables a data transfer on the host data bus. When HEN is
asserted and HR/W is high, H0-H7 become outputs, and DSP56001
data may be read by the host processor, When HEN is asserted and
HR/W is low, H0-H7 become inputs and host data is latched inside the
DSP when HEN is deasserted. Normally a chip select signal, derived
from host address decoding and an enable clock, is used to generate
HEN. HEN may be programmed as a general purpose I/O pin called
PB12 when the Host Interface is not being used. This pin is configured
as a GPIO input pins during hardware reset.
This bidirectional pin is used for control by the SSI. SC2 may be programmed as a general purpose I/O pin called PC5 when the SSI is not
being used. This pin is configured as a GPIO input pins during hardware reset.
Host Request (HREQ)
SSI Serial Clock (SCK)
This bidirectional pin provides the serial bit rate clock for the SSI when
only one clock is used. SCK may be programmed as a general purpose I/O pin called PC6 when the SSI is not being used. This pin is
configured as a GPIO input pins during hardware reset.
This open-drain output signal is used by the DSP56001 Host Interface
to request service from the host processor, DMA controller, or simple
external controller. HREQ may be programmed as a general purpose
I/O pin (not open-drain) called PB13 when the Host interface is not being used. HREQ should be pulled high when not in use. This pin is configured as a GPIO input pins during hardware reset.
SSI Receive Data (SRD)
Host Acknowledge (HACK)
This output pin transmits serial data from the SSI Transmit Shift Register. STD may be programmed as a general purpose I/O pin called
PC8 when the SSI is not being used. This pin is configured as a GPIO
input pins during hardware reset.
This input has two functions: 1) to receive a Host Acknowledge handshake signal for DMA transfers and, 2) to receive a Host Interrupt Acknowledge compatible with MC68000 Family processors. HACK may
be programmed as a general purpose I/O pin called PB14 when the
Host Interface is not being used. This pin is configured as a GPIO input
pins during hardware reset. HACK should be pulled high when not
in use.
This input pin receives serial data into the SSI Receive Shift Register.
SRD may be programmed as a general purpose I/O pin called PC7
when the SSI is not being used. This pin is configured as a GPIO input
pins during hardware reset.
SSI Transmit Data (STD)
SERIAL COMMUNICATIONS INTERFACE (SCI)
Receive Data (RXD)
This input receives byte-oriented data into the SCI Receive Shift Register. Input data is sampled on the positive edge of the Receive Clock.
RXD may be programmed as a general purpose I/O pin called PC0
when the SCI is not being used. This pin is configured as a GPIO input
pins during hardware reset.
MOTOROLA
4
DSP56001
DSP56001 Electrical Characteristics
Electrical Specifications
The DSP is fabricated in high density CMOS with TTL compatible inputs and outputs.
Maximum Ratings (VSS = 0 Vdc)
Rating
Symbol
Value
Unit
Supply Voltage
Vcc
-0.3 to +7.0
V
All Input Voltages
Vin
VSS- 0.5 to Vcc + 0.5
V
I
10
mA
TJ
-40 to +105
°C
Tstg
-55 to +150
°C
Current Drain per Pin
excluding Vcc and VSS
Operating Temperature Range
Storage Temperature
Maximum Electrical Ratings
Thermal Characteristics - PGA Package
Characteristics
Thermal Resistance - Ceramic
Symbol
Value
Rating
Junction to Ambient
ΘJA
27
°C/W
Junction to Case (estimated)
ΘJC
6.5
°C/W
Thermal Characteristics - CQFP Package
Characteristics
Thermal Resistance - Ceramic
Junction to Ambient
Junction to Case (estimated)
Symbol
ΘJA
ΘJC
Value
40
7.0
Rating
°C/W
°C/W
Thermal Characteristics - PQFP Package
Characteristics
Thermal Resistance - Plastic
Symbol
Value
Rating
Junction to Ambient
ΘJA
38
°C/W
Junction to Case (estimated)
ΘJC
13.0
°C/W
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal
precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either Gnd or Vcc).
DSP56001
MOTOROLA
5
DSP56001 Electrical Characteristics
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD × ΘJA)
(1)
Where:
TA = Ambient Temperature, °C
ΘJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
PD = PINT + PI/O
PINT = ICC × Vcc, Watts - Chip Internal Power
PI/O = Power Dissipation on Input and Output Pins - User Determined
For most applications PI/O << PINT and can be neglected; however, PI/O + PINT must not exceed Pd. An appropriate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K/(TJ + 273° C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273° C) + ΘJA × PD2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation (2) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of
TA. The total thermal resistance of a package (ΘJA) can be separated into two components, ΘJC and CA, representing the barrier to
heat flow from the semiconductor junction to the package (case) surface (ΘJC) and from the case to the outside ambient (CA). These
terms are related by the equation:
ΘJA = ΘJC + CA
(4)
ΘJC is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal
management techniques as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management on the part of
the user can significantly reduce CA so that ΘJA approximately equals ΘJC. Substitution of ΘJC for ΘJA in equation (1) will result in a
lower semiconductor junction temperature. Values for thermal resistance presented in this document, unless estimated, were derived
using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX
Microcomponent Devices”, and are provided for design purposes only. Thermal measurements are complex and dependent on
procedure and setup. User-derived values for thermal resistance may differ.
Layout Practices
Each Vcc pin on the DSP56001 should be provided with a low-impedance path to + 5 volts. Each GND pin should likewise be provided
with a low-impedance path to ground. The power supply pins drive four distinct groups of logic on chip. They are:
Vcc
GND
Function
G12,C6
G11,B7
Internal Logic supply pins
L8
L6,L9
Address bus output buffer supply pins
G3
D3,J3
Data bus output buffer supply pins
C9
E11
Port B and C output buffer supply pins
Power and Ground Connections for PGA
Vcc
GND
Function
35, 36, 128, 129 33, 34, 130, 131
Internal Logic supply pins
63, 64
55, 56, 73, 74
Address bus output buffer supply pins
100, 101
90, 91, 111, 112
Data bus output buffer supply pins
12, 13
23, 24
Port B and C output buffer supply pins
Power and Ground Connections for CQFP and PQFP
MOTOROLA
6
DSP56001
DSP56001 Electrical Characteristics
Power and Ground Connections
The Vcc power supply should be bypassed to ground using at least four 0.1 uF by- pass capacitors located either underneath the chip
or as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip
Vcc and Gnd should be kept to less than 1/2" per capacitor lead. A four-layer board is recommended, employing two inner layers as
Vcc and Gnd planes. All output pins on the DSP56001 have fast rise and fall times — typically less than 3 ns. with a 10 pf. load. Printed
circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast
output switching times. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB,
and HEN pins. Maximum PC trace lengths on the order of 6" are recommended. Capacitance calculations should consider all device
loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents in the Vcc and GND circuits. Pull up/down
all unused inputs or signals that will be inputs during reset.
Signal Stability
When designing hardware to interface with the Host Interface, it is important to ensure that all signals be clean and free from noise.
Particular attention should be given to the quality of the Host Enable (HEN). All inputs to the port should be stable when HEN is
asserted and should remain stable until HEN has fully returned to the deasserted state. It is important to note that such phenomena
as ground-bounce and cross-talk can inadvertently cause HEN to temporarily rise above Vil max. Should this occur without completing
the full logic transition to Vih min, the DSP56001 Host Port may not correctly update the port status information which can result in
storing two or more copies of a single down loaded data word. Of course, if a full logic transition occurs, the part will complete a normal
data transfer operation.
DSP56001
MOTOROLA
7
DSP56001 Electrical Characteristics
DC Electrical Characteristics (Vcc = 5.0 Vdc + 10%; TJ = -40 to +105° C at 20.5 MHz and 27 MHz)
(Vcc = 5.0 Vdc + 5%; TJ = -40 to +105° C at 33 MHz)
Characteristic
Supply Voltage
20, 27 MH z
33 MHz
Symbol
Min
Typ
Max
Unit
Vcc
4.5
4.75
5.0
5.5
5.25
V
Input High Voltage
Except EXTAL, RESET, MODA/IRQA, MODB/IRQB
VIH
2.0
—
Vcc
V
Input Low Voltage
Except EXTAL, MODA/IRQA, MODB/IRQB
VIL
-0.5
—
0.8
V
Input High Voltage
VIHC
4.0
—
Vcc
V
EXTAL
Input Low Voltage
EXTAL
VILC
-0.5
—
0.6
V
Input High Voltage
RESET
VIHR
2.5
—
Vcc
V
Input High Voltage
MODA/IRQA and MODB/IRQB
VIHM
3.5
—
Vcc
V
Input Low Voltage
MODA/IRQA and MODB/IRQB
VILM
-0.5
—
2.0
V
Input Leakage Current
EXTAL, RESET, MODA/IRQA, MODB/IRQB, BR
Iin
-1
—
1
uA
Three-State (Off-State) Input Current
(@2.4 V/0.4 V)
ITSI
-10
—
10
uA
(IOH = -0.4 mA)
VOH
2.4
—
—
V
Output Low Voltage
(IOL = 1.6 mA;
RD, WR IOL = 1.6 mA; Open Drain
HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA)
VOL
—
—
0.4
V
Total Supply Current
IDD33
IDD27
IDD20
IDDW
IDDS
160
130
100
10
100
185
155
115
25
2000
mA
mA
mA
mA
µA
10
—
pf
Output High Voltage
Input Capacitance
5.25 V, 33 MHz
5 . 5 V, 27 MHz
5 . 5 V, 20 MHz
in WAIT Mode (see Note 1)
in STOP Mode (see Note 1)
(see Note 2)
Cin
—
—
—
—
—
—
Notes:
1. In order to obtain these results all inputs must be terminated (i.e., not allowed to float).
2. Periodically sampled and not 100% tested.
MOTOROLA
8
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for
all pins, except EXTAL, RESET, MODA, and MODB. These four pins are tested using the input levels set forth in the DC Electrical
Characteristics. AC timing specifications which are referenced to a device input signal are measured in production with respect to the
50% point of the respective input signal’s transition. DSP56001 output levels are measured with the production test machine VOL and
VOH reference levels set at 0.8 V and 2.0 V respectively.
AC Electrical Characteristics - Clock Operation
The DSP56001 system clock may be derived from the on-chip crystal oscillator as shown in Clock Figure 1, or it may be externally
supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected
(see Clock Figure 2) to the board or socket. The rise and fall time of this external clock should be 5 ns maximum.
Characteristics
Num
1
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
Frequency of Operation (EXTAL Pin)
4.0
20.5
4.0
27.0
4.0
33.0
MHz
External Clock Input High (tch) —
22
150
17
150
13.5
150
ns
22
150
17
150
13.5
150
ns
EXTAL Pin
2
20.5 MHz
(see Note 1 and 2)
External Clock Input Low (tcl) —
EXTAL Pin
(see Note 1 and 2)
3
Clock Cycle Time = cyc = 2T
48.75
250
37
250
30.33
250
ns
4
Instruction Cycle Time = Icyc = 4T
97.5
500
74
500
60
500
ns
Notes:
1. External Clock Input High and External Clock Input Low are measured at 50% of the
input transition. tch and tcl are dependent on the duty cycle.
2. T = Icyc / 4 is used in the electrical characteristics. T represents an average which is
independent of the duty cycle.
DSP56001
MOTOROLA
9
DSP56001 Electrical Characteristics
XTAL
EXTAL
EXTAL
XTAL
R
R2
R1
•
•
•
•
•
•
C1
•
•
C
C
XTAL1
L1
C2
C3
3rd Overtone
Crystal Oscillator
Fundamental Frequency
Crystal Oscillator
Suggested Component Values
For fosc = 4 MHz:
R = 680 KΩ + 10%
C = 20 pf + 20%
XTAL1*
Suggested Component Values
R1 = 470 KΩ + 10%
R2 = 330 Ω + 10%
C1 = 0.1 µf + 20%
C2 = 26 pf + 20%
C3 = 20 pf + 10%
L1 = 2.37 µH + 10%
XTAL =33 MHz, AT cut, 20 pf load,
5 0Ω max series resistance
For fosc = 30 MHz:
R = 680 KΩ + 10%
C = 20 pf + 20%
Notes:
(1) The suggested crystal source is ICM,
# 433163 - 4.00 (4MHz fundamental, 20
pf load) or # 436163 - 30.00 (30 MHz fundamental, 20 pf load).
Notes:
(1) *3rd overtone crystal.
(2) The suggested crystal source is ICM, # 471163 - 33.00 (33
MHz 3rd overtone, 20 pf load).
(3) R2 limits crystal current
(4) Reference Benjamin Parzen, The Design of Crystal and
Other Harmonic Oscillators, John Wiley& Sons, 1983
Clock Figure 1. Crystal Oscillator Circuits
VIHC
Midpoint
EXTAL
VILC
1
2
3
4
Note: The midpoint is VILC + 0.5 (VIHC - VILC).
Clock Figure 2. External Clock Timing
MOTOROLA
10
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Reset, Stop, Mode Select and Interrupt Timing
(Vcc = 5.0 Vdc +10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
(See Control Figure 1 through 8)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of wait states (1 WS = 1 cyc = 2T) programmed into external bus access
using BCR (WS = 0 - 15)
tch = Clock high period
tcl = Clock low period
Characteristics
Num
9
10
12
13
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
—
50
—
38
—
31
ns
75000 cyc
*
25 cyc
*
—
—
75000*cyc
25 cyc
*
—
—
75000*cyc
25 cyc
*
—
—
ns
ns
Delay from Asynchronous RESET
Deassertion to First External Address
Output (Internal Reset Negation)
8 cyc
*
9 cyc+40
*
8*cyc
9*cyc+31
8*cyc
9*cyc+25
ns
Synchronous Reset Setup Time from
RESET Deassertion to Falling Edge of
External Clock
20
cyc-10
15
cyc-8
13
cyc-7
ns
Synchronous Reset Delay Time from
the Synchronous Falling Edge of External Clock to the First External Address
Output
8 cyc+5
*
8 cyc+30
*
8*cyc+5
8*cyc+23
8*cyc+5
8*cyc+19
ns
—
62
—
ns
Delay from RESET Assertion to
Address High Impedance (periodically
sampled and not 100% tested)
Minimum Stabilization Duration
Internal Osc. (see Note 1)
External Clock (see Note 2)
11
20.5 MHz
14
Mode Select Setup Time
100
—
77
15
Mode Select Hold Time
0
—
0
16
Edge-Triggered Interrupt Request
25
15
—
—
17
10
assertion
16a
0
—
—
16
10
ns
—
—
ns
ns
deassertion
VIHR
RESET
10
11
9
A0-A15
First Fetch
Control Figure 1. Reset Timing
DSP56001
MOTOROLA
11
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Reset, Stop, Mode Select, and Interrupt Timing
(Continued)
NOTE
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the negative edge-triggered mode is recommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode.
Characteristics
Num
17
18
19
20
Delay from IRQA, IRQB Assertion to
External Memory Access Address Out
Valid Caused by First Interrupt
Instruction Fetch
Instruction Execution
Delay from IRQA, IRQB Assertion to
General Purpose Transfer Output Valid
Caused by First Interrupt Instruction
Execution
Delay from Address Output Valid
Caused by First Interrupt Instruction
Execution to Interrupt Request
Deassertion for Level Sensitive Fast
Interrupts
Delay from RD Assertion to Interrupt
Request Deassertion for Level
Sensitive Fast Interrupts
21
Delay from WR Assertion to WS=0
Interrupt Request Deassertion for
WS>0 Level Sensitive Fast Interrupts
22
Delay from General-Purpose Output
Valid to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts
- If Second Interrupt Instruction is:
Single Cycle
Two Cycle
MOTOROLA
12
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
5 cyc+tch
9*cyc+tch
*
—
—
5 cyc+tch
9*cyc+tch
*
—
—
5 cyc+tch
9*cyc+tch
*
—
—
ns
ns
11+cyc
+tch
—
11 cyc
*
+tch
—
11 cyc
*
+tch
—
ns
—
2 cyc+tcl+
*
(cyc
WS)
*
-44
—
2 cyc+tcl+
*
(cyc
WS)
*
-34
—
2 cyc+tcl+
*
(cyc
WS)
*
-27
ns
2 cyc+
*
(cyc WS)
*
-25
ns
—
2 cyc+
*
(cyc WS)
*
-40
—
2 cyc+
*
(cyc WS)
*
-31
—
—
—
2 cyc-40
*
cyc+tcl+
(cyc WS)
*
-40
—
—
2 cyc-31
*
cyc+tcl+
(cyc WS)
*
-31
—
—
2 cyc-25
*
cyc+tcl+
(cyc WS)
*
-25
ns
ns
—
—
tcl-60
(2 cyc)+tcl
* -60
—
—
tcl-46
(2 cyc)+tcl
* -46
—
—
tcl-37
(2 cyc)+tcl
* -37
ns
ns
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Reset, Stop, Mode Select, and Interrupt Timing
(Continued)
Characteristics
Num
23
24
25
26
27
Synchronous Interrupt Setup Time
from IRQA, IRQB Assertion to the
Synchronous Rising Edge of External
Clock (see Notes 5, 6)
Synchronous Interrupt Delay Time
from the Synchronous Rising Edge of
External Clock to the First External
Address Output Valid Caused by the
First Instruction Fetch after Coming out
of Wait State (see Notes 3, 5)
Duration for IRQA Assertion to
Recover from Stop State (see Note 4)
Duration for Level Sensitive IRQA
Assertion to Fetch of First Interrupt
Instruction (for Stop) for
Internal Osc / OMR bit 6 = 0
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
25
cyc-10
19
cyc-8
16
cyc-7
ns
13 cyc+
*
tch+8
13 cyc+
*
tch+30
13 cyc+
*
tch+6
13 cyc+
*
tch+23
13 cyc+
*
tch+5
13 cyc+
*
tch+19
ns
25
—
19
—
16
—
ns
—
—
65545 cyc
*
17 cyc
*
—
—
65545 cyc
*
17 cyc
*
—
—
ns
ns
65533 cyc
+tcl*
—
65533 cyc
+tcl*
—
65533 cyc
+tcl*
—
ns
5 cyc+tcl
*
—
5 cyc+tcl
*
—
5 cyc+tcl
*
—
ns
—
—
65545 cyc
*
17 cyc
*
—
—
65545 cyc
*
17 cyc
*
—
—
ns
ns
Delay from IRQA Assertion to Fetch of
First Instruction (for Stop) for
Internal Osc / OMR bit 6 = 0 65545 cyc
*
External Clock / OMR bit 6 = 1
17 cyc
*
(see Notes 1, 2, and 7)
External Clock / OMR bit 6 = 1
(see Notes 1, 2, and 7)
28
20.5 MHz
Delay from Level Sensitive IRQA
Assertion to Fetch of First Interrupt
Instruction (for Stop) for
I nternal Osc / OMR bit 6 = 0
65545 cyc
*
External Clock / OMR bit 6 = 1
17 cyc
*
(see Notes 1, 2, and 7)
Notes:
1. A clock stabilization delay is required when using the on-chip crystal oscillator in
two cases:
1) after power-on reset, and
2) when recovering from Stop mode.
During this stabilization period, T will not be constant. Since this stabilization period
varies, a delay of 150,000T is typically allowed to assure that the oscillator is stabilized
before executing programs. While it is possible to set OMR bit 6 = 1 when using
the internal crystal oscillator, it is not recommended and these specifications do not
guarantee timings for that case. See Section 8.5 in the DSP56000/DSP56001 User’s Manual for
additional information.
2. Circuit stabilization delay is required during reset when using an external clock in
two cases:
1) after power-on reset, and
2) when recovering from Stop mode.
3. For Revision B silicon, the min and max numbers are 12cyc+Tch+8 and 12cyc+Tch+30, respectively.
4. The minimum is specified for the duration of an edge triggered IRQA interrupt required to recover
from the STOP state without having the IRQA interrupt accepted.
5. Timing #23 is for all IRQx interrupts while timing #24 is only when exiting WAIT.
6. Timing #23 triggers off T1 in the normal state and off T1/T3 when exiting the WAIT state.
7. The timings in the table are for Rev. C parts. The timings for Rev. C parts are shorter by 1 cyc than
the Rev. B parts when OMR6=0.
DSP56001
MOTOROLA
13
DSP56001 Electrical Characteristics
EXTAL
12
RESET
13
11
A0-A15,
DS, PS
X/Y
Control Figure 2. Synchronous Reset Timing
VIHR
RESET
14
15
MODA, MODB
VIHM
VIH
VILM
VIL
IRQA, IRQB
Control Figure 3. Operating Mode Select Timing
IRQA, IRQB
16
16a
Control Figure 4. External Interrupt Timing (Negative Edge-Triggered)
MOTOROLA
14
DSP56001
DSP56001 Electrical Characteristics
A0-A15
First Interrupt Instruction Execution
RD
20
WR
21
17
19
IRQA
IRQB
a) First Interrupt Instruction Execution
General
Purpose
I/O
18
22
IRQA
IRQB
b) General Purpose I/O
Control Figure 5. External Level-Sensitive Fast Interrupt Timing
DSP56001
MOTOROLA
15
DSP56001 Electrical Characteristics
T0, T2
EXTAL
T1, T3
23
IRQA, IRQB
24
A0-A15, DS
PS, X/Y
Control Figure 6. Synchronous Interrupt and Synchronous Wait State Timing
IRQA
25
26
A0-A15, DS,
PS, X/Y
First Instruction Fetch
Control Figure 7. Recovery from Stop State Using IRQA
IRQA
27
28
A0-A15, DS,
PS, X/Y
First IRQA Interrupt
Instruction Fetch
Control Figure 8. Recovery from Stop State Using IRQA Interrupt Service
MOTOROLA
16
DSP56001
DSP56001 Electrical Characteristics
HOST PORT USAGE CONSIDERATIONS
Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common
problem when two asynchronous systems are connected. The situation exists in the Host port. The considerations for proper operation
are discussed below.
Host Programmer Considerations
1.
Unsynchronized Reading of Receive Byte Registers
When reading receive byte registers, RXH, RXM, or RXL, the Host programmer should use interrupts or poll the RXDF flag which
indicates that data is available. This assures that the data in the receive byte registers will be stable.
2.
Overwriting Transmit Byte Registers
The Host programmer should not write to the transmit byte registers, TXH, TXM, or TXL, unless the TXDE bit is set indicating that
the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register.
3.
Synchronization of Status Bits from DSP to Host
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF (refer to DSP56000/DSP56001 User’s Manual, I/O Interface section, Host/
DMA Interface Programming Model for descriptions of these status bits) status bits are set or cleared from inside the DSP and
read by the Host processor. The Host can read these status bits very quickly without regard to the clock rate used by the DSP,
but the possibility exists that the state of the bit could be changing during the read operation. This is generally not a system
problem, since the bit will be read correctly in the next pass of any Host polling routine.
However, if the Host asserts the HEN for more than timing number 31a (T31a), with a minimum cycle time of timing number 32a
(T32a), then the status is guaranteed to be stable.
A potential problem exists when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00
to 11, there is a small probability that the Host could read the bits during the transition and receive 01 or 10 instead of 11. If the
combination of HF3 and HF2 has significance, the Host could read the wrong combination.
Solution:
a. Read the bits twice and check for consensus.
b. Assert HEN access for T31a so that status bit transitions are stabilized.
4.
Overwriting the Host Vector
The Host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change will
guarantee that the DSP interrupt control logic will receive a stable vector.
5.
Cancelling a Pending Host Command Exception
The Host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is
recognized by the DSP. Because the Host does not know exactly when the exception will be recognized (due to exception
processing synchronization and pipeline delays), the DSP may execute the Host exception after the HC bit is cleared. For these
reasons, the HV bits must not be changed at the same time the HC bit is cleared.
DSP Programmer Considerations
1.
Reading HF0 and HF1 as an Encoded Pair
DMA, HF1, HF0, and HCP, HTDE, and HRDF (refer to DSP56000/DSP56001 User’s Manual, I/O Interface section, Host/DMA
Interface Programming Model for descriptions of these status bits) status bits are set or cleared by the Host processor side of the
interface. These bits are individually synchronized to the DSP clock.
A potential problem exists when reading status bits HF1 and HF2 as an encoded pair, i.e., the four combinations 00, 01, 10, and
11 each have significance. A very small probability exists that the DSP will read the status bits synchronized during transition.
The solution to this potential problem is to read the bits twice for consensus.
DSP56001
MOTOROLA
17
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Host I/O Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
(see Host Figures 1 through 6)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tHSDL = Host Synchronization Delay Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications
Characteristics
Num
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
30
Host Synchronous Delay (see Note 1)
tcl
cyc+tcl
tcl
cyc+tcl
tcl
cyc+tcl
ns
31
HEN/HACK Assertion Width
(see Note 2)
a.CVR, ICR, ISR Read (see Note 4)
b.Read
c.Write
cyc+60
50
25
—
—
—
cyc+46
39
19
—
—
—
cyc+37
31
16
—
—
—
ns
ns
ns
25
—
19
—
16
—
ns
2*cyc+60
—
2*cyc+46
—
2*cyc+37
—
ns
32
HEN/HACK Deassertion Width
(see Note 2 and 5)
32a
Minimum Cycle Time Between Two
HEN Assertion for Consecutive CVR,
ICR, and ISR Reads (see Note 2)
33
Host Data Input Setup Time Before
HEN/HACK Deassertion
5
—
4
—
4
—
ns
34
Host Data Input Hold Time After HEN/
HACK Deassertion
5
—
4
—
4
—
ns
35
HEN/HACK Assertion to Output Data
Active from High Impedance
0
—
0
—
0
—
ns
36
HEN/HACK Assertion to Output Data
Valid (periodically sampled, and not
100% tested)
—
50
—
39
—
31
ns
37
HEN/HACK Deassertion to Output
Data High Impedance
—
35
—
27
—
22
ns
38
Output Data Hold Time After HEN/
HACK Deassertion
5
—
4
—
4
—
ns
39
HR/W Low Setup Time Before HEN
Assertion
0
—
0
—
0
—
ns
40
HR/W Low Hold Time After HEN
Deassertion
5
—
4
—
4
—
ns
41
HR/W High Setup Time to HEN
Assertion
0
—
0
—
0
—
ns
42
HR/W High Hold Time After HEN/
HACK Deassertion
5
—
4
—
4
—
ns
43
HA0-HA2 Setup Time Before HEN
Assertion
0
—
0
—
0
—
ns
44
HA0-HA2 Hold Time After HEN
Deassertion
5
—
4
—
4
—
ns
45
DMA HACK Assertion to HREQ
Deassertion
(see Note 3)
5
60
4
46
4
49
ns
MOTOROLA
18
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Host I/O Timing (Continued)
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz
(Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see Host Figures 1 through 6)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tHSDL = Host Synchronization Delay Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications
Characteristics
Num
46
20.5 MHz
DMA HACK Deassertion to HREQ
Assertion
(see Note 3)
for DMA RXL Read
for DMA TXL Write
for All Other Cases
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
tHSDL+cyc
+tch+5
tHSDL+cyc+5
5
—
tHSDL+cyc
+tch+4
tHSDL+cyc+4
4
—
tHSDL+cyc
+tch+4
tHSDL+cyc+4
4
—
ns
—
—
ns
ns
—
—
—
—
47
Delay from HEN Deassertion to HREQ
Assertion for RXL Read (see Note 3)
tHSDL+cyc
+tch+5
—
tHSDL+cyc
+tch+4
—
tHSDL+cyc
+tch+4
—
ns
48
Delay from HEN Deassertion to HREQ
Assertion for TXL Write (see Note 3)
tHSDL+cyc+5
—
tHSDL+cyc+4
—
tHSDL+cyc+4
—
ns
49
Delay from HEN Assertion to HREQ
Deassertion for RXL Read, TXL Write
(see Note 3)
5
75
4
70
4
65
ns
Notes:
1. “Host synchronization delay (tHSDL)” is the time period required for the
DSP56001 to sample any external asynchronous input signal, determine
whether it is high or low, and synchronize it to the DSP56001 internal clock.
2. See HOST PORT USAGE CONSIDERATIONS.
3. HREQ is pulled up by a 1kΩ resistor.
4. This timing must be adhered to only if two consecutive reads from one of these registers are executed.
5. It is recommended that timing #32 be 2cyc+tch+10 minimum for 20.5 MHz, 2cyc+tch+7 minimum for 27 MHz,
and 2cyc+tch+6 minimum for 33 MHz if two consecutive writes to TXL are executed without polling TXDE or
HREQ.
EXTERNAL
30
30
INTERNAL
Host Figure 1. Host Synchronization Delay
DSP56001
MOTOROLA
19
DSP56001 Electrical Characteristics
HREQ
(OUTPUT)
31
32
HACK
(INPUT)
41
42
HR/W
(INPUT)
36
37
35
H0-H7
(OUTPUT)
38
Data
Valid
Host Figure 2. Host Interrupt Vector Register (IVR) Read
MOTOROLA
20
DSP56001
DSP56001 Electrical Characteristics
HREQ
(OUTPUT)
49
32A
RXH
Read
HEN
(INPUT)
31
RXM
Read
RXL
Read
32
43
44
Address
Valid
HA2-HA0
(INPUT)
47
41
Address
Valid
Address
Valid
42
HR/W
(INPUT)
H0-H7
(OUTPUT)
36
37
35
38
Data
Valid
Data
Valid
Data
Valid
Host Figure 3. Host Read Cycle (Non-DMA Mode)
DSP56001
MOTOROLA
21
DSP56001 Electrical Characteristics
HREQ
(OUTPUT)
49
TXH
Write
HEN
(INPUT)
TXM
Write
31
TXL
Write
32
43
44
Address
Valid
HA2-HA0
(INPUT)
48
Address
Valid
39
Address
Valid
40
HR/W
(INPUT)
33
34
Data
Valid
H0-H7
(INPUT)
Data
Valid
Data
Valid
Host Figure 4. Host Write Cycle (Non-DMA Mode)
HREQ
(OUTPUT)
45
46
31
HACK
(INPUT)
H0-H7
(OUTPUT)
46
46
32
RXH
Read
RXM
Read
36
37
35
38
Data
Valid
Data
Valid
RXL
Read
Data
Valid
Host Figure 5. Host DMA Read Cycle
MOTOROLA
22
DSP56001
DSP56001 Electrical Characteristics
HREQ
(OUTPUT)
45
46
31
HACK
(INPUT)
46
46
32
TXH
Write
TXM
Write
TXL
Write
33
34
H0-H7
(INPUT)
Data
Valid
Data
Valid
Data
Valid
Host Figure 6. Host DMA Write Cycle
DSP56001
MOTOROLA
23
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SCI Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see SCI Figures 1 and 2)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tSCC = Synchronous Clock Cycle Time (for internal clock tSCC is determined by the SCI clock control register and Icyc.)
SCI Synchronous Mode Timing
Characteristics
Num
20.5 MHz
Min
55
Synchronous Clock Cycle — tSCC
56
Clock Low Period
27 MHz
33 MHz
Unit
Max
Min
Max
Min
Max
—
8 cyc
*
4 cyc-15
*
4 cyc-15
*
2 cyc
*
+tcl-39
—
8 cyc
*
4 cyc-13
*
4 cyc-13
*
2 cyc
*
+tcl-31
—
ns
—
ns
57
Clock High Period
59
Output Data Setup to Clock Falling
Edge (Internal Clock)
8 cyc
*
4 cyc-20
*
4 cyc-20
*
2 cyc
*
+tcl-50
60
Output Data Hold After Clock Rising
Edge (Internal Clock)
2 cyc
*
-tcl-15
—
2 cyc
*
-tcl-11
—
61
Input Data Setup Time Before Clock
Rising Edge (Internal Clock)
2 cyc
*
+tcl+45
—
2 cyc
*
+tcl+35
62
Input Data Not Valid Before Clock Rising Edge (Internal Clock)
—
2 cyc
*
+tcl-10
63
Clock Falling Edge to Output Data
Valid (External Clock)
—
64
Output Data Hold After Clock Rising
Edge (External Clock)
65
66
—
—
ns
—
ns
2 cyc
*
-tcl-9
—
ns
—
2 cyc
*
+tcl+28
—
ns
—
2 cyc
*
+tcl-8
—
2 cyc
*
+tcl-6
ns
63
—
48
—
39
ns
cyc+12
—
cyc+9
—
cyc+8
—
ns
Input Data Setup Time Before Clock
Rising Edge (External Clock)
30
—
23
—
19
—
ns
Input Data Hold Time After Clock Rising Edge (External Clock)
40
—
31
—
25
—
ns
MOTOROLA
24
—
—
—
—
—
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SCI Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see SCI Figures 1 and 2)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tACC = Asynchronous clock cycle time
tACC = Asynchronous Clock Cycle Time (for internal clock tACC is determined by the SCI clock control register and Icyc)
SCI Asynchronous Mode Timing - 1X Clock
Characteristics
Num
67
Asynchronous Clock Cycle
68
Clock Low Period
69
Clock High Period
71
Output Data Setup to Clock Rising
Edge (Internal Clock)
72
Output Data Hold After Clock Rising
Edge (Internal Clock)
DSP56001
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
64 cyc
*
32 cyc-20
*
32 cyc-20
*
32 cyc
*
-100
—
64 cyc
*
32 cyc-15
*
32 cyc-15
*
32 cyc
*
-77
—
64 cyc
*
32 cyc-13
*
32 cyc-13
*
32 cyc
*
-61
—
ns
—
ns
32 cyc
*
-100
—
—
—
—
32 cyc
*
-77
—
—
—
—
32 cyc
*
-61
—
ns
—
ns
—
ns
MOTOROLA
25
DSP56001 Electrical Characteristics
INTERNAL CLOCK
55
58
57
58
56
SCLK
(OUTPUT)
59
60
TXD
DATA VALID
61
62
DATA
VALID
RXD
EXTERNAL CLOCK
55
57
56
SCLK
(INPUT)
63
64
TXD
DATA
65
RXD
VALID
66
DATA VALID
SCI Figure 1. SCI Synchronous Mode Timing
MOTOROLA
26
DSP56001
DSP56001 Electrical Characteristics
67
70
69
70
68
1X SCK
(OUTPUT)
71
TXD
72
DATA VALID
Note: In the wire-OR mode, TXD can be pulled up by 1KΩ
SCI Figure 2. SCI Asynchronous Mode Timing
DSP56001
MOTOROLA
27
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SSI Timing
(Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
see SSI Figures 1 and 2)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tSSICC = SSI clock cycle time
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) = Receive Frame Sync
i ck = Internal Clock
x ck = External Clock
g ck = Gated Clock
i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and
RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and
RXC are the same clock)
bl = bit length
wl = word length
Characteristics
Num
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
4 cyc
*
2 cyc-20
*
2 cyc-20
*
—
4 cyc
*
2 cyc-15
*
2 cyc-15
*
—
4 cyc
*
2 cyc-13
*
2 cyc-13
*
—
ns
—
—
ns
—
ns
80
Clock Cycle (see Note 1)
81
Clock High Period
82
Clock High Period
84
RXC Rising Edge to FSR Out (bl) High
x ck
i ck a
—
—
80
50
—
—
61
38
—
—
48
31
ns
ns
RXC Rising Edge to FSR Out (bl) Low
x ck
i ck a
—
—
70
40
—
—
54
31
—
—
43
25
ns
ns
RXC Rising Edge to FSR Out (wl) High
x ck
i ck a
—
—
70
40
—
—
54
31
—
—
43
25
ns
ns
RXC Rising Edge to FSR Out (wl) Low
x ck
i ck a
—
—
70
40
—
—
54
31
—
—
43
25
ns
ns
Data In Setup Time Before RXC (SCK
in Synchronous Mode) Falling Edge
x ck
i ck a
i ck s
15
35
25
—
—
—
12
27
19
—
—
—
10
22
16
—
—
—
ns
ns
ns
Data In Hold Time After RXC Falling
Edge
x ck
i ck a
35
5
—
—
27
4
—
—
22
4
—
—
ns
ns
FSR Input (bl) High Before RXC Falling
Edge
x ck
i ck a
15
35
—
—
12
27
—
—
10
23
—
—
ns
ns
FSR Input (wl) High Before RXC
Falling Edge
x ck
i ck a
20
55
—
—
15
42
—
—
13
34
—
—
ns
ns
FSR Input Hold Time After RXC Falling
Edge
x ck
i ck a
35
5
—
—
27
4
—
—
22
4
—
—
ns
ns
85
86
87
88
89
90
91
92
MOTOROLA
28
—
—
—
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SSI Timing (Continued)
Note:
1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.
Characteristics
Num
93
94
95
96
97
98
99
100
101
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
Flags Input Setup Before RXC Falling
Edge
x ck
i ck a
30
50
—
—
23
39
—
—
19
31
—
—
ns
nss
Flags Input Hold Time After RXC
Falling Edge
x ck
i ck a
35
5
—
—
27
4
—
—
22
4
—
—
ns
ns
TXC Rising Edge to FST Out (bl) High
x ck
i ck a
—
—
70
30
—
—
54
23
—
—
43
19
ns
ns
TXC Rising Edge to FST Out (bl) Low
x ck
i ck a
—
—
65
35
—
—
50
27
—
—
40
22
ns
ns
TXC Rising Edge to FST Out (wl) High
x ck
i ck a
—
—
65
35
—
—
50
27
—
—
40
22
ns
ns
TXC Rising Edge to FST Out (wl) Low
x ck
i ck a
—
—
65
35
—
—
50
27
—
—
40
22
ns
ns
TXC Rising Edge to Data Out Enable
from High Impedance
x ck
i ck a
—
—
65
40
—
—
50
31
—
—
40
25
ns
ns
TXC Rising Edge to Data Out Valid
x ck
i ck a
—
—
65
40
—
—
50
31
—
—
40
25
ns
ns
TXC Rising Edge to Data Out High
Impedance (periodically sampled, and
not 100% tested)
x ck
i ck a
—
—
70
40
—
—
54
31
—
—
43
25
ns
ns
cyc+tch
—
cyc+tch
—
cyc+tch
—
ns
15
35
—
—
12
27
—
—
10
23
—
—
ns
ns
—
60
—
46
—
37
ns
101a TXC Falling Edge to Data Out High
Impedance for Gated Clock Mode Only
g ck
102
20.5 MHz
FST Input (bl) Setup Time Before TXC
Falling Edge
x ck
i ck a
103
FST Input (wl) to Data Out Enable from
High Impedance
104
FST Input (wl) Setup Time Before TXC
Falling Edge
x ck
i ck a
20
55
—
—
15
42
—
—
13
34
—
—
ns
ns
FST Input Hold Time After TXC Falling
Edge
x ck
i ck a
35
5
—
—
27
4
—
—
22
4
—
—
ns
ns
Flag Output Valid After TXC Rising
Edge
x ck
i ck a
—
—
70
40
—
—
54
31
—
—
43
25
ns
ns
105
106
Note:
1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.
DSP56001
MOTOROLA
29
DSP56001 Electrical Characteristics
80
81
83
83
82
RXC
(Input/Output)
84
85
FSR (Bit)
OUT
86
87
FSR (Word)
OUT
88
89
First
DATA IN
90
Bit
Last Bit
92
FSR (Bit)
IN
91
92
93
94
FSR (Word)
IN
FLAGS IN
SSI Figure 1. SSI Receiver Timing
MOTOROLA
30
DSP56001
DSP56001 Electrical Characteristics
80
83
83
81
82
TXC
(Input/Output)
95
96
FST (Bit)
OUT
98
97
FST (Word)
OUT
100
100
101
99
101a
DATA OUT
First Bit
Last Bit
102
105
FST (Bit)
IN
103
104
105
FST (Word)
IN
106
(See Note 1)
FLAGS OUT
Note:
1. In the Network mode, output flag transitions can occur at the start of each time slot within
the frame. In the Normal mode, the output flag state is asserted for the entire frame
period.
SSI Figure 2. SSI Transmitter Timing
DSP56001
MOTOROLA
31
DSP56001 Electrical Characteristics
AC Electrical Characteristics —
Capacitance Derating — External Bus Asynchronous Timing
Vcc = 5.0 Vdc + 10%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
Vcc = 5.0 Vdc + 5%, TJ = -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz, see Bus Figures 1 and 2
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
WS = Number of Wait States, Determined by BCR Register (WS = 0 to 15)
The DSP56001 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pf, including
stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y) derates
linearly at 1 ns per 12 pf of additional capacitance from 50 pf to 250 pf of loading. Port B and C pins derate linearly at 1 ns per
5 pf of additional capacitance from 50 pf to 250 pf of loading.
Active low inputs should be “pulled up” in a manner consistent with the AC and DC specifications.
To conserve power, when an internal memory access follows an external memory access, the RD and WR strobes remain
deasserted and A0-A15 and X/Y do not change from their previous state. Both PS and DS will be deasserted (they do not
change between two external accesses to the same memory space) indicating that no external memory access is occurring.
If BR has been asserted, then the bus signals will be three-stated according to the timing information in this data sheet.
Characteristics
Num
20.5 MHz
Min
115
Max
27 MHz
Min
Delay from BR Assertion to BG
Assertion
(see Note 1)
2 cyc+tch 4*cyc+tch+ 2 cyc+tch
*
*
20
(see Note 2)
cyc+tch 4*cyc+tch+ cyc+tch
cyc*WS+20
(see Note 3)
cyc+tch 6*cyc+tch+ cyc+tch
2*cyc*WS+
20
(see Note 4)
Infinity
—
Infinity
(see Note 5)
tch+4
cyc+tch+30
tch+3
2*cyc
2*cyc-10
—
0
—
—
tcl-9
cyc-9
4*cyc+tch+ 2 cyc+tch
*
15
4*cyc+tch+ cyc+tch
cyc*WS+15
6*cyc+tch+ cyc+tch
2*cyc*WS+
15
—
Infinity
cyc+tch+23
tch+3
Max
4*cyc+tch+
13
4*cyc+tch+
cyc*WS+13
6*cyc+tch+
2*cyc*WS+
13
—
cyc+tch+19
ns
4*cyc+13
ns
ns
ns
ns
ns
Flags Input Hold Time After RXC
Falling Edge Deassertion
117
BG Deassertion Duration
118
Delay from Address, Data, and Control
Bus High Impedance to BG Assertion
119
Delay from BG Deassertion to
Address, Data, and Control Bus
Enabled
120
Address Valid to WR Assertion WS=0
WS>0
121
WR Assertion Width
122
WR Deassertion to Address Not Valid
tch-12
—
tch-9
—
tch-7.5
—
ns
123
WR Assertion to Data Out Valid WS=0
WS>0
tch-9
0
tch+10
10
tch-7
0
tch+8
8
tch-5.5
0
tch+6.5
6.5
ns
ns
124
Data Out Hold Time from WR
Deassertion (The maximum specification is periodically sampled, and not
100% tested.)
tch-9
tch+7
tch-7
tch+6
tch-5.5
tch+4.5
ns
125
Data Out Setup Time to WR
Deassertion (see Note 6)
—
—
tcl-5
WS*cyc
+tcl-5
—
—
tcl-5
WS*cyc
+tcl-5
—
—
ns
ns
—
tch-7
—
tch-5.5
—
ns
WS=0
cyc-9
WS>0 WS*cyc
+tcl-9
WS=0
tcl-5
WS>0 WS*cyc
+tcl-5
RD Deassertion to Address Not Valid
MOTOROLA
32
4*cyc+20
Min
Unit
116
126
2*cyc
Max
33 MHz
tch-9
4*cyc+15
2*cyc
2*cyc-8
—
2*cyc-6
—
ns
0
—
0
—
ns
tch-10
—
tch-8
—
tch-6
ns
tcl+5
cyc+5
tcl-7
cyc-7
tcl+5
cyc+5
tcl-5.5
cyc-5.5
tcl+5
cyc+5
ns
ns
—
—
cyc-7
WS*cyc
+tcl-7
—
—
cyc-5.0
WS*cyc
+tcl-5.0
—
—
ns
ns
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - External Bus Asynchronous Timing
(Continued)
Characteristics
Num
20.5 MHz
WS = 0
WS > 0
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
cyc+tcl-8
((WS+1)
cyc)+tcl-8*
—
—
cyc+tcl-6
((WS+1)
cyc)+tcl-6*
—
—
cyc+tcl-6
((WS+1)
cyc)+tcl-6*
—
—
ns
ns
0
—
0
—
0
—
ns
127
Address Valid to
RD deassertion
128
Input Data Hold Time to RD
Deassertion
129
RD Assertion Width
WS = 0
WS > 0
cyc-9
((WS+1)*
cyc)-9
—
—
cyc-7
((WS+1)*
cyc)-7
—
—
cyc-5.5
((WS+1)*
cyc)-5.5
—
—
ns
ns
130
Address Valid to
Input Data Valid
WS = 0
WS > 0
—
—
cyc+tcl-18
((WS+1)
*
cyc)+tcl-18
—
—
cyc+tcl-14
((WS+1)
*
cyc)+tcl-14
—
—
cyc+tcl-11
((WS+1)
*
cyc)+tcl-11
ns
ns
tcl-9
tcl+5
tcl-7
tcl+5
tcl-5.5
tcl+5
ns
—
—
cyc-14
((WS+1)*
cyc)-14
—
—
cyc-11
((WS+1)*
cyc)-11
—
—
cyc-9
((WS+1)*
cyc)-9
ns
ns
cyc-15
—
cyc-12
—
cyc-10
—
ns
cyc-10
131
Address Valid to RD Assertion
132
RD Assertion to
Input Data Valid
133
WR Deassertion to RD Assertion
134
RD Deassertion to RD Assertion
—
cyc-8
—
cyc-6.5
—
ns
135
WR Deassertion to
WR Assertion
cyc-15
WS=0
WS>0 cyc+tch-15
—
—
cyc-12
cyc+tch-12
—
—
cyc-10
cyc+tch-10
—
—
ns
ns
136
RD Deassertion to
WR Assertion
cyc-10
WS=0
WS>0 cyc+tch-10
—
—
cyc-8
cyc+tch-8
—
—
cyc-6.5
cyc+tch6.5
—
—
ns
ns
WS=0
WS>0
Notes:
1. With no external access from the DSP.
2. During external read or write access.
3. During external read-modify-write access.
4. During the STOP mode the external bus will not be released and BG will not go low. However,
if the bus is released (BG = 0) and the STOP instruction is executed while BG = 0 then the bus will remain
released while the DSP is in the stop state and BG will remain low.
5. During the WAIT mode the BR/BG circuits remain active.
6. Typical values at 5V are: at 20.5 MHz and WS=0,
Min =
tcl-4
at 20.5 MHz and WS>0,
Min = WS cyc+tcl-4
*
at 27
MHz and WS=0,
Min =
tcl-3
at 27
MHz and WS>0,
Min = WS cyc+tcl-3
*
at 33
MHz and WS=0,
Min =
tcl-2.5
at 33
MHz and WS>0,
Min = WS cyc+tcl-2.5
*
DSP56001
MOTOROLA
33
DSP56001 Electrical Characteristics
BR
115
116
BG
117
119
118
A0-A15, PS,
DS, X/Y,
RD, WR
D0-D23
Async. Bus Figure 1. Bus Request / Bus Grant Timing
A0-A15, DS,
PS, X/Y
(See Note 1)
126
127
131
129
134
133
136
RD
122
120
135
121
WR
132
130
123
128
125
D0-D23
124
DATA OUT
DATA
IN
Note:
1. During Read-Modify-Write instructions and internal instructions,
the address lines do not change state.
Async. Bus Figure 2. External Bus Asynchronous Timing
MOTOROLA
34
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - External Bus Synchronous Timing
Vcc = 5.0 Vdc + 10%; TJ = -40 to 105° C at 20.5 MHz 27 MHz
Vcc = 5.0 Vdc + 5%; TJ = -40 to 105° C at 33 MHz
Characteristics
Num
140
141
Clk Low Transition To Address Valid
Clk High Transition To WR
WS = 0
Assertion (see Note 2)
WS > 0
20.5 MHz
27 MHz
33 MHz
Unit
Min
Max
Min
Max
Min
Max
—
24
—
19
—
19
ns
0
0
19
tch+19
0
0
15
tch+15
0
0
17
tch+17
ns
ns
142
Clk High Transition To WR
Deassertion
5
21
5
16
5
13
ns
143
Clk High Transition To RD Assertion
0
19
0
15
0
16
ns
144
Clk High Transition To RD Deassertion
5
17
5
13
4.5
10.5
ns
145
Clk Low Transition To Data-Out Valid
—
25
—
19
—
19
ns
146
Clk Low Transition To Data-Out Invalid
(see Note 3)
5
—
4
—
3.5
—
ns
147
Data-In Valid To Clk High Transition
(Setup)
0
—
0
—
0
—
ns
148
Clk High Transition To Data-In Invalid
(Hold)
12
—
12
—
13
—
ns
ns
149
Clk Low To Address Invalid
(see Note 3)
3
—
3
—
3
—
ns
Notes:
1. AC timing specifications which are referenced to a device input signal are
measured in production with respect to the 50% point of the respective input
signal’s transition.
2. WS are wait state values specified in the BCR.
3. Clk low to data-out invalid (spec. 146) and Clk low to address invalid (spec.
149) indicate the time after which data/address are no longer guaranteed to
be valid.
DSP56001
MOTOROLA
35
DSP56001 Electrical Characteristics
T0
T1
T2
T3
T0
T1
T2
T3
T0
CLK in
A0-A15
DS,PS
X/Y
140
143
149
144
RD
141
142
WR
147
148
D0-D23
Data Out
145
Data In
146
Sync. Bus Figure 1. DSP56001 Synchronous Bus Timing
Note: During Read-Modify-Write Instructions, the address lines do not change states.
MOTOROLA
36
DSP56001
DSP56001 Electrical Characteristics
AC Electrical Characteristics - Bus Strobe / Wait Timing
Characteristics
Num
150
151
Clk Low Transition To BS Assertion
WT Assertion To Clk Low Transition
(setup time)
20.5 MHz
Min
Max
27 MHz
33 MHz
Min
Max
Unit
Min
Max
4
24
3
19
2.5
19
ns
4
—
3
—
2.5
—
ns
ns
152
Clk Low Transition To WT Deassertion
For Minimum Timing
14
cyc-8
11
cyc-6
12
cyc-5
ns
153
WT Deassertion To Clk Low Transition
For Maximum Timing (2 wait states
8
—
6
—
5
—
ns
154
Clk High Transition To BS Deassertion
5
26
4
20
3.5
19
ns
155
BS Assertion To Address Valid
-2
10
-2
8
-2
6.5
ns
156
BS Assertion To WT Assertion
(see Note 2)
0
cyc-15
0
cyc-11
0
cyc-10
ns
157
BS Assertion To WT Deassertion
(See Note 2 and Note 4)
WS < 2
WS> 2
cyc
(WS-1)
cyc
*
cyc+tcl
2*cyc-15
WS*cyc
-15
cyc
(WS-1)
cyc
*
cyc+tcl
2*cyc-11
WS*cyc
-11
cyc+4
(WS-1)
cyc+4
*
cyc+tcl
2*cyc-10
WS*cyc
-10
ns
ns
158
WT Deassertion To BS Deassertion
159
Minimum BS Deassertion Width For
Consecutive External Accesses
tch-7
160
BS Deassertion To Address Invalid
(see Note 3)
tch-10
161
Data-In Valid to RD Deassertion
(Set Up)
16
2 cyc+tcl
* +23
—
tch-6
2 cyc+tcl
* +17
—
tch-8
—
12
tch-4.5
2 cyc+tcl
* +15
ns
—
ns
—
ns
tch-6.5
—
10
Note:
1.
2.
3.
4.
5.
DSP56001
AC timing specifications which are referenced to a device input signal are measured in production with
respect to the 50% point of the respective input signal’s transition.
If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then
specification numbers 156 and 157 can be increased accordingly.
BS deassertion to address invalid indicates the time after which the address are no longer guaranteed
to be valid.
The minimum number of wait states when using BS/WT is two (2).
For read-modify-write instructions, the address lines will not change states between the read and the
write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are desired for each of the read and write cycle, the WT pin must be asserted once for each cycle.
MOTOROLA
37
DSP56001 Electrical Characteristics
T0
T1
T2
Tw
T2
Tw
T2
T3
T0
EXTAL
140
149
A0-A15,
PS, DS,
X/Y
154
150
BS
152
153
151
WT
143
144
RD
148
147
D0-D23
Data In
141
WR
142
145
D0-D23
146
Data Out
Bus Arbitration Figure 1. DSP56001 Synchronous BS / WT Timings
Note: During Read-Modify-Write Instructions, the address lines do not change state.
However, BS will deassert before asserting again for the write cycle.
MOTOROLA
38
DSP56001
DSP56001 Electrical Characteristics
A0-A15,
PS, DS,
X/Y
160
155
BS
159
157
158
156
WT
126
131
RD
128
161
D0-D23
Data In
120
122
WR
124
123
D0-D23
125
Data Out
Bus Arbitration Figure 2. DSP56001 Asynchronous BS / WT Timings
Note:
DSP56001
During Read-Modify-Write Instructions, the address lines will not change states.
However, BS will deassert before asserting again for the write cycle.
MOTOROLA
39
DSP56001 Electrical Characteristics
MOTOROLA
40
DSP56001
APPENDIX A
ORDERING INFORMATION
DSP56001FE 33
Frequency
20 = 20.5 MHz.
27 = 27 MHz
33 = 33 MHz.
Pack age Type
DSP Type
56001 = RAM Part
RC = Pin Grid Array
FE = Ceramic Quad
Flat Pack (CQFP)
FC = Plastic Quad
Flat Pack (PQFP)
DSP56001 SOCKET INFORMATION
PGA
Supplier
Telephone
Advanced Interconnections
(401) 823-5200
AMP
(717) 564-0100
Socket Type
Part Number
Comment
Standard 88 Pin
4CS088-01TG2
Includes Cutout in Center
Standard 88 Pin
1-916223-3
1-55283-9
1-55383-4
Low Insertion Force
ZIF Production
ZIF Burn-In and Test
PGA-088CM3P-S-TG3
PGA-088CHP3-SL-TG3
High Temp, Longer Leads
MVAS-120-ZSTT-131
CPAS-88-ZSTT-13BF1
Includes Cutout in Center
No Cutout
Standard 128 Pin
Robinson Nugent
(812) 945-0211
Custom Pinout
Samtec
(812) 944-6733
Standard 120 Pin
Custom 88 Pin
NOTES:
1. Please specify wirewrap and plating options. The part numbers shown specify low profile solder tail pins having a tin contact
and tin shell.
2. Please specify wirewrap and plating options. The part number shown specifies gold contact and tin shell.
3. Cutout in the center, unused holes are plugged, solder tail.
CQFP
Supplier
AMP
Telephone
Socket Type
Part Number
Comment
(717)564-0100
—
822054-21
Converts CQFP to fit AMP’s
132 position PQFP “Micro-Pitch
Socket”.
NOTES:
1. This part is not a socket. It is a converter that allows a CQFP part to be used in the PQFP socket described below.
PQFP
Supplier
AMP
Telephone
Socket Type
Part Number
Comment
(717)564-0100
132 Pin
821949-51
821942-11
Housing Sub-Assembly and
Cover for 132 position PQFP
“Micro-Pitch Socket”.
NOTES:
1. One housing sub-assembly and one cover are required for each socket.
DSP56001
MOTOROLA
A-41
PIN ASSIGNMENT
N
D0
A14
A13
D3
D1
A15
D4
D2
D6
D5
D8
D7
A12
A10
A8
A11
A7
A6
A4
A2
A9
A5
A3
GND
VCC
GND
A1
PS
X/Y
A0
DS
WR
RD
BR
BG
SC1
SRD
STD
M
L
K
J
GND
H
D9
SC2
BOTTOM VIEW
G
D10
VCC
GND
VCC
SCK
SC0
SCLK
F
D11
D12
E
D13
GND
TXD
D
D14
D16
D15
D18
D17
D20
GND
H0
RXD
H2
H1
H4
H3
C
VCC
VCC
B
D23
IRQA
EXTAL GND
HA0
HREQ H7
A
D19
D21
D22
IRQB
RESET XTAL
HA2
HA1
HACK
HEN
HR/W H6
H5
1
2
3
4
5
7
8
9
10
11
13
6
–T–
RC SUFFIX
CERAMIC
CASE 789D-01
12
–X–
K
G
N
M
L
K
J
H
G
F
E
D
C
B
A
–A–
G
1 2 3 4 5 6 7 8 9 10 11 12 13
–B–
C
D 88 PL
O 0.76 (0.030) O T A S B S MATRIX
O 0.25 (0.010) O X PINS
DIM
A
B
C
D
G
K
MILLIMETERS
MIN
MAX
34.04 35.05
34.04 35.05
2.16
3.04
0.44
0.55
2.54 BSC
4.20
5.08
INCHES
MIN
MAX
1.340 1.380
1.340 1.380
0.085 0.120
0.017 0.022
0.100 BSC
0.165 0.200
1.
DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M. 1982.
2.
CONTROLLING DIMENSION: INCH.
Mechanical Specification Figure A-1. Pin Grid Array Mechanical Specification
MOTOROLA
A-42
DSP56001
Mechanical Specification Table A-1. CQFP and PQFP Pin Out
PIN # FUNCTION
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
NO CONNECT
H4
H5
H6
PERIPHERAL VCC
PERIPHERAL VCC
H7
HREQ
HR/W
HEN
NO CONNECT
HACK
HA0
NO CONNECT
NO CONNECT
HA1
HA2
NO CONNECT
INTERNAL LOGIC GND
INTERNAL LOGIC GND
INTERNAL LOGIC VCC
INTERNAL LOGIC VCC
EXTAL
XTAL
NO CONNECT
RESET
MODA/IRQA
NO CONNECT
NMI/MODB/IRQB
D23
D22
D21
NO CONNECT
PIN # FUNCTION
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
NO CONNECT
D20
D19
D18
DATA BUS GND
DATA BUS GND
NO CONNECT
D17
D16
NO CONNECT
D15
D14
D13
NO CONNECT
D12
DATA BUS VCC
DATA BUS VCC
D11
NO CONNECT
D10
D9
NO CONNECT
D8
D7
D6
DATA BUS GND
DATA BUS GND
NO CONNECT
D5
D4
D3
D2
NO CONNECT
PIN # FUNCTION
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NO CONNECT
D1
D0
A15
A14
NO CONNECT
A13
A12
A11
ADDRESS BUS GND
ADDRESS BUS GND
NO CONNECT
A10
A9
NO CONNECT
A8
A7
NO CONNECT
A6
ADDRESS BUS VCC
ADDRESS BUS VCC
NO CONNECT
A5
A4
NO CONNECT
A3
A2
ADDRESS BUS GND
ADDRESS BUS GND
A1
A0
PS
NO CONNECT
PIN # FUNCTION
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NO CONNECT
DS
X/Y
RD
WR
BR
NO CONNECT
BG
SRD
NO CONNECT
SC1
STD
NO CONNECT
SC2
INTERNAL LOGIC VCC
INTERNAL LOGIC VCC
INTERNAL LOGIC GND
INTERNAL LOGIC GND
SCK
SC0
NO CONNECT
SCLK
TXD
RXD
NO CONNECT
H0
PERIPHERAL GND
PERIPHERAL GND
H1
NO CONNECT
H2
H3
NO CONNECT
Note: Do not connect to “NO CONNECT” pins.
“NO CONNECT” pins are reserved for future enhancements.
DSP56001
MOTOROLA
A-43
Mechanical Specification Figure A-2. Ceramic Quad Flat Pack
MOTOROLA
A-44
DSP56001
Mechanical Specification Figure A-2. Ceramic Quad Flat Pack (Continued)
DSP56001
MOTOROLA
A-45
Mechanical Specification Figure A-3. Plastic Quad Flat Pack
MOTOROLA
A-46
DSP56001
Mechanical Specification Figure A-3. Plastic Quad Flat Pack (Continued)
DSP56001
MOTOROLA
A-47
APPENDIX B
APPLICATION EXAMPLES
The lowest cost DSP56001 based system is shown in Figure B1. It uses no run time external memory and requires only two
chips, the DSP56001 and a low cost EPROM. The EPROM read
access time should be less than 780 nanoseconds when the
DSP56001 is operating at a clock rate of 20.5 MHz.
+5 V
+5 V
Note: When in RESET,
IRQA and IRQB must
be deasserted by external
peripherals.
15K
A system with external data RAM memory requires no glue logic
to select the external EPROM from bootstrap mode. PS is used
to enable the EPROM and DS is used to enable the high speed
data memories as shown in Figure B-2.
15K
15K
+5 V
+5 V
15K
15K
15K
DSP56001
BR
D23
FROM OPEN
COLLECTOR
BUFFER
MODA/IRQA
HACK
2716
PS
CE
MBD301*
11
A0-A10
FROM
RESET
FUNCTION
RESET
8
D0-D7
A0-A10
D0-D7
MBD301*
Note *: These diodes must be Schottky diodes.
FROM OPEN
COLLECTOR
BUFFER
MODB/IRQB
Figure B-1. No Glue Logic, Low Cost Memory Port Bootstrap — Mode 1
+5 V
15K
15K
15K
15K
15K
BR
DSP56001 RD
HACK
FROM OPEN
COLLECTOR
BUFFER
MODA/IRQA
WR
DS
X/Y
11
A0-A10
PS
10
MBD301*
FROM
RESET
FUNCTION
A0-A9 A10 CS WE OE
CE
RESET
A0-A10
2018-55 (3)
2716
MBD301*
D0-D7
D0-D23
+5 V
FROM OPEN
COLLECTOR
BUFFER
8
15K
MODB/IRQB
24
D23
D0-D23
Note *: These diodes must be Schottky diodes.
Figure B-2. Port A Bootstrap with External Data RAM — Mode 1
MOTOROLA
B-48
DSP56001
Figure B-3 shows the DSP56001 bootstrapping via the Host Port
from an MC68000.
DSP56001 is operated in mode 2 with external program memory
at location $E000. The programmer can overlay the high speed
on-chip PRAM with DSP algorithms by using the MOVEM instruction.
Systems with external program memory can load the on-chip
PRAM without using the bootstrap mode. In Figure B-4, the
+5 V
15K
15K
15K
15K
15K
BR
DSP56001
HACK
FROM OPEN
COLLECTOR
BUFFER
HEN
LDS
F32
MODA/IRQA
AS
F32
ADDRESS
DECODE
A4-A23
MBD301*
MC68000
+5 V
FROM
RESET
FUNCTION
(12.5MHz)
1K
RESET
LS09
DTACK
MBD301*
F32
HR/W
FROM OPEN
COLLECTOR
BUFFER
MODB/IRQB
15K
D0-D7
3
A1-A3
Note *: These diodes must be Schottky diodes.
Figure B-3. DSP56001 Host Bootstrap Example — Mode 1
+5 V
15K
8
H0-H7
HA0-HA2
D23
R/W
F32
15K
15K
DSP56001 RD
FROM OPEN
COLLECTOR
BUFFER
MODA/IRQA
PS
15
A0-A14
+5V
MBD301*
A0-A14
FROM
RESET
FUNCTION
RESET
HACK
2756-30 (3)
+5V
MBD301*
FROM OPEN
COLLECTOR
BUFFER
CS
15 ΚΩ
D0-D23
15 ΚΩ
MODB/IRQB
BR
D0-D23
24
Note *: These diodes must be Schottky diodes.
Figure B-4. 32K Words of External Program ROM — Mode 2
DSP56001
MOTOROLA
B-49
OE
Figure B-5 shows an alternative clock oscillator circuit used in
the Graphic Equalizer application note (APR2). The 330Ω resistor provides additional current limiting in the crystal. Figure B-6
shows a circuit which waits until Vcc on the DSP is at least 4.5 V
before initiating a 3.75 ms minimum (150,000T) oscillator stabilization delay required for the on-chip oscillator (only 50T is required for an external oscillator). This insures that the DSP is operational and stable before releasing the reset signal.
330 Ω
470KΩ
•
•
XTAL
EXTAL
•
•
10 pf
10 pf
20.5
MHz
Figure B-5. Alternative Clock Circuit from the Graphic Equalizer (APR2)
+5V
•
R
RESET
1 (1)
2 (2)
•
•
•
•
•
•
CDLY
MC34064
MC33064
•
+
1.2 Vref
•
•
1
U1
tDLY = RCDLY In
Vth
1-
Vin - Vol
•
3 (4)
Where:
tDLY = 150,000T min.
Vin = 5 V
LOGIC
RESET
R = 8.2K + 5%
fosc = 20.5 MHz
Vth = 2.5 V
Vol = 0.4 V
CDLY = 1 µf + 20%
T = 25 ns
Notes: 1. IRQA and IRQB must
be hardwired.
2. MODA and MODB
must be hard wired.
Figure B-6. Reset Circuit Using MC34064/MC33064
MOTOROLA
B-50
DSP56001
Figure 7 illustrates how to connect a 20 ns static RAM with a 33
MHz. DSP56001. The important parameters are TDW < 10 ns,
TDOE < 10 ns, and TAA = 20 ns maximum. A 7.5 ns PLD is used
to minimize decoding delays. This example maps the static RAM
into the ranges X:$1000-1FFF and Y:$1000-1FFF. The PLD
equation is:
RAM_ENABLE = PS & !DS & !A15 & !A14 & !A13 & !A12
MCM6264D
(8K X 8) 20 ns
DSP56001
27 MHZ
DATA
ADDRESS
DS
PS
DATA
16L8-7
7.5ns PLD
4
A12
5
A13
6
A14
7
A15
8
DS
9
PS
ADDRESS
RAM_ENABLE
12
E
RD
OE
WR
WR
CS
Figure B-7. 27 MHz DSP56001 with 20 ns SRAM
DSP56001
MOTOROLA
B-51
Figure B-8 shows the DSP56001 connected to the bus of an
IBM-PC computer. The PAL equations and other details of this
circuit are available in “An ISA BUS INTERFACE FOR THE
DSP56001” which is provided on request by the Motorola DSP
Marketing Department (512-891-2030).
NOTE:
CONNECTOR is J1 of ISA BUS
All Series Resistors 15K OHMS
IRQA
IRQB
+5v
1
2
23
L13
3
13
B10
A9
4
PAL22V10
B30
A27
A26
A25
A24
A23
A22
A17
A11
B14
B13
OSC
A04
A05
A06
A07
A08
A09
A14
AEN
IOR
IOW
5
6
7
8
9
17
A10
16
A11
21
A5
11
19
A31
A30
A29
A00
A01
A02
RESET
15
11
12
13
14
15
16
17
18
D23
DSP56001
1
DIR
MC74ACT245
OE
D07
D06
D05
D04
D03
D02
D01
D00
HEN
22
B4
A02
A03
A04
A05
A06
A07
A08
A09
HREQ
HACK
HR/W
B5
MODA/IRQA
A4
MODB/IRQB
14
10
BR
9
B11
8
A12
7
6
5
4
H7
H6
A13 H5
B12 H4
B13 H3
3
C12 H2
C13 H1
2
D12
H0
B8
HA0
A8 HA1
A7
HA2
Figure B-8. DSP56001-to-ISA Bus Interface Schematic
MOTOROLA
B-52
DSP56001
APPENDIX C
MU-LAW / A-LAW EXPANSION TABLES
;
M_00
M_01
M_02
M_03
M_04
M_05
M_06
M_07
M_08
M_09
M_0A
M_0B
M_0C
M_0D
M_0E
M_0F
M_10
M_11
M_12
M_13
M_14
M_15
M_16
M_17
M_18
M_19
M_1A
M_1B
M_1C
M_1D
M_1E
M_1F
M_20
M_21
M_22
M_23
M_24
M_25
M_26
M_27
M_28
M_29
M_2A
M_2B
M_2C
M_2D
M_2E
M_2F
M_30
M_31
M_32
M_33
M_34
M_35
M_36
M_37
M_38
M_39
M_3A
M_3B
M_3C
M_3D
M_3E
ORG
X:$100
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$7D7C00
$797C00
$757C00
$717C00
$6D7C00
$697C00
$657C00
$617C00
$5D7C00
$597C00
$557C00
$517C00
$4D7C00
$497C00
$457C00
$417C00
$3E7C00
$3C7C00
$3A7C00
$387C00
$367C00
$347C00
$327C00
$307C00
$2E7C00
$2C7C00
$2A7C00
$287C00
$267C00
$247C00
$227C00
$207C00
$1EFC00
$1DFC00
$1CFC00
$1BFC00
$1AFC00
$19FC00
$18FC00
$17FC00
$16FC00
$15FC00
$14FC00
$13FC00
$12FC00
$11FC00
$10FC00
$0FFC00
$0F3C00
$0EBC00
$0E3C00
$0DBC00
$0D3C00
$0CBC00
$0C3C00
$0BBC00
$0B3C00
$0ABC00
$0A3C00
$09BC00
$093C00
$08BC00
$083C00
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
8031
7775
7519
7263
7007
6751
6495
6239
5983
5727
5471
5215
4959
4703
4447
4191
3999
3871
3743
3615
3487
3359
3231
3103
2975
2847
2719
2591
2463
2335
2207
2079
1983
1919
1855
1791
1727
1663
1599
1535
1471
1407
1343
1279
1215
1151
1087
1023
975
943
911
879
847
815
783
751
719
687
655
623
591
559
527
M_3F
M_40
M_41
M_42
M_43
M_44
M_45
M_46
M_47
M_48
M_49
M_4A
M_4B
M_4C
M_4D
M_4E
M_4F
M_50
M_51
M_52
M_53
M_54
M_55
M_56
M_57
M_58
M_59
M_5A
M_5B
M_5C
M_5D
M_5E
M_5F
M_60
M_61
M_62
M_63
M_64
M_65
M_66
M_67
M_68
M_69
M_6A
M_6B
M_6C
M_6D
M_6E
M_6F
M_70
M_71
M_72
M_73
M_74
M_75
M_76
M_77
M_78
M_79
M_7A
M_7B
M_7C
M_7D
M_7E
M_7F
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$07BC00
$075C00
$071C00
$06DC00
$069C00
$065C00
$061C00
$05DC00
$059C00
$055C00
$051C00
$04DC00
$049C00
$045C00
$041C00
$03DC00
$039C00
$036C00
$034C00
$032C00
$030C00
$02EC00
$02CC00
$02AC00
$028C00
$026C00
$024C00
$022C00
$020C00
$01EC00
$01CC00
$01AC00
$018C00
$017400
$016400
$015400
$014400
$013400
$012400
$011400
$010400
$00F400
$00E400
$00D400
$00C400
$00B400
$00A400
$009400
$008400
$007800
$007000
$006800
$006000
$005800
$005000
$004800
$004000
$003800
$003000
$002800
$002000
$001800
$001000
$000800
$000000
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
495
471
455
439
423
407
391
375
359
343
327
311
295
279
263
247
231
219
211
203
195
187
179
171
163
155
147
139
131
123
115
107
99
93
89
85
81
77
73
69
65
61
57
53
49
45
41
37
33
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
Figure C-1. Mu-Law/A-Law Expansion Table Contents (Sheet 1 of 2)
DSP56001
MOTOROLA
C-53
A_80
A_81
A_82
A_83
A_84
A_85
A_86
A_87
A_88
A_89
A_8A
A_8B
A_8C
A_8D
A_8E
A_8F
A_90
A_91
A_92
A_93
A_94
A_95
A_96
A_97
A_98
A_99
A_9A
A_9B
A_9C
A_9D
A_9E
A_9F
A_A0
A_A1
A_A2
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_AA
A_AB
A_AC
A_AD
A_AE
A_AF
A_B0
A_B1
A_B2
A_B3
A_B4
A_B5
A_B6
A_B7
A_B8
A_B9
A_BA
A_BB
A_BC
A_BD
A_BE
A_BF
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$158000
$148000
$178000
$168000
$118000
$108000
$138000
$128000
$1D8000
$1C8000
$1F8000
$1E8000
$198000
$188000
$1B8000
$1A8000
$0AC000
$0A4000
$0BC000
$0B4000
$08C000
$084000
$09C000
$094000
$0EC000
$0E4000
$0FC000
$0F4000
$0CC000
$0C4000
$0DC000
$0D4000
$560000
$520000
$5E0000
$5A0000
$460000
$420000
$4E0000
$4A0000
$760000
$720000
$7E0000
$7A0000
$660000
$620000
$6E0000
$6A0000
$2B0000
$290000
$2F0000
$2D0000
$230000
$210000
$270000
$250000
$3B0000
$390000
$3F0000
$3D0000
$330000
$310000
$370000
$350000
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
688
656
752
720
560
528
624
592
944
912
1008
976
816
784
880
848
344
328
376
360
280
264
312
296
472
456
504
488
408
392
440
424
2752
2624
3008
2880
2240
2112
2496
2368
3776
3648
4032
3904
3264
3136
3520
3392
1376
1312
1504
1440
1120
1056
1248
1184
1888
1824
2016
1952
1632
1568
1760
1696
A_C0
A_C1
A_C2
A_C3
A_C4
A_C5
A_C6
A_C7
A_C8
A_C9
A_CA
A_CB
A_CC
A_CD
A_CE
A_CF
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_DA
A_DB
A_DC
A_DD
A_DE
A_DF
A_E0
A_E1
A_E2
A_E3
A_E4
A_E5
A_E6
A_E7
A_E8
A_E9
A_EA
A_EB
A_EC
A_ED
A_EE
A_EF
A_F0
A_F1
A_F2
A_F3
A_F4
A_F5
A_F6
A_F7
A_F8
A_F9
A_FA
A_FB
A_FC
A_FD
A_FE
A_FF
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$015800
$014800
$017800
$016800
$011800
$010800
$013800
$012800
$01D800
$01C800
$01F800
$01E800
$019800
$018800
$01B800
$01A800
$005800
$004800
$007800
$006800
$001800
$000800
$003800
$002800
$00D800
$00C800
$00F800
$00E800
$009800
$008800
$00B800
$00A800
$056000
$052000
$05E000
$05A000
$046000
$042000
$04E000
$04A000
$076000
$072000
$07E000
$07A000
$066000
$062000
$06E000
$06A000
$02B000
$029000
$02F000
$02D000
$023000
$021000
$027000
$025000
$03B000
$039000
$03F000
$03D000
$033000
$031000
$037000
$035000
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
43
41
47
45
35
33
39
37
59
57
63
61
51
49
55
53
11
9
15
13
3
1
7
5
27
25
31
29
19
17
23
21
172
164
188
180
140
132
156
148
236
228
252
244
204
196
220
212
86
82
94
90
70
66
78
74
118
114
126
122
102
98
110
106
Figure C-1. Mu-Law/A-Law Expansion Table Contents (Sheet 2 of 2)
MOTOROLA
C-54
DSP56001
APPENDIX D
SINE WAVE TABLE
This sine wave table is normally used by FFT routines which use bit reversed address pointers. This table can be used as it is for up
to 512 point FFTs; however, for larger FFTs, the table must be copied to a different memory location to allow the reverse-carry addressing mode to be used (see Section 5.3.2.3 REVERSE-CARRY MODIFIER (Mn=$0000) in the DSP56000/DSP56001 Digital Signal
Processor User’s Manual for additional information).
;
S_00
S_01
S_02
S_03
S_04
S_05
S_06
S_07
S_08
S_09
S_0A
S_0B
S_0C
S_0D
S_0E
S_0F
S_10
S_11
S_12
S_13
S_14
S_15
S_16
S_17
S_18
S_19
S_1A
S_1B
S_1C
S_1D
S_1E
S_1F
S_20
S_21
S_22
S_23
S_24
S_25
S_26
S_27
S_28
S_29
S_2A
S_2B
S_2C
S_2D
S_2E
S_2F
S_30
S_31
S_32
S_33
S_34
S_35
S_36
S_37
ORG
Y:$100
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$000000
$03242B
$0647D9
$096A90
$0C8BD3
$0FAB27
$12C810
$15E214
$18F8B8
$1C0B82
$1F19F9
$2223A5
$25280C
$2826B9
$2B1F35
$2E110A
$30FBC5
$33DEF3
$36BA20
$398CDD
$3C56BA
$3F174A
$41CE1E
$447ACD
$471CED
$49B415
$4C3FE0
$4EBFE9
$5133CD
$539B2B
$55F5A5
$5842DD
$5A827A
$5CB421
$5ED77D
$60EC38
$62F202
$64E889
$66CF81
$68A69F
$6A6D99
$6C2429
$6DCA0D
$6F5F03
$70E2CC
$72552D
$73B5EC
$7504D3
$7641AF
$776C4F
$788484
$798A24
$7A7D05
$7B5D04
$7C29FC
$7CE3CF
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
+0.0000000000
+0.0245412998
+0.0490676016
+0.0735644996
+0.0980170965
+0.1224106997
+0.1467303932
+0.1709619015
+0.1950902939
+0.2191012055
+0.2429800928
+0.2667128146
+0.2902846038
+0.3136816919
+0.3368898928
+0.3598949909
+0.3826833963
+0.4052414000
+0.4275551140
+0.4496113062
+0.4713967144
+0.4928981960
+0.5141026974
+0.5349975824
+0.5555701852
+0.5758082271
+0.5956993103
+0.6152315736
+0.6343932748
+0.6531729102
+0.6715589762
+0.6895405054
+0.7071068287
+0.7242470980
+0.7409511805
+0.7572088242
+0.7730104923
+0.7883464098
+0.8032075167
+0.8175848722
+0.8314697146
+0.8448535204
+0.8577286005
+0.8700870275
+0.8819212914
+0.8932244182
+0.9039893150
+0.9142097235
+0.9238795042
+0.9329928160
+0.9415441155
+0.9495282173
+0.9569402933
+0.9637761116
+0.9700313210
+0.9757022262
S_38
S_39
S_3A
S_3B
S_3C
S_3D
S_3E
S_3F
S_40
S_41
S_42
S_43
S_44
S_45
S_46
S_47
S_48
S_49
S_4A
S_4B
S_4C
S_4D
S_4E
S_4F
S_50
S_51
S_52
S_53
S_54
S_55
S_56
S_57
S_58
S_59
S_5A
S_5B
S_5C
S_5D
S_5E
S_5F
S_60
S_61
S_62
S_63
S_64
S_65
S_66
S_67
S_68
S_69
S_6A
S_6B
S_6C
S_6D
S_6E
S_6F
S_70
S_71
S_72
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$7D8A5F
$7E1D94
$7E9D56
$7F0992
$7F6237
$7FA737
$7FD888
$7FF622
$7FFFFF
$7FF622
$7FD888
$7FA737
$7F6237
$7F0992
$7E9D56
$7E1D94
$7D8A5F
$7CE3CF
$7C29FC
$7B5D04
$7A7D05
$798A24
$788484
$776C4F
$7641AF
$7504D3
$73B5EC
$72552D
$70E2CC
$6F5F03
$6DCA0D
$6C2429
$6A6D99
$68A69F
$66CF81
$64E889
$62F202
$60EC38
$5ED77D
$5CB421
$5A827A
$5842DD
$55F5A5
$539B2B
$5133CD
$4EBFE9
$4C3FE0
$49B415
$471CED
$447ACD
$41CE1E
$3F174A
$3C56BA
$398CDD
$36BA20
$33DEF3
$30FBC5
$2E110A
$2B1F35
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
+0.9807853103
+0.9852777123
+0.9891765118
+0.9924796224
+0.9951847792
+0.9972904921
+0.9987955093
+0.9996988773
+0.9999998808
+0.9996988773
+0.9987955093
+0.9972904921
+0.9951847792
+0.9924796224
+0.9891765118
+0.9852777123
+0.9807853103
+0.9757022262
+0.9700313210
+0.9637761116
+0.9569402933
+0.9495282173
+0.9415441155
+0.9329928160
+0.9238795042
+0.9142097235
+0.9039893150
+0.8932244182
+0.8819212914
+0.8700870275
+0.8577286005
+0.8448535204
+0.8314697146
+0.8175848722
+0.8032075167
+0.7883464098
+0.7730104923
+0.7572088242
+0.7409511805
+0.7242470980
+0.7071068287
+0.6895405054
+0.6715589762
+0.6531729102
+0.6343932748
+0.6152315736
+0.5956993103
+0.5758082271
+0.5555701852
+0.5349975824
+0.5141026974
+0.4928981960
+0.4713967144
+0.4496113062
+0.4275551140
+0.4052414000
+0.3826833963
+0.3598949909
+0.3368898928
Figure D-1. Sine Wave Table Contents (Sheet 1 of 3)
DSP56001
MOTOROLA
D-55
S_73
S_74
S_75
S_76
S_77
S_78
S_79
S_7A
S_7B
S_7C
S_7D
S_7E
S_7F
S_80
S_81
S_82
S_83
S_84
S_85
S_86
S_87
S_88
S_89
S_8A
S_8B
S_8C
S_8D
S_8E
S_8F
S_90
S_91
S_92
S_93
S_94
S_95
S_96
S_97
S_98
S_99
S_9A
S_9B
S_9C
S_9D
S_9E
S_9F
S_A0
S_A1
S_A2
S_A3
S_A4
S_A5
S_A6
S_A7
S_A8
S_A9
S_AA
S_AB
S_AC
S_AD
S_AE
S_AF
S_B0
S_B1
S_B2
S_B3
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$2826B9
$25280C
$2223A5
$1F19F9
$1C0B82
$18F8B8
$15E214
$12C810
$0FAB27
$0C8BD3
$096A90
$0647D9
$03242B
$000000
$FCDBD5
$F9B827
$F69570
$F3742D
$F054D9
$ED37F0
$EA1DEC
$E70748
$E3F47E
$E0E607
$DDDC5B
$DAD7F4
$D7D947
$D4E0CB
$D1EEF6
$CF043B
$CC210D
$C945E0
$C67323
$C3A946
$C0E8B6
$BE31E2
$BB8533
$B8E313
$B64BEB
$B3C020
$B14017
$AECC33
$AC64D5
$AA0A5B
$A7BD23
$A57D86
$A34BDF
$A12883
$9F13C8
$9D0DFE
$9B1777
$99307F
$975961
$959267
$93DBD7
$9235F3
$90A0FD
$8F1D34
$8DAAD3
$8C4A14
$8AFB2D
$89BE51
$8893B1
$877B7C
$8675DC
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
+0.3136816919
+0.2902846038
+0.2667128146
+0.2429800928
+0.2191012055
+0.1950902939
+0.1709619015
+0.1467303932
+0.1224106997
+0.0980170965
+0.0735644996
+0.0490676016
+0.0245412998
+0.0000000000
-0.0245412998
-0.0490676016
-0.0735644996
-0.0980170965
-0.1224106997
-0.1467303932
-0.1709619015
-0.1950902939
-0.2191012055
-0.2429800928
-0.2667128146
-0.2902846038
-0.3136816919
-0.3368898928
-0.3598949909
-0.3826833963
-0.4052414000
-0.4275551140
-0.4496113062
-0.4713967144
-0.4928981960
-0.5141026974
-0.5349975824
-0.5555701852
-0.5758082271
-0.5956993103
-0.6152315736
-0.6343932748
-0.6531729102
-0.6715589762
-0.6895405054
-0.7071068287
-0.7242470980
-0.7409511805
-0.7572088242
-0.7730104923
-0.7883464098
-0.8032075167
-0.8175848722
-0.8314697146
-0.8448535204
-0.8577286005
-0.8700870275
-0.8819212914
-0.8932244182
-0.9039893150
-0.9142097235
-0.9238795042
-0.9329928160
-0.9415441155
-0.9495282173
S_B4
S_B5
S_B6
S_B7
S_B8
S_B9
S_BA
S_BB
S_BC
S_BD
S_BE
S_BF
S_C0
S_C1
S_C2
S_C3
S_C4
S_C5
S_C6
S_C7
S_C8
S_C9
S_CA
S_CB
S_CC
S_CD
S_CE
S_CF
S_D0
S_D1
S_D2
S_D3
S_D4
S_D5
S_D6
S_D7
S_D8
S_D9
S_DA
S_DB
S_DC
S_DD
S_DE
S_DF
S_E0
S_E1
S_E2
S_E3
S_E4
S_E5
S_E6
S_E7
S_E8
S_E9
S_EA
S_EB
S_EC
S_ED
S_EE
S_EF
S_F0
S_F1
S_F2
S_F3
S_F4
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
$8582FB
$84A2FC
$83D604
$831C31
$8275A1
$81E26C
$8162AA
$80F66E
$809DC9
$8058C9
$802778
$8009DE
$800000
$8009DE
$802778
$8058C9
$809DC9
$80F66E
$8162AA
$81E26C
$8275A1
$831C31
$83D604
$84A2FC
$8582FB
$8675DC
$877B7C
$8893B1
$89BE51
$8AFB2D
$8C4A14
$8DAAD3
$8F1D34
$90A0FD
$9235F3
$93DBD7
$959267
$975961
$99307F
$9B1777
$9D0DFE
$9F13C8
$A12883
$A34BDF
$A57D86
$A7BD23
$AA0A5B
$AC64D5
$AECC33
$B14017
$B3C020
$B64BEB
$B8E313
$BB8533
$BE31E2
$C0E8B6
$C3A946
$C67323
$C945E0
$CC210D
$CF043B
$D1EEF6
$D4E0CB
$D7D947
$DAD7F4
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
-0.9569402933
-0.9637761116
-0.9700313210
-0.9757022262
-0.9807853103
-0.9852777123
-0.9891765118
-0.9924796224
-0.9951847792
-0.9972904921
-0.9987955093
-0.9996988773
-1.0000000000
-0.9996988773
-0.9987955093
-0.9972904921
-0.9951847792
-0.9924796224
-0.9891765118
-0.9852777123
-0.9807853103
-0.9757022262
-0.9700313210
-0.9637761116
-0.9569402933
-0.9495282173
-0.9415441155
-0.9329928160
-0.9238795042
-0.9142097235
-0.9039893150
-0.8932244182
-0.8819212914
-0.8700870275
-0.8577286005
-0.8448535204
-0.8314697146
-0.8175848722
-0.8032075167
-0.7883464098
-0.7730104923
-0.7572088242
-0.7409511805
-0.7242470980
-0.7071068287
-0.6895405054
-0.6715589762
-0.6531729102
-0.6343932748
-0.6152315736
-0.5956993103
-0.5758082271
-0.5555701852
-0.5349975824
-0.5141026974
-0.4928981960
-0.4713967144
-0.4496113062
-0.4275551140
-0.4052414000
-0.3826833963
-0.3598949909
-0.3368898928
-0.3136816919
-0.2902846038
Figure D-1. Sine Wave Table Contents (Sheet 2 of 3)
MOTOROLA
D-56
DSP56001
S_F5
S_F6
S_F7
S_F8
S_F9
S_FA
DC
DC
DC
DC
DC
DC
$DDDC5B
$E0E607
$E3F47E
$E70748
$EA1DEC
$ED37F0
;
;
;
;
;
;
-0.2667128146
-0.2429800928
-0.2191012055
-0.1950902939
-0.1709619015
-0.1467303932
S_FB
S_FC
S_FD
S_FE
S_FF
DC
DC
DC
DC
DC
$F054D9
$F3742D
$F69570
$F9B827
$FCDBD5
;
;
;
;
;
-0.1224106997
-0.0980170965
-0.0735644996
-0.0490676016
-0.0245412998
Figure D-1. Sine Wave Table Contents (Sheet 3 of 3)
DSP56001
MOTOROLA
D-57
APPENDIX E
BOOTSTRAP MODE — OPERATING MODE 1
The bootstrap feature of the DSP56001 consists of four special
on-chip modules: the 512 words of PRAM, a 32-word bootstrap
ROM, the bootstrap control logic, and the bootstrap firmware
program.
BOOTSTRAP ROM
This 32-word on-chip ROM has been factory programmed to perform the actual bootstrap operation from the memory expansion
port (Port A) or from the Host Interface. You have no access to
the bootstrap ROM other than through the bootstrap process.
Control logic will disable the bootstrap ROM during normal operations.
BOOTSTRAP CONTROL LOGIC
The bootstrap mode control logic is activated when the
DSP56001 is placed in Operating Mode 1. The control logic
maps the bootstrap ROM into program memory space as long as
the DSP56001 remains in Operating Mode 1. The bootstrap firmware changes operating modes when the bootstrap load is completed. When the DSP56001 exits the reset state in Mode 1, the
following actions occur.
1.
2.
3.
4.
The control logic maps the bootstrap ROM into the internal DSP program memory space starting at location
$0000. This P: space is read-only.
The control logic forces the entire P: space to be writeonly memory during the bootstrap loading process. Attempts to read from this space will result in fetches from
the read-only bootstrap ROM.
Program execution begins at location $0000 in the bootstrap ROM. The bootstrap ROM program is able to perform the PRAM load through either the memory expansion port from a byte-wide external memory, or through
the Host Interface.
The bootstrap ROM program executes the following sequence to end the bootstrap operation and begin your
program execution.
A. Enter Operating Mode 2 by writing to the OMR.
through the Host Interface. The particular method used is selected by the level of program memory location $C000, bit 23. If location P:$C000, bit 23 is read as a one, the external bus version
of the bootstrap program will be selected. Typically, a byte wide
EPROM will be connected to the DSP56001 Address and Data
Bus as shown in Figure B-1 of the applications examples given
in APPENDIX B APPLICATIONS EXAMPLES. The data contents of the EPROM must be organized as shown below.
Address of External
Byte Wide P Memory
P:$C000
Contents Loaded
to Internal PRAM at:
P:$0000 low byte
P:$C001
P:$0000 mid byte
P:$C002
P:$0000 high byte
•
•
•
•
•
•
P:$C5FD
P:$01FF low byte
P:$C5FE
P:$01FF mid byte
P:$C5FF
P:$01FF high byte
If location P:$C000, bit 23 is read as a zero, the Host Interface
version of the bootstrap program will be selected. Typically a
host microprocessor will be connected to the DSP56001 Host Interface. The host microprocessor must write the Host Interface
registers THX, TXM, and then TSL with the desired contents of
PRAM from location P:$0000 up to P:$01FF. If less than 512
words are to be loaded, the host programmer can exit the bootstrap program and force the DSP56001 to begin executing at location P:$0000 by setting HF0=1 in the Host Interface during the
bootstrap load. In most systems, the DSP56001 responds so
fast that handshaking between the DSP56001 and the host is not
necessary.
The bootstrap program is shown in flowchart form in Figure E-1
and in assembler listing format in Figure E-2.
This action will be timed to remove the bootstrap
ROM from the program memory map and re-enable read/write access to the PRAM.
B.
The change to Mode 2 is timed exactly to allow
the boot program to execute a single cycle instruction then a JMP #00 and begin execution of
the program at location $0000.
You may also select the bootstrap mode by writing Operating
Mode 1 into the OMR. This initiates a timed operation to map the
bootstrap ROM into the program address space after a delay to
allow execution of a single cycle instruction and then a JMP
#<00 (e.g., see Bootstrap code for DSP56001) to begin the bootstrap process as described above in steps 1-4. This technique
allows the DSP56001 user to reboot the system (with a different
program if desired).
BOOTSTRAP FIRMWARE PROGRAM
Bootstrap ROM contains the bootstrap firmware program that
performs initial loading of the DSP56001 PRAM. The program is
written in DSP56000/DSP56001 assembly language. It contains
two separate methods of initializing the PRAM: loading from a
byte-wide memory starting at location P:$C000 or loading
MOTOROLA
E-58
DSP56001
START
IS
L FLAG
=0?
INITIALIZE ADDRESS
REGISTERS
R0=0
R1=$C000
R2=$FFE9
N
HOST
INTERFACE
CONTINUE
LOADING
Y
Y
N
SHIFT 8 BITS
FROM A3 INTO
ACCUMULATOR
A1’S 8 MSBS
SET L FLAG = 1
(INDICATES A BOOT
FROM EXTERNAL
MEMORY WAS
SELECTED)
FINISHED
3 LOOPS?
START DO
LOOP, 512
ITERATIONS
N
ENDDO
STOP BOOT
LOAD
IS THE
HOST RECEIVE
FLAG = 0?
WAIT FOR
HOST TO FILL
INPUT REGISTER
EXTERNAL
MEMORY
N
IS
HOST FLAG 0
=0?
GET 8-BIT DATA
FROM P MEMORY
PUT I N A2,
INCREMENT R1
Y
ENABLE
HOST INTERFACE
LOGIC
LOAD FROM
EXTERNAL
MEMORY
DO 3 TIMES
(GET 8-BIT DATA
AND SHIFT INTO
24-BIT WORD)
GET P:$C000 BIT 23
AND PUT IT IN THE
CARRY FLAG
WAS
P:$C000 BIT 23
=0?
LOAD FROM
HOST
INTERFACE
Y
DATA AVAILABLE
PUT DATA FROM
HOST RECEIVE
DATA REGISTER
INTO
ACCUMULATOR A1
N
REPEAT UNTIL
24-BIT DATA IS IN A1
Y
MOVE A1 INTO
NEXT INTERNAL
P MEMORY LOCATION.
INCREMENT R0
POINTER.
REPEAT UNTIL
512 PROGRAM WORDS
HAVE BEEN LOADED
N
FINISHED
512 LOOPS?
Y
SET OPERATING
MODE TO
MODE 2
CLEAR
STATUS
REGISTER
JUMP TO P:0
Figure E-1. Bootstrap Program Flowchart
DSP56001
MOTOROLA
E-59
Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page 1
1
PAGE 132,50,0,10
2
; BOOTSTRAP SOURCE CODE FOR DSP56001 - (C) Copyright 1986 Motorola Inc.
4
; Host algorithm / AND / external bus method
6
; This is the Bootstrap source code contained in the DSP56001 32 word boot ROM.
7
; This program can load the internal program memory from one of two external sources.
8
; The program reads P:$C000 bit 23 to decide which external source to access. If
9
; P:$C000 bit 23 = 0 then it loads internal PRAM from H0-H7, using the Host Interface
10
; logic. If P:$C000 bit 23 = 1 then it loads from 1,536 consecutive byte-wide P:
11
; memory locations (starting at P:$C000).
13
0000C000
BOOT
EQU
$C000
; The location in P: memory
14
; where the external byte-wide
15
; EPROM is expected to be mapped.
16
17
p:0000
ORG
PL:$0
; Bootstrap code starts at P:$0
18
19
P:0000
62F400
START
MOVE
#$FFE9,R2
; R2 = address of the Host
MOVE
#BOOT,R1
; R1 = starting P: address of
MOVE
#0,R0
00FFE9
20
21
; Interface status register.
P:0002
61F400
00C000
22
23
; external bootstrap byte-wide ROM.
P:0004
300000
; R0 = starting P: address of
24
; internal memory where program
25
; will begin loading.
26
27
P:0005
07E18C
MOVE
28
P:0006
200037
ROL
A
29
P:0007
0E0009
JCC
<INLOOP
30
P:(R1),Al
; Get the data at P:$C000
; Shift bit 23 into the Carry flag
; Perform load from Host Interface
; if carry is zero.
31
32
; IMPORTANT NOTE: This routine assumes that the L bit has been cleared before entering
33
; this program and that M0 and M1 have been preloaded with $FFFF (linear addressing).
34
; This would be the case after a reset. If this program is entered by changing the OMR
Figure E-2. Assembler Listing for Bootstrap Program (Sheet 1 of 3)
MOTOROLA
E-60
DSP56001
Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page 2
35
; to bootstrap operating mode, make certain that the L bit is cleared and registers M0
36
; and M1have been set to $FFFF. Also, make sure the BCR is set to $xxFx since
37
; EPROMS are slow and BCR is set to $FFFF after a reset. If the L bit was set before
38
; changing modes, the program will load from external program memory.
39
40
P:0008
0040F9
ORI
#$40,CCR
; Set the L bit to indicate
41
; that the bootstrap program
42
; is being loaded from the
43
; external P: space.
44
45
; The first routine will load 1,536 bytes from the external P: memory space beginning
46
; at P:$C000 (bits 7-0). These will be packed into 512 24-bit words and stored in
47
; contiguous internal PRAM memory locations starting at P:$0.
48
49
; The shifter moves the 8-bit input data from register A2 into register A1 eight bits
50
; at a time. After assembling one 24-bit word (this takes three loops) it stores the
51
; result in internal PRAM and continues until internal PRAM is filled. Note that the
52
; first routine loads data starting with the least significant byte of P:$0 first.
53
54
; The second routine loads the internal PRAM using the Host Interface logic.
55
; If the host only wants to load a portion of the PRAM, the Host Interface bootstrap
56
; load program can be aborted and execution of the loaded program started, by setting
57
; the Host Flag (HF0) = 1 at any time during the load from the Host Processor.
58
59
P:0009
060082
INLOOP
D0
#512,_LOOP1
; Load 512 instruction words.
00001B
60
61
; This is the context switch
62
63
P:000B
0E6012
JLC
< _HOSTLD
64
; Load from the Host Interface
; if the Limit flag is clear.
65
66
; This is the first routine. It loads from external P: memory.
67
68
P:000C
060380
DO
#3, _LOOP2
; Each instruction has 3 bytes.
000010
Figure E-2. Assembler Listing for Bootstrap Program (Sheet 2 of 3)
DSP56001
MOTOROLA
E-61
Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page 3
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
P:000E
07D98A
MOVE
P:(R1)+,A2
P:000F
P:0010
0608A0
200022
REP
ASR
#8
A
P:0011
0C001B
JMP
< _STORE
_LOOP2
; Get the 8 LSB from external
; P: memory.
; Shift 8 bit data into A1
; Get another byte
; then put the word in PRAM.
; This is the second routine. It loads from the Host Interface pins.
P:0012
P:0013
0AA020
0AA983
000017
00008C
0C001C
_HOSTLD
_LBLA
P:0017
0A6280
000013
_LBLB
P:0019
54F000
00FFEB
P:001B
07588C
P:0015
P:0016
_STORE
BSET
JCLR
#0,X:$FFE0
#3,X:$FFE9, _LBLB
; Configure Port B as Host Interface
; If HF0=1, stop loading data.
ENDDO
JMP
<_BOOTEND
; Must terminate the DO loop
JCLR
; Wait for HRDF to go high
#0,X:(R2), _LBLA
MOVE
X:$FFEB,A1
; (meaning 24-bit data is present)
; Put 24-bit host data in A1
MOVE
A1,P:(R0)+
; Store 24-bit result in PRAM.
_LOOP1
; and return for another 24-bit word
; This is the exit handler that returns execution to normal expanded mode
; and jumps to the RESET location.
P:001C
0502BA
_BOOTEND
MOVEC
#2,0MR
97 P:001D
98
99
100 P:001E
101
0000B9
ANDI
#$0,CCR
0C0000
JMP
<$0
; Set the operating mode to 2
; (and trigger an exit from
; bootstrap mode).
; Clear SR as if RESET and
; introduce delay needed for
; Op. Mode change.
; Start fetching from PRAM P:$0000
Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page 4
0 Errors
0 Warnings
Figure E-2. Assembler Listing for Bootstrap Program (Sheet 3 of 3)
MOTOROLA
E-62
DSP56001
DSP56001
MOTOROLA
E-63
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
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registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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