BUS IC DC/DC CONVERTER MOTOR DRIVER IC RIPPLE COUNTER DRIVER IC I/O IC SENSOR IC SENSOR INTERFACE IC ÿ Low side driver 8x, serial Low side driver 8x, parallel LCD controller ÿ Low side driver (8 channel, serial interface) FEATURES E910.01 APPLICATION PINNING Driver for: ÿ Supply voltage range VDD 4.5V to 5.5V ÿ Low standby current (typical < 1µA) ÿ Relays ÿ Serial structure for direct µC interfacing ÿ Lamps / LEDs ÿ Cascadable ÿ DC and stepper motors ÿ Output status detection ÿ TTL - compatible input levels with threshold DESCRIPTION hysteresis The IC is developed for automotive applications and can also ÿ 8 high current outputs be used in several other application areas. The IC is well suited to drive relays, lamps, bus systems etc. with medium power ÿ (RON typ. 1.5 Ý / Imax=350mA) Wide output operating voltage range Pin Name Description 1 GND Ground GND 1 20 2 TEST Connect to ground TEST 2 19 3 OUT3 Open - drain low - side driver 4 OUT2 Open - drain low - side driver 5 OUT1 Open - drain low - side driver 6 OUT0 Open - drain low - side driver 7 CE Open - drain low - side driver consumption. 8 SCLK 9 SI 10 GND Serial data input 11 GND Ground 12 SO Ground 13 VDD Serial data output (high impendence when CE = High) 14 RESET Supply voltage 15 OUT7 External reset - active low (= internal power on reset) 16 OUT6 Open - drain low - side driver 17 OUT5 Open - drain low - side driver 18 OUT4 Open - drain low - side driver 19 NC Not connected 20 GND Ground (5.5 to 25.5V) ÿ Output open- and short - circuit detection The device provides a serial data bus for comunication with a µC ÿ Individual output short - circuit protection and 8 identical power drivers. All outputs are short circuit pro- ÿ Thermal overload protection tected. A thermal shut-off protects the device against thermal ÿ – 40°C to + 125°C operating temperature overload. Readback capability enables fault detection as well as ÿ SO20w package simple switch monitoring. BLOCK DIAGRAM PACKAGE Chip enable - active low (output data is read back on the falling edge of the pulse and only after 8x n falling edges on SCLK is the output data clocked on the next rising edge) OUT3 3 18 OUT2 4 17 OUT1 5 16 OUT0 6 15 CE 7 14 SCLK 8 13 SI 9 12 10 11 GND GND NC OUT4 OUT5 OUT6 OUT7 RESET VDD SO GND Serial clock input VDD VDD 8 Reset µC control Logic 8 8 OUT 0...7 OVLD Prot. CE SCLK SI Interface SO Note ELMOS Semiconductor AG (below ELMOS) reserves the right to make changes to the product contained in this publication without notice. ELMOS assumes no responsibility for the use of any circuits described herein, conveys no licence under any patent or other right, and makes no representation that the circuits are free of patent infringement. While the information in this publication has been checked, no responsibility, however, is assumed for inaccuracies. ELMOS does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of a life-support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications. 56 Copyright © 2005 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited. www.elmos.de | [email protected] elmos product catalog june 2005 57