PRELIMINARY DATA SHEET 256MB Direct Rambus DRAM SO-RIMM Module EBR25EC8ABSA (128M words × 18 bits) Features The Direct Rambus SO-RIMM module is a generalpurpose high-performance memory module subsystem suitable for use in a broad range of applications including computer memory, mobile personal computers, networking systems and other applications where high bandwidth and low latency are required. • 256MB Direct RDRAM storage and 256 banks total on module • High speed 1066MHz/800MHz Direct RDRAM devices • 160 edge connector pads with 0.65mm pad spacing Module PCB size: 67.60mm × 31.25mm × 1.00mm Gold plated edge connector pads contacts • Serial Presence Detect (SPD) support • Operates from a 2.5V supply • Low power and power down self refresh modes • Separate Row and Column buses for higher efficiency • RDRAMs uses Chip Scale Package (CSP) FBGA package EO Description The EBR25EC8ABSA consists of 8 pieces of 288M Direct Rambus DRAM (Direct RDRAM) devices. These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits 1066MHz or 800MHz transfer rates while using conventional system and board design technologies. L t uc od Pr The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions per device. Document No. E0320E11 (Ver. 1.1) Date Published March 2006 (K) Japan URL: http://www.elpida.com This product became EOL in March, 2004. Elpida Memory, Inc. 2002-2006 EBR25EC8ABSA Ordering Information Part number Organization EBR25EC8ABSA-AD 128M x 18 EBR25EC8ABSA-8C I/O Freq. (MHz) RAS access time (ns) Package Mounted devices 1066 35 160 edge connector pads SO-RIMM with heat spreader 800 40 Edge connector: Gold plated EDR2518ABSE Module Pad Names Pad Signal Name Pad Signal Name A1 A2 Pad Signal Name GND B1 LDQA8 B2 Pad Signal Name GND A41 LDQA7 A42 NC B41 NC VREF B42 VREF EO A3 GND B3 GND A43 SCL B43 SA0 A4 LDQA6 B4 LDQA5 A44 VDD B44 VDD A5 GND B5 GND A45 SDA B45 SA1 A6 LDQA4 B6 LDQA3 A46 VDD B46 VDD GND B7 GND A47 SVDD B47 SWP A8 LDQA2 B8 LDQA1 A48 GND B48 GND A9 GND B9 GND A49 RSCK B49 RCMD A10 LDQA0 B10 LCFM A50 GND B50 GND A11 GND B11 GND A51 RDQB8 B51 RDQB6 A12 LCTM B12 LCFMN A52 GND B52 GND A13 GND B13 GND A53 RDQB7 B53 RDQB4 A14 LCTMN B14 LROW2 A54 GND B54 GND A15 GND B15 GND A55 RDQB5 B55 RDQB2 A16 LROW1 B16 LROW0 A56 GND B56 GND A17 GND B17 GND A57 RDQB3 B57 RDQB0 A18 LCOL4 B18 LCOL3 A58 GND B58 GND A19 GND B19 A20 LCOL2 B20 A21 GND B21 GND A22 LCOL0 B22 LDQB1 A23 GND B23 GND A24 LDQB0 B24 LDQB3 A25 GND B25 GND A26 LDQB2 B26 LDQB5 A27 GND B27 GND A28 LDQB4 B28 A29 GND B29 A30 LDQB6 B30 A31 GND B31 GND A71 RCFM B71 RDQA0 A32 LSCK B32 LCMD A72 GND B72 GND A33 GND B33 GND A73 RDQA1 B73 A34 SOUT B34 SIN A74 GND B74 A35 VDD B35 VDD A75 RDQA3 B75 A36 NC B36 NC A76 GND B76 L A7 Pr GND A59 RDQB1 B59 RCOL0 LCOL1 A60 GND B60 GND od A61 RCOL1 B61 RCOL2 A62 GND B62 GND A63 RCOL3 B63 RCOL4 A64 GND B64 GND RROW0 B65 RROW1 GND B66 GND A67 RROW2 B67 RCTMN LDQB7 A68 GND B68 GND GND A69 RCFMN B69 RCTM LDQB8 A70 GND B70 GND 2 RDQA2 t Preliminary Data Sheet E0320E11 (Ver. 1.1) uc A65 A66 GND RDQA4 GND EBR25EC8ABSA Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name A37 GND B37 GND A77 RDQA5 B77 RDQA6 A38 NC B38 NC A78 GND B78 GND A39 VCMOS B39 VCMOS A79 RDQA7 B79 RDQA8 A40 NC B40 NC A80 GND B80 GND Module Connector Pad Description Module Connector Pads Signal I/O Description – Ground reference for RDRAM core and interface. B10 I RSL B12 I RSL LCMD B32 I VCMOS LCOL4..LCOL0 A18, B18, A20, B20, A22 I RSL LCTM A12 I RSL LCTMN A14 I RSL EO Type A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29,A31, A33, A37, A48, A50, A52, A54,A56, A58, A60, A62, A64, A66, A68,A70, A72, A74, A76, – A78, A80, B1,B3, B5, B7, B9, B11, B13, B15, B17,B19, B21, B23, B25, B27, B29, B31,B33, B37, B48, B50, B52, B54, B56, B58, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80 GND LCFMN L LCFM A2, B2, A4, B4, A6, B6, I/O A8, B8, A10 B30, B28, A30, B26, I/O A28, B24, A26, B22, A24 RSL od LDQB8..LDQB0 Pr LDQA8..LDQA0 Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM.. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Row bus. 3-bit bus containing control and address information for row accesses. Serial clock input. Clock source used to read from and write to the RDRAM control registers. These pads are not connected. These 8 connector pads are reserved for future use. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Column bus. 5-bit bus containing control and address information for column accesses. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. RSL I RSL LSCK A32 I VCMOS NC A36, B36, A38, B38, A40, B40, A41, B41 – – RCFM A71 I RSL RCFMN A69 I RSL RCMD B49 I VCMOS RCOL4..RCOL0 B63, A63, B61, A61, B59 I RSL RCTM B69 I RSL RCTMN B67 I RSL t B14, A16, B16 uc LROW2..LROW0 Preliminary Data Sheet E0320E11 (Ver. 1.1) 3 EBR25EC8ABSA Signal RDQA8..RDQA0 RDQB8..RDQB0 Module Connector Pads I/O B79, A79, B77, A77, I/O B75, A75, B73, A73, B71 A51, A53, B51, A55, I/O B53, A57, B55, A59, B57 Type Description Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. Row bus. 3-bit bus containing control and address information for row accesses. Serial clock input. Clock source used to read from and write to the RDRAM control registers. RSL RSL RROW2..RROW0 A67, B65, A65 I RSL RSCK A49 I VCMOS SA0 B43 I SVDD Serial Presence Detect Address 0. SA1 A43 I SVDD Serial Presence Detect Address 1. SCL B45 I SVDD Serial Presence Detect Clock. SDA A45 I/O SVDD Serial Presence Detect Data (Open Collector I/O). EO Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2. Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. B34 I/O VCMOS SOUT A34 I/O VCMOS SVDD A47 — — SWP B47 I SVDD A39, B39 — — A35, B35, A44, B44, A46, B46 — — Supply voltage for the RDRAM core and interface logic. A42, B42 — — Logic threshold reference voltage for RSL signals. VCMOS VDD VREF L SIN t uc od Pr Preliminary Data Sheet E0320E11 (Ver. 1.1) 4 EBR25EC8ABSA Block Diagram DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 SIO 0 SIO 1 DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 SIO 0 SIO 1 U3 L U8 SIO 1 SCK CMD VREF SVDD SCL SWP VCC SCL SDA WP U0 A0 A1 A2 SA0 SA1 SA2 Preliminary Data Sheet E0320E11 (Ver. 1.1) 5 t Serial PD SDA uc RDQA 8 RDQA 7 RDQA 6 RDQA 5 RDQA 4 RDQA 3 RDQA 2 RDQA 1 RDQA 0 RCFM RCFMN RCTM RCTMN RROW 2 RROW 1 RROW 0 RCOL 4 RCOL 3 RCOL 2 RCOL 1 RCOL 0 RDQB 0 RDQB 1 RDQB 2 RDQB 3 RDQB 4 RDQB 5 RDQB 6 RDQB 7 RDQB 8 SOUT RSCK RCMD od Pr DQA 8 DQA 7 DQA 6 DQA 5 DQA 4 DQA 3 DQA 2 DQA 1 DQA 0 CFM CFMN CTM CTMN ROW 2 ROW 1 ROW 0 COL 4 COL 3 COL 2 COL 1 COL 0 DQB 0 DQB 1 DQB 2 DQB 3 DQB 4 DQB 5 DQB 6 DQB 7 DQB 8 SIO 0 U2 SCK CMD VREF EO VREF U1 SIO 1 VDD VCMOS LDQA 8 LDQA 7 LDQA 6 LDQA 5 LDQA 4 LDQA 3 LDQA 2 LDQA 1 LDQA 0 LCFM LCFMN LCTM LCTMN LROW 2 LROW 1 LROW 0 LCOL 4 LCOL 3 LCOL 2 LCOL 1 LCOL 0 LDQB 0 LDQB 1 LDQB 2 LDQB 3 LDQB 4 LDQB 5 LDQB 6 LDQB 7 LDQB 8 SIN LSCK LCMD VREF SIO 0 SCK CMD VREF SCK CMD Note: 1. Rambus Channel signals form a loop through the SO-RIMM module, with the exception of the SIO chain. 2. See Serial Presence Detection Specification for information on the SPD device and its contents. EBR25EC8ABSA Electrical Specifications Absolute Maximum Ratings Symbol Parameter min. max. Unit VI,ABS Voltage applied to any RSL or CMOS signal pad with respect to GND −0.3 VDD + 0.3 V VDD,ABS Voltage on VDD with respect to GND −0.5 VDD + 1.0 V TSTORE Storage temperature −50 +100 °C Caution EO Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Recommended Electrical Conditions Symbol Parameter and conditions 1 VDD Supply voltage* VCMOS CMOS I/O power supply at pad 2.5V controllers L 1.8V controllers VREF VSPD Reference voltage* 1 min. max. Unit 2.50 − 0.13 2.50 + 0.13 V 2.50 − 0.13 2.50 + 0.25 1.8 − 0.1 1.8 + 0.2 V 1.4 − 0.2 1.4 + 0.2 V 3.6 V Serial Presence Detector- positive power 2.2 supply V Note: 1. See Direct RDRAM datasheet for more details. t uc od Pr Preliminary Data Sheet E0320E11 (Ver. 1.1) 6 EBR25EC8ABSA AC Electrical Specifications Symbol Parameter and Conditions Z TPD ∆TPD ∆TPD-CMOS ∆TPD- SCK,CMD min. typ. max. Unit Module Impedance of RSL signals 25.2 28.0 30.8 Ω Module Impedance of SCK and CMD signals 23.8 28.0 32.2 Ω — — TBD ns TBD — TBD ps TBD — TBD ps TBD — TBD ps — — TBD % — — TBD % — — TBD % — — TBD Ω Average clock delay from finger to finger of all RSL clock nets (CTM, CTMN,CFM, and CFMN) Propagation delay variation of RSL signals with respect 1, 2 to TPD * Propagation delay variation of SCK signal with respect 1 to an average clock delay * Propagation delay variation of CMD signal with respect to SCK signal -AD -8C -AD -8C -AD -8C -AD -8C Attenuation Limit EO Vα/VIN Grade VXF/VIN VXB/VIN RDC Forward crosstalk coefficient (300ps input rise time 20% - 80%) Backward crosstalk coefficient (300ps input rise time 20% - 80%) DC Resistance Limit L Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 2. If the SO-RIMM module meets the following specification, then it is compliant to the specification. If the SO-RIMM module does not meet these specifications, then the specification can be adjusted by the “Adjusted ∆TPD Specification” table. Adjusted ∆TPD Specification Absolute Parameter and conditions ∆TPD Propagation delay variation of RSL signals with respect to TPD Note: 1 Adjusted min./max. Pr Symbol +/− [17+(18*N*∆Z0)] * 1 min. max. Unit TBD TBD ps N = Number of RDRAM devices installed on the SO-RIMM module. ∆Z0 = delta Z0% = (max. Z0 - min. Z0) / (min. Z0) (max. Z0 and min. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.) t uc od Preliminary Data Sheet E0320E11 (Ver. 1.1) 7 EBR25EC8ABSA SO-RIMM Module Current Profile IDD SO-RIMM module power conditions * 1 Grade 2 IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 One RDRAM device in Read * , balance in NAP mode 2 One RDRAM device in Read * , balance in Standby mode 2 One RDRAM device in Read * , balance in Active mode One RDRAM device in Write, balance in NAP mode One RDRAM device in Write, balance in Standby mode One RDRAM device in Write, balance in Active mode EO -AD -8C -AD -8C -AD -8C -AD -8C -AD -8C -AD -8C max. Unit TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA Notes: 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Power does not include Refresh Current. 2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x18 need to add 276mA for the following: VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF − 0.5V. L t uc od Pr Preliminary Data Sheet E0320E11 (Ver. 1.1) 8 EBR25EC8ABSA Physical Outline R1.00 1.00±0.10 25.35 A 13.60 30.00 4.00 25.35 Pad A80 3.70 33.60 67.60 detail of A part 2.55 0.43 R0.75 1.50±0.10 0.65 od 0.15± 0.10 Pr 4.00± 0.10 L EO Pad A1 1.65 31.25 17.50 5.00± 0.10 Unit: mm Note: The dimensions without tolerance specification use the default tolerance of ± 0.13. ECA-TS2-0082-01 t uc Preliminary Data Sheet E0320E11 (Ver. 1.1) 9 EBR25EC8ABSA CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 EO NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES L Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES 3 od Pr No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES uc Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 t Preliminary Data Sheet E0320E11 (Ver. 1.1) 10 EBR25EC8ABSA Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. EO Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. Pr [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. M01E0107 t uc od If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. Preliminary Data Sheet E0320E11 (Ver. 1.1) 11