EL5102, EL5103, EL5202, EL5203, EL5302 ® Data Sheet January 17, 2008 400MHz Slew Enhanced VFAs Features The EL5x02 and EL5x03 families represent high-speed VFAs based on a CFA amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. With slew rates of 3500V/µs, this family of devices enables the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family will also be available in single, dual, and triple versions, with 200MHz, 400MHz, and 750MHz versions. These are all available in single, dual, and triple versions. • Operates off 3V, 5V, or ±5V applications Both families operate on single 5V or ±5V supplies from minimum supply current. EL5x02 also features an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. • AVOL = 2000 Typical applications for these families will include cable driving, filtering, A/D and D/A buffering, multiplexing and summing within video, communications, and instrumentation designs. FN7331.8 • Power-down to 0µA (EL5x02) • -3dB bandwidth = 400MHz • ±0.1dB bandwidth = 50MHz • Low supply current = 5mA • Slew rate = 3500V/µs • Low offset voltage = 5mV max • Output current = 140mA • Differential gain/phase = 0.01%/0.01° • Pb-free available (RoHS compliant) Applications • Video amplifiers • PCMCIA applications • A/D drivers • Line drivers • Portable computers • High speed communications • RGB applications • Broadcast equipment • Active filtering 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5102, EL5103, EL5202, EL5203, EL5302 Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # EL5102IS 5102IS 8 Ld SOIC (150 mil) MDP0027 EL5102IS-T7* 5102IS 8 Ld SOIC (150 mil) MDP0027 EL5102IS-T13* 5102IS 8 Ld SOIC (150 mil) MDP0027 EL5102ISZ (Note) 5102ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5102ISZ-T7* (Note) 5102ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5102ISZ-T13* (Note) 5102ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5102IW-T7* q 6 Ld SOT-23 MDP0038 EL5102IW-T7A* q 6 Ld SOT-23 MDP0038 EL5102IWZ-T7* (Note) BBSA 6 Ld SOT-23 (Pb-free) MDP0038 EL5102IWZ-T7A* (Note) BBSA 6 Ld SOT-23 (Pb-free) MDP0038 EL5103IC B 5 Ld SC-70 P5.049 EL5103IC-T7* B 5 Ld SC-70 P5.049 EL5103IC-T7A* B 5 Ld SC-70 P5.049 EL5103IW-T7* g 5 Ld SOT-23 MDP0038 EL5103IW-T7A* g 5 Ld SOT-23 MDP0038 EL5103IWZ-T7* BBTA 5 Ld SOT-23 (Pb-free) MDP0038 EL5103IWZ-T7A* BBTA 5 Ld SOT-23 (Pb-free) MDP0038 EL5202IY BRAAA 10 Ld MSOP (3.0mm) MDP0043 EL5202IY-T7* BRAAA 10 Ld MSOP (3.0mm) MDP0043 EL5202IY-T13* BRAAA 10 Ld MSOP (3.0mm) MDP0043 EL5202IYZ (Note) BAAAD 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5202IYZ-T7* (Note) BAAAD 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5202IYZ-T13* (Note) BAAAD 10 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5203IS 5203IS 8 Ld SOIC (150 mil) MDP0027 EL5203IS-T7* 5203IS 8 Ld SOIC (150 mil) MDP0027 EL5203IS-T13* 5203IS 8 Ld SOIC (150 mil) MDP0027 EL5203ISZ (Note) 5203ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5203ISZ-T7* (Note) 5203ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5203ISZ-T13* (Note) 5203ISZ 8 Ld SOIC (150 mil) (Pb-free) MDP0027 EL5203IY BSAAA 8 Ld MSOP (3.0mm) MDP0043 EL5203IY-T7* BSAAA 8 Ld MSOP (3.0mm) MDP0043 EL5203IY-T13* BSAAA 8 Ld MSOP (3.0mm) MDP0043 EL5203IYZ (Note) BAAAE 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5203IYZ-T7* (Note) BAAAE 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5203IYZ-T13* (Note) BAAAE 8 Ld MSOP (3.0mm) (Pb-free) MDP0043 EL5302IU 5302IU 16 Ld QSOP (150 mil) MDP0040 EL5302IU-T7* 5302IU 16 Ld QSOP (150 mil) MDP0040 EL5302IU-T13* 5302IU 16 Ld QSOP (150 mil) MDP0040 EL5302IUZ (Note) 5302IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5302IUZ-T7* (Note) 5302IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 EL5302IUZ-T13* (Note) 5302IUZ 16 Ld QSOP (150 mil) (Pb-free) MDP0040 * Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Pinouts EL5103 (5 LD SOT-23) TOP VIEW EL5102 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 + - IN+ 3 6 VS+ OUT 1 5 CE VS- 2 4 IN- IN+ 3 8 CE IN- 2 + IN+ 3 VS- 4 INA- 2 6 OUT INA+ 3 IN+ 3 9 OUT + VS- 4 CE 5 7 OUTB + 6 INB+ 8 IN- INA+ 1 CEA 2 16 INA+ 7 IN+ CEB 4 6 CE INB+ 5 CEC 7 INC+ 8 15 OUTA 14 VS+ VS- 3 + - 13 OUTB 12 INB- NC 6 3 5 INB+ EL5302 (16 LD QSOP) TOP VIEW 10 VS+ + 8 VS+ VS- 4 EL5202 (10 LD MSOP) TOP VIEW IN- 2 4 IN- OUTA 1 7 VS+ 5 NC OUT 1 + - EL5203 (8 LD SOIC, MSOP) TOP VIEW EL5102 (8 LD SOIC) TOP VIEW NC 1 5 VS+ 11 NC + - 10 OUTC 9 INC- FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and GND. . . . . . . . . . . . . . . . . . 13.2V Maximum Supply Slewrate between VS+ and VS- . . . . . . . . . 1V/µs Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 80mA Maximum Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . ±5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, RL = 500Ω, VENABLE = +5V, Unless Otherwise Specified. TYP MAX UNIT EL5102, EL5103, EL5202, EL5203 1 5 mV EL5302 2 8 mV Offset Voltage Temperature Coefficient Measured from TMIN to TMAX 10 Input Bias Current VIN = 0V -12 2 12 µA Input Offset Current VIN = 0V -8 1 8 µA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX PSRR Power Supply Rejection Ratio VS = ±4.75V to ±5.25V CMRR Common Mode Rejection Ratio CMIR VOS TCVOS IB IOS DESCRIPTION Offset Voltage CONDITIONS MIN µV/°C 50 nA/°C -70 -80 dB VCM = -3V to 3.0V -60 -80 dB Common Mode Input Range Guaranteed by CMRR test -3 ±3.3 RIN Input Resistance Common mode 200 400 kΩ CIN Input Capacitance SO package 1 pF 3 V IS,ON Supply Current - Enabled Per Amplifier 4.6 5.2 5.8 mA IS,OFF Supply Current - Shut-down Per Amplifier VS+ +1 +9 +25 µA VS- -25 -13 -1 µA VOUT = ±2.5V, RL = 1kΩ to GND 58 66 dB 60 dB AVOL Open Loop Gain VOUT = ±2.5V, RL = 150Ω to GND VOUT IOUT Output Voltage Swing Output Current RL = 1kΩ to GND ±3.5 ±3.9 V RL = 150Ω to GND ±3.4 ±3.7 V AV = 1, RL = 10Ω to 0V ±80 ±150 mA VCE-ON CE Pin Voltage for Power-up (VS+) -5 (VS+) -3 V VCE-OFF CE Pin Voltage for Shut-down (VS+) -1 VS+ V IEN-ON Pin Current - Enabled CE = 0V -1 0 +1 µA IEN-OFF Pin Current - Disabled CE = +5V 1 14 25 µA 4 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Closed Loop AC Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VENABLE = +5V, AV = +1, RF = 0Ω, RL = 150Ω to GND Pin, Unless Otherwise Specified. (Note 1) PARAMETER DESCRIPTION CONDITIONS BW -3dB Bandwidth (VOUT = 400mVP-P) AV = 1, RF = 0Ω SR Slew Rate AV = +2, RL = 100Ω, VOUT = -3V to +3V RL = 500Ω, VOUT = -3V to +3V MIN TYP MAX 400 1100 2200 UNIT MHz 5000 V/µs 4000 V/µs tR,tF Rise Time, Fall Time ±0.1V step 2.8 ns OS Overshoot ±0.1V step 10 % tS 0.1% Settling Time VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 20 ns dG Differential Gain (Note 2) AV = 2, RF = 1kΩ 0.01 % dP Differential Phase (Note 2) AV = 2, RF = 1kΩ 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/√Hz iN Input Noise Current f = 10kHz 11 pA/√Hz tDIS Disable Time (Note 3) 50 ns tEN Enable Time (Note 3) 25 ns NOTES: 1. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested. 2. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. 5 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves 5 3 2 120 1 0 -1 -2 60 0 -60 -120 -3 -180 -4 -3dB BW @ 438MHz -240 -5 0.1 1M 10M 100M FREQUENCY (Hz) 0.1 1G 70 0.5 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 0.3 0.2 0.1 VS = ±5V RL = 500Ω 0.1dB BW @ 35MHz 0 -0.1 10M FREQUENCY (Hz) 100M 1G GAIN = 40dB or 100 FREQUENCY = 1.64 MHz GAIN BW PRODUCT = 1.64 x 100 = 164MHz 60 GAIN (dB) 0.4 1M FIGURE 2. PHASE vs FREQUENCY FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH) NORMALIZED GAIN (dB) VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 180 PHASE (°) NORMALIZED GAIN (dB) 240 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 4 50 40 -0.2 30 -0.3 -0.4 20 -0.5 1M 10M FREQUENCY (Hz) 100M 300 1M 10M FREQUENCY (Hz) 5 VS = ±5V RL = 500Ω 4 250 200 150 100 3 VS = ±5V RL = 500Ω CL = +3.3pF AV = +1 RF = 0 1 0 -1 -2 AV = +5 RF = 1.6k, RG = 400 -3 -5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (±V) FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES 6 AV = +2 RF = RG = 400Ω 2 -4 50 2.0 100M FIGURE 4. GAIN BANDWIDTH PRODUCT NORMALIZED GAIN (dB) GAIN-BANDWIDTH PRODUCT (MHz) FIGURE 3. 0.1dB BANDWIDTH 0 0.1 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 5 5 3 2 AV = +1 RF = 0 RL = 500Ω CL = +3.3pF 1 0 -1 VS = ±6 VS = ±5V VS = ±4V -2 -3 VS = ±3V -4 -5 1M 10M 100M 3 2 RL = 500Ω 0 -1 -2 RL = 150Ω -3 RL = 75Ω -5 1G RL = 50Ω 0.1 1M FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±VS RL = 500Ω RL = 1kΩ 0 -1 RL = 50Ω RL = 70Ω -3 RL = 150Ω -4 1M 10M 100M FREQUENCY (Hz) 3 2 CL = 27pF CL = 15pF CL = 8.2pF 1 RL = 1kΩ 0 -1 RL = 50Ω -2 -3 RL = 75Ω RL = 150Ω 0.1 5 VS = ±5V AV = +1 RF = 0 RL = 500Ω 0 -1 CL = 3.3pF -2 -3 CL = 0pF -4 RL = 500Ω 1 1M 10M FREQUENCY (Hz) 100M FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +5) 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 2 -5 1G FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2) 5 3 -4 -5 0.1 VS = ±5V AV = +5 RF = 402Ω CL = +3.9pF 4 1 -2 1G 5 VS = ±5V AV = +2 RF = 402Ω CL = +3.9pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 100M FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1) 5 3 10M FREQUENCY (Hz) FREQUENCY (Hz) 4 RL = 1kΩ 1 -4 VS = ±2.5V 0.1 VS = ±5V AV = +1 RF = 0 CL = +3.3pF 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 3 2 VS = ±5V AV = +2 RF = 400Ω RL = 500Ω CL = 47pF CL = 18pF 1 0 -1 CL = 8.2pF -2 -3 CL = 0pF -4 -5 CL = 33pF -5 0.1 1M 10M 100M FREQUENCY (Hz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +1) 7 1G 0.1 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2) FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 5 3 2 CL = 150pF CL = 220pF CL = 100pF 1 0 -1 CL = 56pF -2 -3 -4 3 2 RF = 50Ω -2 RF = 25Ω -3 RF = 0Ω -4 10M -5 100M 0.1 1M FREQUENCY (Hz) 3 2 VS = ±5V AV = +2 RL = 500Ω CL = +8pF 5 RF = 1.0kΩ RF = 680Ω 1 0 -1 RF = 402Ω -2 RF = 274Ω -3 -4 -5 1M 10M VS = ±5V AV = +5 RL = 500Ω CL = +12pF 4 3 2 100M 1 0 -1 RF = 100Ω RF = 1kΩ -2 -3 RF = 402Ω 1G -5 0.1 1M FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2) 3 2 VS = ±5V CIN = 3.3pF AV = +2 RF = RG = 402Ω CIN = 2.2pF RL = 500Ω CL= +8pF 0 -1 CIN = 1pF -3 CIN = 0pF -4 -5 0.1 1M 10M 100M FREQUENCY (Hz) 4 3 2 VS = ±5V AV = +5 RG = 402Ω RL = 1600Ω CL = +12pF CIN = 8.2pF CIN = 10pF CIN = 6.8pF 1 0 -1 -2 CIN = 0pF CIN = 4.7pF -3 -4 1G FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2) 8 5 CIN = 4.7pF 1 -2 100M FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10M FREQUENCY (Hz) FREQUENCY (MHz) 5 1G RF = 4kΩ RF = 2kΩ -4 RF = 100Ω 0.1 100M FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +1) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10M FREQUENCY (Hz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +5) 5 RF = 150Ω 0 -1 -5 1M RF = 100Ω 1 CL = 0pF 0.1 VS = ±5V AV = +1 RL = 500Ω CL = +3pF 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 5 VS = ±5V AV = +5 RF = 400Ω RL = 500Ω 4 -5 0.1 1M 10M FREQUENCY (Hz) 100M FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5) FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 -45 70 0 45 PHASE 50 90 40 135 30 180 20 225 GAIN 10 270 0 315 VCC = +5V VEE = -5V -10 -20 10 100 1k 100 OUTPUT IMPEDANCE (Ω) 80 60 GAIN (dB) (Continued) PHASE (°) Typical Performance Curves 360 10k 100k 1M AV = +2 VS = ±5V 10 1 0.1 0.01 405 10M 100M 1G 10k 100k FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 0 -10 -40 -20 PSRR (dB) CMRR (dB) 10 -30 -50 -60 -70 -50 -60 -70 -100 -80 100k 1M 10M -90 1k 100M 500M AV = +1 VS = ±5V -40 -90 10k +PSRR -PSRR 10k RLOAD = 1kΩ 8 GROUP DELAY (ns) MAX OUTPUT VOLTAGE SWING (VP-P) 10 7 6 5 4 2 1 0 VS = ±5V AV = +2 RF = RG = 402Ω CL = 8pF 0.1 RLOAD = 150Ω 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY 9 1M 10M 100M 500M FIGURE 22. PSRR vs FREQUENCY FIGURE 21. CMRR vs FREQUENCY 9 100k FREQUENCY (Hz) FREQUENCY (Hz) 3 100M -30 -80 -110 1k 10M FIGURE 20. OUTPUT IMPEDANCE/PHASE vs FREQUENCY AV = +5 VS = ±5V -20 1M FREQUENCY (Hz) FREQUENCY (Hz) 30 25 VS = ±5V A = +1 20 RV = 0 F 15 RL = 500Ω 10 5 0 -5 -10 -15 -20 -25 -30 0.1 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 24. GROUP DELAY vs FREQUENCY FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) -10 VS = ±5V AV = +1 RF = 0 CHIP DISABLED ISOLATION (dB) -30 OUTPUT TO INPUT -40 -50 -60 INPUT TO OUTPUT GAIN (dB) -20 -70 -80 -90 -100 0.1 1M 10M 100M 1G 10 NOTE: 0 VS = ±5V This was done on the -10 AV = +1 EL5203 (Dual Op-Amps) RF = 0 -20 RL = 500Ω -30 BIN TO AOUT -40 -50 AIN TO BOUT -60 -70 -80 -90 -100 -110 -120 0.1 1M 10M 100M FREQUENCY (Hz) FIGURE 25. INPUT AND OUTPUT ISOLATION FIGURE 26. CHANNEL-TO-CHANNEL ISOLATION -20 -40 -50 -60 -70 -40 T.H.D 2nd HD -80 -70 -100 100M ENABLE SIGNAL 4 3 VS = ±5V AV = +1 RF = 0 RL = 500Ω VOUT = 2VP-P OUTPUT SIGNAL 2 1 0 2 10 3 4 5 6 7 8 DISABLE SIGNAL OUTPUT SIGNAL 1 0 -2 FIGURE 29. TURN-ON TIME 2 VS = ±5V 5 AV = +1 RF = 0 4 R = 500Ω L 3 VOUT = 2VP-P -2 TIME (ns) 1 6 -1 0 200 400 600 800 1000 1200 1400 1600 0 FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES -1 -3 -600 -400 -200 FIN = 1MHz OUTPUT VOLTAGES (VP-P) AMPLITUDE (V) 1M 10M FUNDAMENTAL FREQUENCY (Hz) 6 AMPLITUDE (V) -60 -90 3rd HD FIGURE 27. HARMONIC DISTORTION vs FREQUENCY 5 -50 FIN = 10MHz -80 -90 -100 0.1 VS = ±5V AV = +5 RG = 402Ω RF = 1600Ω RL = 500Ω CL = 12pF -30 THD (dBc) HARMONIC DISTORTION (dBc) -30 VS = ±5V AV = +1 RF = 0 RL = 500Ω CL = 3.3pF VOUT = 2VP-P 1G FREQUENCY (Hz) -3 -600 -400 -200 0 200 400 600 800 1000 1200 1400 1600 TIME (ns) FIGURE 30. TURN-OFF TIME FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 0.5 VS = ±5V 0.4 AV = +1 RF = 0 0.3 AMPLITUDE (V) NOISE VOLTAGE (nV/√Hz) 1000 VS = ±5V 100 10 0.2 tFALL = 0.9ns 0.1 0.0 tRISE = 0.923ns -0.1 -0.2 1 10 100 1k 10k -0.3 -20 100k 0 20 FREQUENCY (Hz) FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY 3 6.0 VS = ±5V AV = +5 RG = 25Ω RL = 500Ω CL = 5pF VOUT = 4.0V 5.8 SUPPLY CURRENT (mA) AMPLITUDE (V) 4 2 1 tFALL = 1.167ns 0 tRISE = 1.243ns -1 -2 40 60 80 100 120 140 160 TIME (ns) 0 -10 -20 -30 -40 -50 5.4 5.2 5.0 4.8 4.6 Please note that the curve showed positive Current. The negative current was almost the same. 4.4 40 35 f1 = 1dBm @ 0.95MHz 2f2-f1 = -77.0dBm @ 1.15MHz 6.0 30 25 20 15 -80 10 -90 5 -100 0.8M 5.5 VS = ±5V AV = +5 RF = 1600Ω RL = 100Ω CL = 12pF 45 f2 = 1dBm @ 1.05MHz 2f1-f2 = -76.8dBm -60 @ 0.85MHz -70 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 50 ΔIM = (1) - (-77) = 78dB IP3 = 1+ (78/2) = 40dBm VS = ±5V AV = +5 RF = 1600Ω RL = 100Ω CL = 12pF 3.0 FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE IP3 (dBm) 20 FIGURE 33. LARGE SIGNAL STEP RESPONSE RISE AND FALL TIME 10 5.6 4.0 2.5 -3 0 60 80 100 120 140 160 TIME (ns) AV = +1 RF = 0 RL = 500Ω CL = 3.3pF 4.2 -20 40 FIGURE 32. SMALL SIGNAL STEP RESPONSE RISE AND FALL TIME 5 AMPLITUDE (dBm) RL = 500Ω CL = 3.3pF VOUT = 400mV 0 0.9M 1.0M FREQUENCY (Hz) 1.1M 1.2M FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3) 11 1M 10M FREQUENCY (Hz) 100M FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 1.0 1.087W M θ JA = 0.8 0.6 543mW θJ 0.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 SO P8 /1 +1 0 15 °C /W SO A =+ 0.2 T2 3 - 5/6 230 °C/ W 1.2 1.136W SO8 θJA = +110°C/W 1.0 1.116W 0.8 QSOP16 θJA = +112°C/W 0.6 0.4 0.2 0 0 0 25 75 85 100 50 125 0 150 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.7 1.0 0.6 MSOP8/10 θJA = +206°C/W 488mW 0.5 POWER DISSIPATION (W) POWER DISSIPATION (W) 607mW 0.4 SOT23-5/6 θJA = +256°C/W 0.3 0.2 0.1 0 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 12 791mW 0.8 QSOP16 θJA = +158°C/W 781mW 0.6 SO8 θJA = +160°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 SOT-23 Package Family MDP0038 e1 D SOT-23 PACKAGE FAMILY A MILLIMETERS 6 N SYMBOL 4 E1 2 E 3 0.15 C D 1 2X 2 3 0.20 C 5 2X e 0.20 M C A-B D B b NX 0.15 C A-B 1 3 SOT23-5 SOT23-6 A 1.45 1.45 MAX A1 0.10 0.10 ±0.05 A2 1.14 1.14 ±0.15 b 0.40 0.40 ±0.05 c 0.14 0.14 ±0.06 D 2.90 2.90 Basic E 2.80 2.80 Basic E1 1.60 1.60 Basic e 0.95 0.95 Basic e1 1.90 1.90 Basic L 0.45 0.45 ±0.10 L1 0.60 0.60 Reference N 5 6 Reference D 2X TOLERANCE Rev. F 2/07 NOTES: C A2 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. SEATING PLANE A1 0.10 C 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. NX 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) 6. SOT23-5 version has no center lead (shown as a dashed line). H A GAUGE PLANE c L 13 0.25 0° +3° -0° FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X 14 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 α WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 16 FN7331.8 January 17, 2008 EL5102, EL5103, EL5202, EL5203, EL5302 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7331.8 January 17, 2008