QLogic Corporation FAS216/216U/236/236U Fast Architecture SCSI Processor Data Sheet Features ■ ■ ■ ■ ■ ■ ■ Host application and 16-bit peripheral application support Compliance with ANSI SCSI standard X3.131-1994 Compliance with ANSI SCSI configured automatically (SCAM) protocol levels 1 and 2 Compliance with ANSI X3T10/855D SCSI-3 parallel interface (SPI) standard Compliance with ANSI X3T10/1071D Fast-20 standard Asynchronous data transfers up to 7 Mbytes/sec Synchronous data transfers up to 5 Mbytes/sec (normal SCSI), 10 Mbytes/sec (fast SCSI), and 20 Mbytes/sec (Ultra SCSI) ❒ Programmable synchronous transfer period ❒ Programmable synchronous transfer offsets up to 15 bytes ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 24-bit transfer counter Initiator and target modes Differential driver protection (DIFFSENS) Direct memory access (DMA) burst transfer rate up to 20 Mbytes/sec Pipelined command structure 16-byte data FIFO between DMA and SCSI channels Parity pass-through on FIFO data Part-unique ID code On-chip, single-ended SCSI transceivers (48-mA drivers) Clock rates up to 40 MHz SCSI DATA DB BUS COMMAND TRANSFER COUNTER REGISTER BUS (IN) TRANSFER COUNT SEL/RESEL BUS ID INTERRUPT SEL/RESEL TIMEOUT SYNC PERIOD REGISTER BUS (OUT) FIFO STATUS SEQUENCERS SYNC OFFSET/ SYNC ASSERT/ SYNC DEASSERT SEQUENCE STEP SCSI CONTROL CLOCK CONVERSION CONFIGURATION PAD BUS NOTE: TEST (SCAM) SCAM APPLIES TO THE FAS216U AND FAS236U ONLY. Figure 1. FAS2x6 Block Diagram 53236-580-00 C FAS216/216U/236/236U 1 QLogic Corporation NOTE: Throughout this data sheet, the term FAS2x6 refers to the FAS216, FAS216U, FAS236, and FAS236U unless otherwise noted. Product Description The FAS2x6 chips are part of the QLogic SCSI processor family with features designed to facilitate SCSI-2 support (FAS216 and FAS236) and SCSI-3 support (FAS216U and FAS236U). The FAS216 and FAS236 can transfer synchronous data at 10 Mbytes/sec. The FAS216U and FAS236U can transfer data at 20 Mbytes/sec with SCAM support. The normal 5-Mbytes/sec transfer rate and the fast 10-Mbytes/sec transfer rate (FAS216U and FAS236U) are supported on-chip by setting the FASTSCSI bit (Configuration 3 register bit 4). Asynchronous transfers up to 7 Mbytes/sec are also supported. The FAS216U and FAS236U chips are firmware and pin compatible with the FAS216 and FAS236 chips, respectively. Figure 1 shows the FAS2x6 block diagram. The FAS2x6 replaces existing SCSI interface circuitry, which typically consists of discrete devices, an external driver, and a low-performance SCSI interface chip. The FAS2x6 contains a fast DMA interface; a 16-byte FIFO; and fast asynchronous and synchronous data interfaces to the SCSI bus, including drivers in single-ended mode. Differential mode requires external drivers. The FAS216 and FAS216U support single-ended mode; the FAS236 and FAS236U support single-ended and differential modes. Since the FAS2x6 operates in both initiator and target modes, it can be used in both host and peripheral applications. The chip performs such functions as bus arbitration, selection of a target, and reselection of an initiator. The FAS2x6 also handles message, command, status, and data transfers between the SCSI bus and its internal FIFO or between the SCSI bus and buffer memory. The chip maximizes protocol efficiency by utilizing a FIFO command pipeline and combination commands to minimize host intervention. Differential Driver Protection (FAS236/236U Only) The FAS236/236U pins 5 (DIFFSENS) and 7 (EDIFFS) support the SCSI DIFFSENS differential driver protection function. The DIFFSENS function is enabled in differential mode when pins 5 and 7 are pulled up by an external device. The FAS236/236U is configured for differential mode operations when pin 87 (DIFFM) is low. If a single-ended device or terminator is connected while the chip is configured for differential operations, DIFFSENS becomes grounded, disabling the differential drivers. The Gross Error bit (Status register bit 6) is set and a disconnect interrupt is generated. The Gross Error bit and the disconnect interrupt are asserted as long as the DIFFSENS condition exists. The DIFFSENS function has no effect in single-ended mode. 2 FAS216/216U/236/236U SCAM Implementation The FAS216U and FAS236U support levels 1 and 2 of the SCAM protocol. SCAM protocol requires direct access and control over the SCSI data bus and several of the SCSI phase and control signals. The majority of the SCAM protocol can be implemented in firmware at microprocessor speeds. The following SCAM features are supported in the chip hardware: ■ Arbitration without an ID ■ Slow response to selection with an unconfirmed ID ■ Detection of and response to SCAM selection System Organization The FAS2x6 controller systems support three main buses: the 8- or 16-bit data bus (DB), the 8-bit microprocessor address and data bus (PAD), and the 8-bit SCSI bus. The DB provides a path for DMA transfers through the FIFO. The PAD bus provides access to all internal registers. The FAS2x6 supports parity pass-through from the SCSI bus through the FIFO to the DB. This versatile split-bus architecture separates the two high-traffic information flows, the SCSI bus and DB bus, to provide maximum efficiency and throughput. Single- or split-bus configurations with 8- or 16-bit DMA are pin selectable. Table 1 shows chip operating conditions. Interfaces The FAS2x6 acts as an interface between the microprocessor and the SCSI bus in target or initiator mode. The other interfaces are described below: ■ Microprocessor Interface. The DB or PAD bus is the microprocessor interface to the FAS2x6. Both buses allow the microprocessor 8-bit read and write access to all chip registers, including the FIFO. The PAD bus allows microprocessor interface to the chip registers independent of DMA activity on the DB. ■ DMA Interface. The FAS2x6 logic transfers data to and from a buffer over the DB configured as 8 or 16 bits. (Each byte on the bus has its own parity.) If byte control mode (Configuration 2 register bit 5) is set, an external DMA controller can dictate how the bytes are placed on the bus. Packaging The pin diagrams for the FAS216/216U and FAS236/236U are shown in figures 2 and 3. Pins that support the FAS216/216U and FAS236/236U operations are shown in figures 4 and 5. Dimensions for the FAS216/216U 84-pin plastic leaderless chip carrier (PLCC) and the FAS236/236U 100-pin plastic quad flat pack (PQFP) are shown in figures 6 and 7. 53236-580-00 C VSS 75 VSS DB2 79 76 DB3 80 77 DB4 81 DB1 DB5 82 DB0 DB6 83 78 DB7 1 84 DB8 3 VSS DB9 4 DBP0 DB10 5 2 DB11 6 DB12 8 7 DB14 DB13 9 DB15 10 11 DBP1 QLogic Corporation SDI0 12 74 DBWR SDI1 13 73 DACK SDI2 14 72 DREQ SDI3 15 71 PAD7 SDI4 16 70 PAD6 SDI5 17 69 PAD5 SDI6 18 68 PAD4 SDI7 19 67 VSS SDIP 20 66 PAD3 VDD 21 65 PAD2 64 PAD1 63 PAD0 FAS216/216U 84-PIN PLCC 52 INT 53 51 RESET 50 MODE1 MODE0 ACKI REQI 49 WR RSTI 54 48 32 47 SDOP 46 RD BSYI CS 55 45 56 31 SELI 30 SDO7 44 SDO6 VSS A0, SA0 43 57 RSTO 29 42 SDO5 ATN A1, BHE 41 58 40 28 IO SDO4 CD A2, DBRD 39 A3, ALE 59 MSG 60 27 38 26 VSS VSS SDO3 37 CK ACKO 61 36 25 35 SDO2 BSYO VDD REQO 62 34 SDO1 24 SELO 23 33 SDO0 VSS VSS 22 Figure 2. FAS216/216U 84-Pin PLCC Pin Diagram 53236-580-00 C FAS216/216U/236/236U 3 SDO7 51 VSS NC VSS 54 SDOP SELO 55 52 BSYO 56 53 REQO 57 IO 64 ACKO ATN 65 58 RSTO 66 VSS VSS 67 59 VSS 68 60 SELI 69 MSG BSYI 70 VSS REQI 71 61 ACKI 72 CD RSTI 73 62 MODE1 74 63 INT MODE0 75 RESET 77 76 WR NC 78 RD 79 80 QLogic Corporation CS 81 50 SDO6 A0, SA0 82 49 SDO5 A1, BHE 83 48 SDO4 A2, DBRD 84 47 VSS A3, ALE 85 46 VSS CK 86 45 SDO3 DIFFM 87 44 SDO2 VDD 88 43 SDO1 NC 89 42 SDO0 PAD0 90 41 VSS PAD1 91 40 VSS PAD2 92 39 NC PAD3 93 38 VDD VSS 94 37 SDIP VSS 95 36 SDI7 PAD4 96 35 SDI6 PAD5 97 34 SDI5 PAD6 98 33 SDI4 PAD7 99 32 SDI3 DREQ 100 31 SDI2 18 19 20 21 22 23 24 25 26 VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 30 17 VSS SDI1 16 DBP0 29 15 DB7 SDI0 14 DB6 28 13 DB5 NC 12 DB4 27 11 DB3 DBP1 10 DB2 DB15 9 7 EDIFFS DB1 6 TGS 8 5 DB0 4 3 NC IGS 2 DIFFSENS 1 DACK DBWR FAS236/236U 100-PIN PQFP Figure 3. FAS236/236U Pin Diagram 4 FAS216/216U/236/236U 53236-580-00 C QLogic Corporation FAS216/216U MICROPROCESSOR INTERFACE A0, SA0 A1, BHE 57 58 48 37 A2, DBRD 59 A3, ALE 42 60 46 CS INT PAD7-0 RD WR 56 52 71-68, 66-63 55 54 35 40 41 39 47 36 DACK DMA AND MICROPROCESSOR INTERFACE DB15-0 DBP1-0 DBWR DREQ 73 10-3, 84-77 11, 1 74 72 49 43 20, 19-12 32, 31-28, 26-23 45 34 RESET RESET CK POWER AND GROUND NOTE: VDD VSS ACKO SCSI INTERFACE ATN BSYI BSYO CD IO MSG REQI REQO RSTI RSTO SDIP, SDI7-0 SDOP, SDO7-0 SELI SELO 53 50, 51 CLOCK ACKI MODE1-0 MISC 61 21, 62 SEE NOTE VSS = 2, 22, 27, 33, 38, 44, 67, 75, 76 Figure 4. FAS216/216U Functional Signal Grouping 53236-580-00 C FAS216/216U/236/236U 5 QLogic Corporation FAS236/236U A0, SA0 MICROPROCESSOR INTERFACE A1, BHE 82 83 A2, DBRD 84 A3, ALE 85 CS 81 INT PAD7-0 RD WR 72 59 65 70 57 76 63 99-96, 93-90 64 80 62 79 71 58 DACK DMA AND MICROPROCESSOR INTERFACE DB15-0 DBP1-0 DBWR DREQ RESET RESET 73 1 26-19, 15-8 27, 16 2 66 37, 36-29 52, 51-48, 45-42 100 77 69 56 87 5 CLOCK POWER AND GROUND NO CONNECT NOTE: CK VDD VSS 86 38, 88 SEE NOTE 7 74, 75 4 6 ACKI ACKO SCSI INTERFACE ATN BSYI BSYO CD IO MSG REQI REQO RSTI RSTO SDIP, SDI7-0 SDOP, SDO7-0 SELI SELO DIFFM DIFFSENS MISC EDIFFS MODE1-0 IGS TGS EXTERNAL TRANSCEIVER CONTROL 3, 28, 39, 53, 78,89 VSS = 17, 18, 40, 41, 46, 47, 54, 55, 60, 61, 67, 68, 94, 95 Figure 5. FAS236/236U Functional Signal Grouping 6 FAS216/216U/236/236U 53236-580-00 C QLogic Corporation 0.175 (NOM) 0.045 X 45° CHFR 0.576 0.15 (NOM) 0.05 (NOM) 1.19 SQ (NOM) 0.576 0.045 X 45° CHFR PIN 1 INDICATOR 0.45 1.12 SQ (NOM) 1.153 SQ (NOM) 0.028 (NOM) 0.018 (NOM) 0.072 (NOM) 0.010 X 45° CHFR (3) 0.093 (NOM) 0.025 (NOM) 0.107 (NOM) NOTE: ALL DIMENSIONS ARE IN INCHES. ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE. Figure 6. FAS216/216U 84-Pin PLCC Mechanical Drawings 23.9 ± 0.25 20.00 PIN 80 PIN 81 A PIN 51 PIN 50 0.13 MIN 0.23 MAX 17.9 ± 0.25 3.4 MAX 14.00 4° TYPICAL INDEX MARK PIN 31 0.13 MIN 0.22 MIN 0.38 MAX 0.8 + 0.15 PIN 100 PIN 30 PIN 1 0.65 BSC 1.95 REF DETAIL A NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE. Figure 7. FAS236/236U 100-Pin PQFP Mechanical Drawings 53236-580-00 C FAS216/216U/236/236U 7 QLogic Corporation Electrical Characteristics Table 1. Operating Conditions Symbol Description VDD Supply voltage IDDa Supply current (static IDD) IDDb Supply current (dynamic IDD) TA Ambient temperature Minimum Maximum Unit 4.75 5.25 V 4 mA 40-60 mA 70 oC 0 Table Notes Conditions not within operating conditions but within the absolute maximum stress ratings may cause the chip to malfunction. a Static IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, and all bidirectional pins configured as inputs. bDynamic IDD is dependent on the application. Specifications are subject to change without notice. QLogic is a trademark of QLogic Corporation. ©October 4, 1996 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200 8 FAS216/216U/236/236U 53236-580-00 C