FPD200 Datasheet v3.0 GENERAL PURPOSE PHEMT DIE LAYOUT: FEATURES: • • • • • 19 dBm Output Power (P1dB) 13 dB Power Gain at 12 GHz 17 dB Maximum Stable Gain at 12 GHz 12 dB Maximum Stable Gain at 18 GHz 45% Power-Added Efficiency GENERAL DESCRIPTION: The FPD200 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), featuring a 0.25 µm by 200 µm Schottky barrier gate, defined by highresolution stepper-based photolithography. The recessed gate structure minimizes parasitics to optimize performance. The epitaxial structure and processing have been optimized for reliable medium-power applications. TYPICAL APPLICATIONS: • • • • Narrowband and broadband highperformance amplifiers SATCOM uplink transmitters PCS/Cellular low-voltage high-efficiency output amplifiers Medium-haul digital radio transmitters ELECTRICAL SPECIFICATIONS1: PARAMETER SYMBOL CONDITIONS MIN TYP Power at 1dB Gain Compression P1dB VDS = 5 V; IDS = 50% IDSS 18 19 dBm Power Gain at P1dB G1dB VDS = 5 V; IDS = 50% IDSS 11.0 13.0 dB Noise Figure N.F.min VDS = 5 V; IDS = 50% IDSS 1.2 dB Power-Added Efficiency PAE VDS = 5V; IDS = 50% IDSS; POUT = P1dB 45 % Maximum Stable Gain (S21/S12) MSG 16 17 dB 10.5 12 dB 45 60 f = 12 GHz VDS = 5 V; IDS = 50% IDSS f = 24 GHz MAX 75 UNITS Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V mA Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 120 mA Transconductance GM VDS = 1.3 V; VGS = 0 V 80 mS Gate-Source Leakage Current IGSO VGS = -5 V 1 10 µA Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 0.2 mA 0.7 1.0 1.3 V Gate-Source Breakdown Voltage |VBDGS| IGS = 0.2 mA 12.0 14.0 V Gate-Drain Breakdown Voltage |VBDGD| IGD = 0.2 mA 14.5 16.0 V Thermal Resistivity θJC VDS > 3V 280 °C/W Note: 1 TAmbient = 22°C; RF specifications measured at f = 12 GHz using CW signal on a sample basis 1 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com FPD200 Datasheet v3.0 1 ABSOLUTE MAXIMUM RATING : PARAMETER SYMBOL TEST CONDITIONS ABSOLUTE MAXIMUM 6 Drain-Source Voltage VDS -3V < VGS < -0.5V 8V Gate-Source Voltage VGS 0V < VDS < +8V -3V Drain-Source Current IDS For VDS < 2V IDSS Gate Current IG Forward or reverse current 10mA RF Input Power PIN Under any acceptable bias state 20dBm Channel Operating Temperature TCH Under any acceptable bias state 175°C Storage Temperature TSTG Non-Operating Storage -65°C to 150°C Total Power Dissipation PTOT See De-Rating Note below 0.5W Comp. Under any bias conditions 5dB 2 or more Max. Limits 80% Gain Compression 4 Simultaneous Combination of Limits Notes: 1 TAmbient = 22°C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power 3 Total Power Dissipation to be de-rated as follows above 22°C: PTOT= 500mW - (3.6mW/°C) x THS where THS= heatsink or ambient temperature above 22°C Example: For a 85°C carrier temperature: PTOT = 500 - (3.6mW x (85 – 22)) = 0.27W 4 Users should avoid exceeding 80% of 2 or more Limits simultaneously 5 Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib. 6 Operating at absolute maximum VD continuously is not recommended. If operation at 8V is considered then IDS must be reduced in order to keep the part within it's thermal power dissipation limits. Therefore VGS is restricted to < -0.5V. PAD LAYOUT: PAD DESCRIPTION PIN COORDINATES (µm) A Gate Pad 90, 200 B Drain Pad 320, 200 C1/C2 Source Pad 200, 290/110 C1 B A C2 Note: Co-ordinates are referenced from the bottom left hand corner of the die to the centre of bond pad opening DIE SIZE (µm) DIE THICKNESS (µm) MIN. BOND PAD OPENING (µm x µm ) 400 x 400 75 70 x 80 2 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com FPD200 Datasheet v3.0 TYPICAL MEASURED PERFORMANCE : FPD200 Biased @ 5V, 27mA FPD200 Biased @ 8V, 27mA 35 S21 30 MSG (dB) 35 25 20 MSG S21 25 20 & 15 Mag S21 10 15 10 5 5 0 0 0.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26 Frequency (GHz) 2.5 Associated Gain and N.F.min vs Frequency Biased @ 3V, 27mA 0.5 18.0 17.0 16.0 15.0 Frequency (GHz) 14.0 2.0 0 Frequency (GHz) TYPICAL WAFER DISTRIBUTIONS: Note: Data taken from a typical wafer at ambient temperature. Future wafers may have nominal values anywhere within the specifications range. LSL = 0.045 A 5000 Mean StDev N LSL= -1.3 V 3000 USL = 0.075 A 0.06103 0.003473 23955 USL = -0.7 V Mean StDev N 2500 -0.8820 0.02686 23867 4000 Frequency Frequency 2000 3000 2000 1500 1000 1000 500 0 0.040 0.045 0.050 0.055 0.060 0.065 IDSS (A) 0.070 0.075 0.080 0 -1.3 -1.2 -1.1 -1.0 VP (V) -0.9 -0.8 -0.7 3 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com N.F.min (dB) 1 10.0 8.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 9.0 10.0 8.0 7.0 6.0 5.0 4.0 0 3.0 8.0 12.0 13.0 0.5 1.5 12.0 1 10.0 2 14.0 11.0 12.0 16.0 9.0 1.5 2.5 10.0 2 14.0 18.0 8.0 16.0 3 Associated Gain (dB) 2.5 3.5 Gain (dB) N.F.min 20.0 3 18.0 2.0 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26 Frequency (GHz) 22.0 3.5 Gain (dB) N.F.min 20.0 6.5 Associated Gain and N.F.min vs Frequency Biased @ 5V, 27mA N.F.min (dB) Associated Gain (dB) 22.0 4.5 7.0 6.5 6.0 4.5 5.0 2.5 4.0 0.5 3.0 Mag S21 & MSG (dB) 30 MSG FPD200 Datasheet v3.0 NOISE PARAMETERS : HANDLING PRECAUTIONS: (Biased @ VDS=3V, IDS=27mA) Freq N.F.min Rn/50 (GHz) (dB) 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 0.32 0.41 0.52 0.55 0.62 0.78 0.87 1.00 1.08 1.20 1.28 1.37 1.55 1.70 1.85 1.99 0.31 0.31 0.29 0.28 0.26 0.26 0.26 0.25 0.24 0.24 0.24 0.24 0.22 0.20 0.20 0.19 0.75 0.71 0.74 0.62 0.63 0.54 0.48 0.43 0.41 0.41 0.34 0.28 0.24 0.23 0.24 0.17 6.70 14.60 22.60 27.90 34.90 41.50 47.50 54.40 60.20 65.70 78.60 89.70 95.90 103.70 113.50 137.10 18.00 2.09 0.18 0.20 156.80 To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 0 (0-250 V) as defined in JEDEC Standard No. 22-A114. Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. Gamma Opt. (Ohms) Mag Angle APPLICATION NOTES & DESIGN DATA: Application Notes and design data including Sparameters, noise parameters and device model are available on request DISCLAIMERS: This product is not designed for use in any space based or life sustaining/supporting equipment. ORDERING INFORMATION: PREFERRED ASSEMBLY INSTRUCTIONS: GaAs devices are fragile and should be handled with great care. Specially designed collets should be used where possible. PART NUMBER DESCRIPTION FPD200 Die The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280-290°C; maximum time at temperature is one minute. The recommended wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm) gold wire. Stage temperature should be 250-260°C. 4 Tel: +44 (0) 1325 301111 Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: [email protected] Website: www.filtronic.com