300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 FEATURES z z z z z z z z z z z Low dropout voltage: 180mV at 300mA (Vo=3.3V) Quiescent current: Typ. 65µA 2% Voltage Accuracy High PSRR: 70dB at 1KHz Thermal Shutdown Current Limiting Excellent line and load regulation Fast response Short circuit protection Low temperature coefficient Space saving SOT23-3L package The FSP2130 series of positive voltage linear regulators feature low quiescent current (Typ. 65µA) and low dropout voltage, making them ideal for battery powered applications. Their high PSRR make them useful in applications where AC noise on the input power supply must be suppressed. Space saving SOT23-3L package is attractive for portable and handheld applications. They have both thermal shutdown and a current limit feature to prevent device failure from extreme operating conditions. They are stable with an output capacitor of 2.2µF or greater. APPLICATIONS z z z z z z z Cordless phones Cellular phones Bluetooth earphones Digital Cameras Portable electronics WLANs MP3 players PIN CONFIGURATION GENERAL DESCRIPTION (Top View) 1 3 2 1/11 PIN DESCRIPTION Pin Number Pin Name Pin Function 1 2 3 GND VOUT VIN Ground Output Input BLOCK DIAGRAM 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL APPLICATIONS CIRCUITS ABSOLUTE MAXIMUM RATINGS Parameter Input Supply Voltage Output Current Rating +6 300 Unit V mA Output Pin Voltage GND-0.3 to VIN+0.3 V ESD Rating Class B Internal Power Dissipation 400 mW Junction to Case Thermal Resistance (θJC) 130 ℃/ W Junction to Ambient Thermal Resistance (θJA) 250 ℃/ W Operating temperature -40 to 85 °C Operating Junction Temperature -40 to 125 °C Storage Temperature -65 to 150 °C Lead Temperature (Soldering, 5 sec) 300 Note: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 2/11 2007-4-19 °C 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 ELECTRICAL CHARACTERISTICS (VIN = VO + 1V, CIN = 1µF, CO = 2.2µF, TA= 25°C unless otherwise specified.) PARAMETER SYMBOL Input Voltage Output Voltage Accuracy Output Current Ground Current Quiescent Current VIN VO IO IGND IQ Line Regulation LNR Load Regulation Error Temperature Coefficient Over Temperature Shutdown Over Temperature Hystersis LDR TC OTS OTH Power Supply Ripple Rejection (with bypass Cap.) PSRR Power Supply Ripple Rejection (without bypass Cap.) PSRR Dropout Voltage VDO Output Noise Vn TEST CONDITIONS MIN IO= 1mA Note1 -2 300 IO= 1mA to 300mA IO= 0mA IO= 1mA, VO < 2V VIN =2.8V to 3.8V IO= 1mA, 2≤ VO < 3.3V VIN =VO + 0.5V to VO + 1V IO= 1mA, VO ≥3.3V VIN =VO + 0.5V to VO + 1V IO = 1mA to 300mA IO = 1mA IO = 1mA IO = 1mA IO = 100mA f=100Hz CBYP = 10nF f= 1KHz Vo =1.8V f= 10KHz IO = 100mA Vo =1.8V IO = 300mA f=100Hz f= 1KHz f= 10KHz VO= 1.8V 2.5 ≤ VO < 3.3V VO ≥ 3.3V CBYP =10nF, f = 10Hz to 100kHz TYP MAX UNIT V % mA 70 65 5.5 +2 Note2 90 90 -0.15 0.1 0.15 -0.1 0.03 0.1 -0.4 0.2 0.4 -1 0.2 40 150 30 70 70 1 50 %/V % ppm/°C °C °C 50 70 60 40 850 370 180 µA µA dB 1100 450 230 mV µVRMS Note 1：The minimum input voltage of the FSP2130 is determined by output voltage and dropout voltage. The minimum input voltage is defined as: VIN(MIN)=VO+VDROP Note 2：Output current is limited by PD, maximum IO=PD/(VIN(MAX)-VO) 3/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 APPLICATION INFORMATION Capacitor Selection and Regulator Stability Similar to any low dropout regulator, the external capacitors used with the FSP2130 must be carefully selected for regulator stability and performance. Using a capacitor, CIN, whose value is ＞1μF at the FSP2130 input pin, the amount of the capacitance can be increased without limit. Please note that the distance between CIN and the input pin of the FSP2130 should not exceed 0.5 inch. Ceramic capacitors are suitable for the FSP2130. Capacitors with larger values and lower ESR provide better PSRR and line-transient response. The FSP2130 is designed specifically to work with low ESR ceramic output capacitors in order to save space and improve performance. Using an output ceramic capacitor whose value is ＞2.2μF with ESR＞5mΩ ensure stability. A 10nF bypass capacitor connected to BYP pin is suggested for suppressing output noise. The capacitor, in series connection with an internal 200kΩ resistor, forms a low-pass filter for noise reduction. Increasing the capacitance will slightly decrease the output noise, but increase the start-up time. Load Transient Considerations The figure11 shows the FSP2130 load transient response. It shows two components the output response: a DC shift from the output impedance due to the load current change and transient response. The DC shift is quite small due to excellent load regulation of the FSP2130. The transient spike, resulting from a step change in the load current from 1mA to 300mA, is 20mV. The ESR of the output capacitor is critical to the transient spike. A larger capacitance along with smaller ESR results in a smaller spike. Internal P-Channel Pass Transistor The FSP2130 features a 0.75Ω P-Channel MOSFET device as a pass transistor. The P-MOS pass transistor enables the FSP2130 to consume only 65μA of ground current during low dropout, light load, or heavy load operations. This feature increases the battery operation life time. Dropout Voltage A regulator’s minimum dropout voltage determines the lowest usable supply voltage. The FSP2130 has a typical 300mV dropout voltage. In battery powered systems, this will determine the useful end-of-life battery voltage. Current Limit and Short Circuit Protection The FSP2130 features a current limit, which monitors and controls the gate voltage of the pass transistor. The output current can be limited to 400mA by regulating the gate voltage. The FSP2130 also has a built-in short circuit current limit. Thermal Considerations Thermal protection limits power dissipation in the FSP2130. When the junction temperature exceeds 150℃, the OTP (Over Temperature Protection) starts the thermal shutdown and turns the pass transistor off. The pass transistor resumes operation after the junction temperature drops below 120℃. For continuous operation, the junction temperature should be maintained below 125℃. The power dissipation is defined as : PD=(VIN-VOUT)*IO+VIN*IGND The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surrounding airflow and temperature difference between junction and ambient. The maximum power dissipation can be calculated by the following formula: PD(MAX)=(TJ(MAX)-TA)/θJA Where TJ(MAX) is the maximum allowable junction temperature 125℃. TA is the ambient temperature and θJA is the thermal resistance from the junction to the ambient. For example, θJA is 250℃/W for the SOT23-3L package, based on the standard JEDEC 51-3 for a single layer thermal test board. The maximum power dissipation at TA=25℃ can be calculated by the following formula: PD(MAX)= (125℃-25℃)/250=0.4W It is also useful to calculated the junction temperature of the FSP2130 under a set of specific conditions. In this example let the input voltage VIN=3.3V, the output current IO=300mA and the case temperature TA=40℃ measured by a thermal couple during operation. The power dissipation for the VO=2.8V version of the FSP2130 can be calculated as: PD=(3.3V-2.8V)*300mA+3.3V*70μA≌150mW And the junction temperature, TJ, can be calculated as follows: TJ=TA+PD*θJA TJ=40℃+0.15W*250℃/W =77.5℃＜TJ(MAX) =125℃ For this operating condition, TJ, is lower than the absolute maximum operating junction temperature, 125℃, so it is safe to use the FSP2130 in this configuration. 4/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL PERFORMANCE CHARACTERISTICS (VIN = VEN , CIN = 1µF, CO = 2.2µF , CBYP =10nF TA = 25°C unless otherwise specified.) 5/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL PERFORMANCE CHARACTERISTICS（CONTINUED） (VIN = VEN , CIN = 1µF, CO = 2.2µF , CBYP =10nF TA = 25°C unless otherwise specified.) 6/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL PERFORMANCE CHARACTERISTICS（CONTINUED） (VIN = VEN , CIN = 1µF, CO = 2.2µF , CBYP =10nF TA = 25°C unless otherwise specified.) 7/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL PERFORMANCE CHARACTERISTICS（CONTINUED） (VIN = VEN , CIN = 1µF, CO = 2.2µF , CBYP =10nF TA = 25°C unless otherwise specified.) 8/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 TYPICAL PERFORMANCE CHARACTERISTICS（CONTINUED） (VIN = VEN , CIN = 1µF, CO = 2.2µF , CBYP =10nF TA = 25°C unless otherwise specified.) 9/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 ORDERING INFORMATION FSP2130XXXX Package Type: C: SOT23-3L Output Voltage: 40: 4.0V 38: 3.8V 33: 3.3V 31: 3.1V 30: 3.0V 29: 2.9V 285: 2.85V 28: 2.8V 25: 2.5V 18: 1.8V Temperature Grade: Packing: A: Tape & Reel D: -40~85℃ MARKING INFORMATION XXVYW Date code: Y: Year W; Week Output Voltage: M: 4.0V O: 3.8V K: 3.3V P: 3.1V J: 3.0V Q: 2.9V I: 2.85V H: 2.8V G: 2.5V E: 1.8V Product Code 10/11 2007-4-19 300MA HIGH PSRR LOW DROPOUT CMOS LINEAR REGULATOR FSP2130 PACKAGE INFORMATION D b Symbol A A1 b D E E1 e1 11/11 2 Dimensions In Millimeters Min. Max. 0.889 1.295 0.000 0.152 0.353 0.599 2.692 3.099 2.591 2.977 1.397 1.803 0.838 1.041 A A1 1 e1 E E1 3 Dimensions In Inches Min. Max. 0.036 0.052 0.000 0.006 0.014 0.024 0.108 0.124 0.104 0.119 0.056 0.072 0.034 0.042 2007-4-19