TI GC1115IZDJ

GC1115
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SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
Crest Factor Reduction Processor
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
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•
Significantly Reduces Signal Peaks to ≥ 6 dB
PAR
One 20-MHz or 2 Independent 10-MHz
Channels
Programmable Output PAR Down to 6 dB
Programmable Cancellation Pulse Coefs
Meets 3GPP TS 25.141 Down to 6 dB PAR
Meets cdma2000 C.S0010 Down to 6 dB PAR
256-ball PBGA Package, 17-mm × 17-mm
1.2-V Core, 3.3 V I/O
3GPP (W-CDMA) Base Stations
3GPP2 (cdma2000) Base Stations
CDMA Multi-Carrier Power Amps (MCPAs)
CFR Reduction of OFDM, HSDPA Signals
Two-Channel Transmit Diversity Applications
Operates with TI DAC5687 (500 Msps)
DESCRIPTION
The GC1115 is a flexible, programmable, wideband crest factor reduction (CFR) processor with a maximum
composite bandwidth of 20 MHz. The GC1115 selectively reduces the peak-to-average ratio (PAR) of wideband
digital signals provided in quadrature (I and Q) format, such as those used in third-generation (3G) code division
multiple access (CDMA) wireless applications. By reducing the PAR of digital signals, the efficiency of follow-on
power amplifiers (PAs) is improved, the D/A converter requirements are eased, and the out-of-band spectral
regrowth caused by simple hard limiting is eliminated.
By including the GC1115, manufacturers of 3G BTS equipment can realize significant savings on power
amplifier costs. The GC1115 meets multi-carrier 3G performance standards (PCDE, composite EVM, and ACLR)
at PAR levels down to 6 dB. The GC1115 integrates easily into the transmit signal chain, between a digital
upconverter such as the Texas Instruments GC5016 or GC5316 and a high-quality D/A converter, such as the
Texas Instruments DAC5675 or DAC5687.
The GC1115 uses four cascaded stages of peak detection and cancellation (PDC) to remove over-threshold
peaks from the input signal. Each PDC stage can be independently programmed with detection target peak
levels and cancellation pulse coefficients. A pool of 32 cancellation pulse generators can be flexibly assigned in
groups of 4 to any PDC stage. Spectrally shaped cancellation pulses are designed using any of the widely
available FIR filter design programs, such as those from MATLAB™, ADS™, etc. Cancellation pulses are
designed to match the user’s carrier frequency allocation. Cancellation pulse energy is bandlimited and thus is
only added within allocated carrier bands. The GC1115’s peak cancellation algorithm does not affect the signal’s
ACLR.
Input sampling rates to 130 Msamp/sec are supported, in either parallel or multiplexed I/Q modes, and in either
twos complement or unsigned format. Output sampling rates to 130 Msamp/sec are supported in either parallel
or multiplexed I/Q modes, and in either twos complement or unsigned format. A special one-channel output
mode uses both GC1115 output ports to carry odd/even real output samples. The GC1115 includes an
interpolator that increases the output sampling rate by 2x or 4x and optionally modulates the output signal to the
fs/4 center frequency. Dual on-chip RAM banks provide either time-domain snapshots or long-term
histogramming of the internal peak cancellation signal chain at five user-selected points, enabling real-time
monitoring of the CCDF function. A power level meter monitors either the GC1115 input or output power level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS is a trademark of Agilent Technologies Inc..
MATLAB is a trademark of The MathWorks Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
GC1115
www.ti.com
SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
FUNCTIONAL BLOCK DIAGRAM
VDD
(40)
VSS
(64)
VDDSHV
(31) VDDA1 VSSA1
VSS1
VDDA2 VSSA2
. .
PLL_
CORE
CORE_CLK
VDD1
PLL_
TX
LOOP
(NC)
IN_CLK
32 Cancellation Pulse Generators
(allocate to PDC Stages in groups of 4)
IN_A[17:0]
IN_B[17:0]
PDC
Stage
1
PDC
Stage
2
PDC
Stage
3
PDC
Stage
4
Interp
2x, 4x
+ fs/4
Soft
Limiter
&
Output
Format
SYNC_A
SYNC_B
Test Signal
Generator
Sync
Control
JTAG[4:0]
Snapshot RAM
Input Selector
Snapshot
RAM A
TEST_MODE
Power
Measurement
.
..
..
.
OUT_IQ_SEL
OUT_A[17:0]
OUT_B[17:0]
SYNC_OUT
CRC
Gen.
Snapshot
RAM B
OUT_CLK
VPP
(NC)
Microprocessor Registers
A[7:0]
D[15:0]
CS
RD
WR
INT
RESET
Related Documents
•
•
•
•
GC1115 Evaluation Module (EVM) User’s Guide
Application Note: GC1115 Configuration for UMTS (W-CDMA) Base Stations
Application Note: GC1115 Configuration for 3GPP2 (cdma2000) Base Stations
Matlab code for cancellation pulse design
ORDERING INFORMATION
2
TA
PACKAGE
DEVICE
-40°C to 85°C
256-PBGA Plastic Ball Grid Array
GC1115IZDJ
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GC1115
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SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
INTRODUCTION
Figure 1 shows the typical usage of the GC1115 crest factor reduction processor in the transmit signal chain of a
wireless base station.
GC5016,
GC5316,
or
other DUC
GC1115
D/A
RF
upconversion
PA
Microproc.
or
TI DSP
Figure 1. Wireless System Using the GC1115
The GC1115 is initialized and controlled using an 8-bit address (A) and a 16-bit data (D) bus. These pins, along
with the read (RD), write (WR), and chip select (CS) pins, allow users to modify the control registers of the
GC1115.
Signals are provided to the GC1115 using two 18-bit input ports, IN_A[17:0] and IN_B[17:0], which are typically
driven by a digital upconverter such as the GC5016, GC5316, or similar. The GC1115 can accept either one or
two input channels.
When the GC1115 is configured to process two input channels, IN_A[17:0] carries channel 0’s multiplexed I & Q
samples, while IN_B[17:0] carries channel 1’s multiplexed I & Q samples. The GC1115 output samples are
provided to a D/A converter using two 18-bit output ports, OUT_A[17:0] and OUT_B[17:0]. The GC1115 output
may appear on one or both output ports, depending on which output mode (real or complex; parallel or
multiplexed; odd-even) is selected.
NOTE:
The D/A converter must not use the GC1115’s OUT_CLK signal. OUT_CLK is for
test purposes only. OUT_CLK’s phase is not aligned with the data on the OUT_A and
OUT_B ports. OUT_CLK may contain jitter in excess of that required to clock
high-speed D/A converters.
Why Cancel Peaks?
The purpose of the GC1115 is to lower the peak-to-average ratio (PAR) of composite digital communication
signals. Specifically, wideband code division multiple access (W-CDMA) and orthogonal frequency division
multiplexed (OFDM) signals have high peak-to-average ratios (PARs) ranging from 10 dB to 15 dB. After D/A
conversion, a power amplifier (PA) amplifies the resulting analog signal. In order to accommodate the high PAR
of W-CDMA and OFDM signals, the peak signal level must be at or below the 1 dB compression point of the PA,
which is usually accommodated by backing off the input drive to the power amplifier.
Figure 2 illustrates the effects of a decrease in peak-to-average ratio on a PA’s Vin vs Vout graph.
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Vout
7 dB
output PAR
GC1115
provides
6 dB peak
reduction
1 dB Compression Point
(maximum output)
Input Signal
Average Power
(0 dB Point)
PA efficiency before GC1115:
Avg PA output (10 W )
= 8%
DC power (125 W)
13 dB
input PAR
Vin
Figure 2. Reducing the Peak-to-Average Ratio (PAR)
However, since the peak-to-average ratio of CDMA signals is so high, the average power is relatively low,
consequently resulting in a low PA efficiency (output power divided by input power). By decreasing the
peak-to-average ratio, the average power of the peak-reduced signal at the output of the GC1115 can be
increased, decreasing PA back-off thus also increasing PA efficiency.
Figure 3 illustrates that the decrease in PAR can then be used to increase the average signal power while still
keeping the peaks below the PA’s 1 dB compression point. The GC1115 can typically limit the output PAR of
CDMA signals to between 6 dB and 7 dB while still meeting all relevant 3GPP or 3GPP2 requirements. This
decreased PAR enables a 2 dB to 3 dB increase in PA drive, which in turn allows PA manufacturers to achieve
2 dB to 3 dB more PA output power. As PAs represent a significant percentage of the capital equipment cost of
base stations, using a 10 W PA instead of a 20 W PA (for example) significantly decreases base station costs.
V out
7 dB
output PAR
6 dB less
PA back −off
Input Signal
Average Power
1 dB Compression Point
(maximum output)
PA efficiency after GC1115:
Output Signal
Average Power
Avg PA power (20 W)
DC power (125 W)
13 dB
input PAR
V in
Figure 3. Increasing PA Efficiency
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= 16%
GC1115
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How Peak Cancellation Works: Time Domain View
Figure 4 provides a time-domain example of GC1115 operation. Figure 4 shows the magnitude of the complex
input signal in blue, and the magnitude of the complex, peak-reduced signal (after GC1115 processing) in red.
[Note: for users who print this data sheet on a black-and-white printer, the input signal is a solid line, while the
output signal is a finely dotted line.] Notice that for most of the 130 samples in this example, the red output
waveform is identical to the blue input waveform. However, the GC1115 has reduced the magnitude of samples
around two peaks (one at sample 63, one at sample 95) that exceed the detection threshold. The aqua-colored
waveform above the gain threshold line demonstrates the magnitude of the cancellation pulse that was
subtracted from the complex input waveform. Notice that the GC1115’s PDC stages each have two independent
thresholds:
1. Detection threshold: interpolated peaks above the detection threshold are candidates for cancellation
2. Target peak level: detected peaks will be reduced to the target peak level, assuming cancellation resources
are available
Independent detection and target peak levels allow the GC1115 greater flexibility in peak reduction processing.
4
7
x 10
Detection Threshold
6
Target Peak Level
5
4
3
2
1
0
0
20
40
60
80
100
120
140
Figure 4. Peak Cancellation Example: Time Domain
How Peak Cancellation Works: Frequency Domain View
Figure 5 demonstrates the frequency-domain effects of peak cancellation. In Figure 5, the original signal’s
frequency response is shown in blue. The output signal’s frequency response looks identical and is not shown.
The yellow (8 dB PAR), red (7 dB PAR), green (6 dB PAR), and black (5 dB PAR) curves show the spectra of
just the added signal (GC1115 input – GC1115 output) to achieve peak reduction. The difference between the
input and output signals is the signal distortion. [Note: for users who print this data sheet on a black-and-white
printer, the input spectrum is a solid line, while the output spectra are finely dotted lines.] Note that the distortion
is not significant in the spectral response:
1. The out-of-band energy of the distortion added by the GC1115 during peak cancellation is 70 to 80 dB
below the signal and hence is not an issue. The out-of-band energy is only a weak function of the target
PAR level.
2. The amount of in-band distortion energy rises with decreasing output PAR. This is to be expected, because
lower PAR thresholds result in more peaks being canceled. Lower PAR levels require more energy to cancel
the peaks, thus increasing the distortion level.
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The GC1115 reduces the amplitude of peaks in a way that keeps the out-of-band (ACLR) energy well below
required levels. Users can determine how much in-band distortion is acceptable by monitoring the effects of
peak cancellation at a given output PAR, using two key in-band distortion metrics for CDMA signals:
1. peak code domain error, or PCDE, and
2. composite error vector magnitude, or EVM
Various CFR signal quality metrics (ACLR, PCDE, EVM, CCDF) will be further discussed in a subsequent
section.
Power spectral density: input (blue) & distortion (red)
100
80
Input Spectrum
60
Distortion Spectrum,
5 dB Output PAR
40
Distortion Spectrum,
8 dB Output PAR
20
0
−20
−4
−3
−2
−1
0
1
2
3
4
x 10
7
Figure 5. Spectral View of Distortion
SUMMARY OF GC1115 FEATURES
Refer to the GC1115 functional block diagram for the following discussion.
The GC1115 removes peaks from an input signal stream by subtracting user-designed, spectrally shaped
cancellation pulses from detected peaks in the input waveform that are above a user-specified detection
threshold. The cancellation pulse’s spectral shape matches that of the GC1115 input signal’s single- or
multi-carrier configuration. This cancellation pulse design methodology ensures that energy is only added into
frequency bands where signal energy is located, minimizing out-of-band energy that could otherwise increase
ACLR/ACPR.
Cancellation pulses may be real or complex. Real cancellation pulses are used when the input signal spectrum
is symmetric, while complex cancellation pulses are used when the input signal spectrum is asymmetric. A
single cancellation pulse reduces the peak amplitude of multiple samples around each signal peak while
maintaining both the in-band (PCDE, cEVM) and out-of-band (ACLR) signal quality requirements. Peaks are
cancelled to a user-specified level, which is called the output peak-to-average ratio, or PAR. The GC1115
provides four sequential peak detection and cancellation (PDC) stages to remove peaks. The PDC stage
thresholds are normally set so that earlier stages remove the largest peaks, while later stages remove smaller,
remaining peaks.
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During peak detection, an effective 256x oversampling process identifies the exact magnitude and location of
interpolated peaks. In other words, the interpolated waveform approximates the output of the follow-on D/A
converter. The interpolated waveform can therefore have a larger amplitude than any of the D/A’s individual
input samples. The GC1115’s effective 256x oversampling allows both the magnitude and the location of peaks
(after D/A conversion) to be predicted prior to the actual D/A conversion process. If the magnitude of the
interpolated peak is above the detection threshold of the PDC stage, the peak is a candidate for peak
cancellation. Detected peaks are always cancelled, unless all of the cancellation resources assigned to a given
stage are already busy. When all of a PDC stage’s cancellation resources are already busy canceling other
peaks, subsequent PDC stages will again detect and cancel the missed peak, if that stage’s resources allow.
The GC1115 contains a total of 32 cancellation pulse generators (also called cancelers) per channel that are
allocated in groups of four to PDC stages. The normal allocation of the 32 cancelers is as follows:
• PDC Stage 1 uses 4 cancelers
• PDC Stage 2 uses 8 cancelers
• PDC Stage 3 uses 12 cancelers
• PDC Stage 4 uses 8 cancelers
The allocation of cancelers should correspond to the detection threshold (DETECT_TSQD) for each PDC Stage.
A PDC stage with a lower detection threshold will find more peaks than a PDC stage with a higher detection
threshold. As mentioned above, the detection threshold for PDC stages 1 and 2 is set to detect and cancel the
largest peaks (typically those above 8 or 9 dB PAR), while PDC stages 3 and 4 detect and cancel peaks at the
desired output PAR (typically between 6 and 8 dB). Since the largest peaks are the ones that would cause the
most distortion in the PA if they were not cancelled, setting the detection threshold higher in PDC Stages 1 and
2 ensures that the large peaks will be canceled.
Cancellation pulse coefficients are stored in special GC1115 RAM blocks. The GC1115 RAM blocks can store
up to 256 real or 128 complex cancellation pulse coefficients and their associated first and second derivatives.
Cancellation coefficients are signed, 12-bit integer value between –2048 and +2047. Each cancellation
coefficient RAM supports up to four cancelers. Cancellation pulse generator RAMs assigned to the same stage
normally contain the same coefficients, but each of the GC1115’s eight cancellation RAMs may contain different
coefficients. The cancellation pulse coefficients are normalized, i.e. the largest coefficient magnitude is always
+2047 (1.0). However, both the magnitude and the phase of the normalized cancellation pulses are adjusted
before the cancellation pulse is added to the input waveform during peak cancellation, ensuring proper
alignment with the samples of the input signal.
While the subtraction of cancellation pulses reduces the peak amplitude in the region immediately surrounding a
detected peak, this subtraction may also introduce new, smaller, over-threshold peaks away from the region of
the peak. This phenomenon is called peak regrowth. Peak regrowth is an infrequent phenomenon whose effects
are mitigated by using four serial PDC stages. If Stage N causes peak regrowth, Stage N+1 and subsequent
stages will detect and cancel the regrowth peaks, assuming the PDC stages have available pulse cancelers.
Regrowth peaks, when they occur, are usually just a few percent (or less) over the PAR threshold.
Following the four PDC stages, the GC1115 also contains an interpolator and a soft limiter. When enabled, the
interpolator supports 2x real, 2x complex, and 4x real interpolation. The real output modes also modulate the
signal by fs/4. The soft limiter acts as a fixed-length AGC that optionally attenuates the input signal over a
fixed-length window of up to 33 samples surrounding the detected over-threshold peak. Under nearly all
circumstances, the soft limiter should be bypassed.
The GC1115 operates most efficiently when there are at least 2.5 complex samples per Hertz of bandwidth. For
example, a four-carrier (20 MHz) 3G stack should be sampled at no less than 50 Msamp/sec, while a
single-carrier 3G system can be sampled as low as 12.5 Msamp/sec. Under certain circumstances, the input
signal can be represented using as few as 2.0 complex samples per Hz.
The GC1115 contains two flexible, user-programmable snapshot RAMs. The snapshot memories operate either
in capture or in histogram mode. In the capture mode, 1024 consecutive I and Q samples are stored in one of
the snapshot RAMs. During capture mode, 32 bits per complex sample (16 bits I, 16 bits Q) are captured. The
lower 2 LSBs of each real and imaginary 18-bit sample are dropped.
Each of the two snapshot RAMs receives samples from one of five user-selected test probe points:
1. At the GC1115 input
2. After PDC Stage 1
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3. After PDC Stage 2
4. After PDC Stage 3
5. After PDC Stage 4
When operating in histogram mode, the snapshot RAMs generate a histogram of the real part, the imaginary
part, or the power of each complex sample. In histogram mode, millions of samples can be characterized using
the snapshot RAM’s 32-bit bin counters, thus providing a statistically significant number of events for CCDF and
related magnitude distribution measurements.
Each of the GC1115’s PDC stages can be bypassed by clearing a corresponding bit in the CONTROL register.
Although bypassing a stage removes that stage’s peak cancellation capability, it also removes the latency
introduced by the peak detection and cancellation process itself, and reduces power consumption as well.
The GC1115 includes an on-chip test signal generator that can create DC levels, sawtooth waveforms, and a
filtered random number generator with Gaussian-like peak-to-average statistics (i.e. approximately 10 dB PAR).
In conjunction with a CRC generator, the test signal generator can be used to verify proper, expected behavior
of the GC1115 without applying an input signal to the GC1115 IN_A and IN_B ports. The CRC generator
processes the GC1115 output samples and generates a periodic, 16-bit checksum. Since both the test signal
generator and the CRC generator can be synchronized to the same sync source, the presence of a predictable,
periodic value in the CRC register indicates that the GC1115 internal circuitry is operating as expected. TI
provides several GC1115 configurations (starting test generator register values, sample periods, and expected
CRC value at the end of each period) that enable GC1115 users to test for proper GC1115 internal operation.
The test signal generator can also be used without the CRC generator, providing a suite of general-purpose test
signals (DC, sawtooth, pseudo-LFSR) to exercise ICs attached to the GC1115 output ports, OUT_A and
OUT_B.
CFR PERFORMANCE METRICS FOR CDMA SIGNALS: CCDF, ACLR, PCDE, cEVM
The GC1115 reduces peaks by subtracting spectrally shaped waveforms from detected peaks in the input signal
whose interpolated magnitude is above a user-specified output PAR threshold. Researchers in peak reduction
techniques use a graph called the complementary cumulative distribution function, or CCDF, to display the
probability that a particular sample has a given magnitude. The x-axis of a CCDF curve begins at 0 dB, defined
as the average power of the signal, and extends to the peak value of the waveform. The y-axis of a CCDF curve
lists the probability (usually on a log scale) that a given complex sample has a certain magnitude. Plotting the
before and after CCDF curves on the same graph demonstrates that the GC1115 peak reduction algorithms
have achieved their primary purpose: reducing peaks to a user-specified level. In Figure 6, the input CCDF
curve is shown in blue and the output CCDF curve (after GC1115 peak reduction) is shown in red.
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Complementary Cumulative Distrib
Function
2
10
1
10
CCDF Curve
After Peak
Reduction
0
10
% of
samples
−1
10
−2
10
CCDF Curve
Before Peak
Reduction
−3
10
−4
10
0
2
4
6
8
10
12
Sample Power (mean sample power = 0
14
Figure 6. Example Complementary Cumulative Distribution Function (CCDF)
Because the GC1115 modifies samples of the input waveform during peak reduction, the peak reduction
process introduces certain distortions. The nature of these distortions is well understood and is under the user’s
control. GC1115 users have great flexibility in determining the overall distortion level. Distortion can be
quantified in several ways:
• By analyzing the spectrum of the distortion (input–output) signal
• By analyzing the out-of-band output noise level in neighboring channels (also called the adjacent channel
leakage ratio, or ACLR)
• By measuring a composite error vector magnitude (cEVM) level
• By determining the interference level (caused peak reduction) in the CDMA code noise floor; this metric is
called the peak code domain error, or PCDE
• By monitoring bit error rate (BER) at the receiver
The two dominant 3G standards, W-CDMA (3GPP) and cdma2000 (3GPP2), have developed a set of
standardized requirements for ACLR, cEVM, and PCDE. Because a wide variety of valid CDMA waveforms
exist, the 3G standards bodies have also specified a set of test waveforms called test models to verify all
elements in the downlink signal processing chain. Test models also allow BTS developers to compare the
performance of competing signal processing devices, including crest factor reduction processors, on identical
input signals.
Texas Instruments quantified GC1115 behavior with extensive 3G Test Model 1, Test Model 3, and Test Model
5 signals, and in both single-carrier and multi-carrier configurations. For all tests, TI measured the following
parameters:
• CCDF
• ACLR
• PCDE
• CEVM
The following paragraphs review the relevant 3G requirements for these parameters. Subsequent sections
present test results that demonstrate the GC1115’s ability to meet all relevant 3G requirements at output PAR
levels to 6 dB.
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Relevant 3GPP (W-CDMA) Requirements
The GC1115 is designed to meet the following 3GPP specifications. The Test Models used to verify these
specifications are described in 3GPP TS 25.141, Section 6.1.1 of Release 6 (2002-12).
• ACLR: At least 45 dB ACLR at 5 MHz below the first (or above the last) active W-CDMA carrier in the band,
and at least 50 dB ACLR at 10 MHz below the first (or above the last) active W-CDMA carrier in the band,
(TS 25.141, Section 6.5.2.2), using Test Model 1.
– NOTE: The GC1115 supports > 70 dB ACLR using 85-tap cancellation pulses or longer.
• EVM: ≤ 17.5% for QPSK modulation (TS 25.141, Section 6.7.1), using Test Model 4.
– NOTE: The GC1115 provides ≤ 17.5% cEVM for all Test Models with output PAR down to 6 dB.
• PCDE: ≤– 33 dB (TS 25.141, Section 6.7.2), using Test Model 3.
– NOTE: The GC1115 provides ≤ -33 PCDE for all Test Models with output PAR down to 6 dB.
• Spurious emissions: various (TS 25.141, Section 6.5.3), using Test Model 1.
Relevant cdma2000 Requirements
Ref. 3GPP2 C.S0010-A (March 30, 2001):
• Section 4.2: Modulation Requirements (Rho – waveform quality)
• Section 4.3: RF Output Power Requirements
• Section 4.4: Limitations on Emissions
SUMMARY OF GC1115 PERFORMANCE USING 3G TEST MODEL SIGNALS
Table 1. 3GPP PCDE and Composite EVM Performance
3G Test Signal
# of cxrs
PCDE (Spec: < -33 dB)
Composite EVM (Spec: < 17.5%)
8 dB
7 dB
6 dB
5.7 dB
8 dB
7 dB
6 dB
TM1_64
1
–52.0
–46.6
–41.9
–41.0
3.0%
5.3%
8.4%
5.7 dB
9.9%
TM1_64
2
–50.4
–46.5
–41.7
–40.5
3.1%
5.7%
8.9%
10.5%
TM1_64
4
–51.4
–46.8
–41.3
–40.0
2.5%
5.0%
8.5%
9.9%
TM3_32
1
–46.8
–38.6
–35.9
–34.5
4.3%
7.4%
10.4%
11.9%
TM3_32
2
–44.0
–40.1
–35.8
–35.1
5.5%
8.1%
12.4%
12.9%
TM3_32
4
–47.6
–41.8
–38.2
–36.2
4.5%
7.2%
10.7%
12.6%
Test Conditions:
a. Each simulation processed 614,400 input samples (one 10 msec frame at 61.44 Msamp/sec)
b. PCDE and composite EVM were measured using a Rohde & Schwarz FSU
c. Cancellation pulse lengths varied from 75 to 181
d. ACLR depends mostly on cancel pulse length. Cancel pulse lengths of 85 achieve –70 dB ACLR for
four-carrier UMTS signals. Cancel pulse lengths of 115 achieve –70 dB ACLR for single-carrier UMTS
signals.
e. Multi-carrier Test Model signals used frames that were staggered by 2 msec between carriers
f. Stages 1 thru 4 were assigned 4, 8, 12, and 8 cancelers, respectively (total of 32 cancelers).
g. For PAR = 7 dB, Stages 1 thru 4 used detection thresholds of 8, 7, 7, and 7 dB, respectively.
h. For PAR = 6 dB, Stages 1 thru 4 used detection thresholds of 8, 7, 6, and 6 dB, respectively.
i. For PAR = 5 dB, Stages 1 thru 4 used detection thresholds of 8, 6, 5, and 5 dB, respectively.
RESET
The GC1115 supports three kinds of reset:
1. PLL reset (only the PLLs are reset)
2. Hardware reset (all configuration registers are brought to their RESET values)
3. Datapath hardware reset
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Setting specific bits in the RESET register activates these resets. Asserting the RESET pin of the GC1115 also
causes hardware reset. Hardware reset results in the following GC1115 conditions:
• All input pins are put in their high-impedance state
• All output pins are put in their high-impedance state
• All internal registers are reset to their RESET states
• All state machines are placed in their initial (idle) states
• No config registers can be modified before clearing the config reset.
GC1115 Initialization Sequence
The GC1115 initialization sequence requires the following register groups to be properly initialized:
1. RESET, PLL_CONTROL, CLK_CONTROL, IO_CONTROL
2. CONTROL, IO_MODE, DECIMATE, RESOURCE_MASK, DELAY_MASK
3. SYNC registers
4. TSQD detection threshold and target peak level registers
5. INTERP registers
6. OUT_GAIN, OUT_OFFSET
7. CANCEL_MODE, CANCEL_LENGTH, CANCEL_DELAY, cancellation coefficients
The following paragraphs describe in general terms how each of these registers is initialized to achieve the
desired user-specified peak reduction performance.
RESET, PLL_CONTROL, CLK_CONTROL, IO_CONTROL
The RESET register contains four bits that can individually reset:
• The memory-mapped registers
• The GC1115 internal datapath
• The “core” PLL
• The output PLL
At GC1115 startup, hardware RESET always precedes all other register accesses and this asserts all internal
reset registers. Configuration control reset must also be cleared before performing subsequent configuration
steps.
After the RESET bits have been asserted, the PLL_CONTROL and CLK_CONTROL registers should be
initialized to the desired values. The GC1115 normally operates at four times the input sample rate, while the
output clock rate is determined by several additional factors (decimation, interpolation, and output format and
mode). The CLK_CONTROL register determines the PLL multiplying factors that control the GC1115 core clock
and output clock frequencies. Finally, the IO_CONTROL register determines the input and output format (twos
complement or unsigned), the output enabled state (tri-stated or enabled), and the output bit width (18, 16, 14,
or 12 bits).
The GC1115 PLLs require a warm-up time of at least 1 µs from PLL_CONTROL modification to PLL reset
release, and at least 100 µs from PLL_CONTROL and CLK_CONTROL modification to PLL reset release before
the internal clock is stable.
CONTROL, IO_MODE, DECIMATE, RESOURCE_MASK, DELAY_MASK
The CONTROL register contains six control bits that selectively enable or disable the four PDC stages, the
interpolator, and the soft limiter. The DECIMATE register allows users to decimate the input sample stream by 1
(no decimation) or 2. The RESOURCE_MASK register determines which of the eight cancellation pulse SRAMs
are updated with new cancel pulse coefficients when a CANCEL_SYNC event occurs. Similarly, the
DELAY_MASK register determines which of the four PDC stages are affected by changes to the
CANCEL_DELAY register when the DELAY_SYNC event occurs.
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SYNC Registers
The GC1115 contains a group of SYNC registers that control the behavior of thirteen different sync-related
functions. A subsequent section discusses GC1115 synchronization alternatives. This section only describes the
registers that must be properly initialized prior to GC1115 operation. Four datapath SYNC registers
(RCV_SYNC, STAGE_SYNC, DECIM_SYNC, and INTERP_SYNC) must be synchronized by a hardware event
before the GC1115 will process input samples. Four additional ancillary SYNC registers (DELAY_SYNC,
CANCEL_SYNC, RESOURCE_SYNC, and OUTGAIN_SYNC) must be synchronized by a hardware or software
event before the GC1115 properly applies cancellation coefficients and gains. TI recommends that the four
datapath SYNC registers be synchronized using a SYNC_A or SYNC_B hardware event, and that the ancillary
SYNC registers be synchronized using a SW_TRIGGER software event. Note that the SYNC registers must be
initialized BEFORE the corresponding hardware or software event occurs. For example, CANCEL_SYNC must
be initialized before the cancellation coefficients are transferred from the GC1115’s shadow RAM to the internal
canceler RAMs.
TSQD (Threshold) and RESOURCE_CNT Registers
The behavior of each PDC stage is controlled by two threshold registers (DETECT_TSQDx and GAIN_TSQDx)
and one resource (RESOURCE_CNTx) register, where x represents a specific stage (from 1 to 4). These 16-bit
registers contain the scaled threshold-squared values for the stage’s detection threshold and target peak level.
The 16-bit RESOURCE_CNT registers contain the number of cancellation resources (from 0 to 8) assigned to
the stage. NOTE: if a RESOURCE_CNT register is set to N (0 ≤ N ≤ 8), that PDC stage can cancel up to 4 × N
peaks simultaneously. A resource represents a canceler RAM. Up to four cancellation pulse generators are
supported by each canceler RAM.
INTERP Registers
A programmable output interpolator follows the GC1115’s four PDC stages. The GC1115 interpolator operates
in one of four modes:
• Bypass (the default condition)
• Interpolate by 2 (complex output)
• Interpolate by 2 (real output centered at fs/4)
• Interpolate by 4 (real output centered at fs/4)
The interpolator’s filter coefficients are programmable and must therefore be initialized, even in bypass mode,
before the GC1115 starts processing input samples. A total of 40 interpolator registers (from D0_COEF0 thru
D3_COEF9) must be initialized before the GC1115 processes input data.
OUT_GAIN and OUT_OFFSET Registers
The GC1115 output circuitry includes individual I and Q gain and offset registers that allow users to compensate
for I/Q imbalances in subsequent D/A converters and/or subsequent analog I/Q modulators. Because the
OUT_GAIN and OUT_OFFSET registers are user-programmable, they must be properly initialized before the
GC1115 starts processing input samples. OUT_GAIN registers are normally initialized to 0x2000 (gain of 1.0),
and OUT_OFFSET registers are usually initialized to 0x0000.
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CANCEL_MODE, CANCEL_LENGTH, CANCEL_DELAY, Cancellation Coefficients
The GC1115 applies user-specified cancellation coefficients to detected peaks. Cancellation coefficients can
contain either real or complex values, to support both symmetric and asymmetric input spectra. For this reason,
the CANCEL_MODE, CANCEL_LENGTH, and CANCEL_DELAY registers must be properly initialized before
the GC1115 begins processing input samples. The cancellation coefficients themselves (in either real or
complex format) must be copied to the GC1115 canceler RAMs in a two-step process:
• The microprocessor or FPGA writes the cancellation coefficients to memory-mapped shadow RAM registers
• The shadow RAM registers are copied to one or more (of a total of eight) cancellation pulse SRAMs after a
CANCEL_SYNC event occurs.
The CANCEL_MODE register determines whether the GC1115 is using real or complex coefficients
(corresponding to a symmetric or an asymmetric input spectrum), as well as whether coefficient symmetry is to
be exploited. Coefficient symmetry (mirrored coefficients) only applies when using real coefficients. The
CANCEL_MODE register also contains a four-bit field that indicates a timeout or hysteresis value. A non-zero
timeout value indicates that the PDCs are to examine the envelope of the input signal, rather than the magnitude
of the input signal. TI-provided Matlab cancel pulse design software automatically calculates the timeout value.
The CANCEL_LENGTH register specifies the number of unique cancellation coefficients used to cancel peaks.
The CANCEL_MODE register settings affect the interpretation of CANCEL_LENGTH. The following table
describes how CANCEL_LENGTH and CANCEL_DELAY are used, depending on CANCEL_MODE:
Table 2. Relationship Between CANCEL_MODE, CANCEL_LENGTH,
and CANCEL_DELAY
CANCEL_LENGTH
CANCEL_DELAY
0 (Real, unique coefs)
CANCEL_MODE
N (odd, from 15 to 255)
(N-1)/2
1 (Real, mirrored coefs)
N (odd, from 15 to 255)
N
1 (Complex, unique coefs)
N (odd, from 15 to 127)
(N-1)/2
OPERATING MODES
The GC1115 supports a variety of operating modes that accommodate a range of input formats, number of
channels, and follow-on A/D converter and transmit architectures. Users select a specific input and output
operating mode that depends upon:
• The number of channels (one or two)
• The input sampling rate:
– Up to 130 Msamp/sec in 1-channel mode
– Up to 65 Msamp/sec in 2-channel mode
– Down to 25 Msamp/sec in 1-channel parallel mode
– Down to 12.5 Msamp/sec in 1-channel multiplexed mode, or in 2-channel mode
• The input format (parallel or multiplexed)
• The input decimation factor (1 or 2)
• The output interpolator mode (bypass, 2x real, 2x complex, 4x real)
• The output format (parallel, multiplexed, or odd-even; real or complex)
• The internal GC1115 clock rate (up to 320 MHz)
• The PLL multiplier (1x, 2x, or 4x)
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The following constraints restrict the allowed combinations of the previously listed parameters:
1. Maximum input pin toggling rate: 130 MHz
2. Maximum output pin toggling rate in single-ended mode: 130 MHz
3. Maximum internal GC1115 clock rate: 305 MHz (IN_CLK x1, x2, x4)
4. Minimum PLL-driven internal GC1115 clock rate (at divide-by-1 PLL output): 100 MHz
5. Minimum IN_CLK rate: 25 MHz (using the 4x PLL multiplier with IN_CLK = 25 MHz generates the 100 MHz
minimum PLL output rate, at divide-by-1 PLL output)
Table 3 and Table 4 summarize the available one-channel and two-channel operating modes of the GC1115,
respectively.
Table 3. One-Channel Operating Modes
INPUT
FORMAT
OUTPUT
FORMAT
DECIM
INTERP
PLL MULT
IN_CLK
(MHz)
CORE CLK
(MHz)
OUT_CLK
(MHz)
fs/4 (MHz)
Parallel
Parallel
Parallel
Parallel
1
1
4
25 - 75
1
2c
4
25 - 65
100 - 305
25 - 80
NA
100 - 260
50 - 130
Parallel
Parallel
2
1
2
NA
50 - 130
100 - 260
25 - 65
NA
Parallel
Parallel
2
2c
Parallel
Muxed
1
1
2
50 - 130
100 - 260
50 - 130
NA
4
25 - 65
100 - 260
50 - 130
Parallel
Muxed
1
NA
2c
4
25 - 32.5
100 - 305
100 - 130
NA
Parallel
Muxed
Parallel
Muxed
2
1
2
50 - 130
100 - 260
50 - 130
NA
2
2c
2
50 - 130
100 - 260
50 - 130
Parallel
NA
Odd/Even
1
2r
4
25 - 75
100 - 305
50 - 160
12.5 - 40
Parallel
Odd/Even
1
4r
4
25 - 75
100 - 305
100 - 250
25 - 62.5
Parallel
Odd/Even
2
2r
2
50 - 130
100 - 260
100 - 250
25 - 62.5
Parallel
Odd/Even
2
4r
2
50 - 130
100 - 260
100 - 250
25 - 62.5
Muxed
Parallel
1
1
2
50 - 130
100 - 260
25 - 65
NA
Muxed
Parallel
1
2c
2
50 - 130
100 - 260
50 - 130
NA
Muxed
Parallel
2
1
1
100 - 130
100 - 130
25 - 32.5
NA
Muxed
Parallel
2
2c
1
100 - 130
100 - 130
50 - 65
NA
Muxed
Muxed
1
1
2
50 - 130
100 - 260
50 - 130
NA
Muxed
Muxed
1
2c
2
50 - 65
100 - 130
100 - 130
NA
Muxed
Muxed
2
1
1
100 - 130
100 - 130
25 - 32.5
NA
Muxed
Muxed
2
2c
1
100 - 130
100 - 130
50 - 65
NA
Muxed
Odd/Even
1
2r
2
50 - 130
100 - 260
25 - 65
12.5 - 32.5
Muxed
Odd/Even
1
4r
2
50 - 130
100 - 260
50 - 130
25 - 32.5
Muxed
Odd/Even
2
2r
1
100 - 130
100 - 130
25 - 32.5
12.5 - 16.25
Muxed
Odd/Even
2
4r
1
100 - 130
100 - 130
50 - 65
25 - 32.5
OUT_CLK
(MHz)
fs/4 (MHz)
Table 4. Two-Channel Operating Modes
14
INPUT
FORMAT
OUTPUT
FORMAT
DECIM
INTERP
PLL MULT
IN_CLK
(MHz)
CORE CLK
(MHz)
Muxed
Muxed
Muxed
Muxed
1
1
4
50 - 130
100 - 260
50 - 130
NA
1
2c
4
50 - 130
100 - 260
100 - 260
Muxed
NA
Muxed
2
1
2
100 - 130
100 - 130
50 - 65
NA
Muxed
Muxed
2
2c
2
100 - 130
100 - 130
100 - 130
NA
Muxed
Real
1
2r
4
50 - 130
100 - 260
50 - 130
NA
Muxed
Real
2
2r
2
100 - 130
100 - 130
50 - 130
NA
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Clock Generation and PLL Operation
The GC1115 internal clock is normally generated through an on-board PLL. The PLL output frequency is 1, 2, or
4 times the frequency of the user-provided IN_CLK signal. For example, if the GC1115 is provided with an input
signal stream at 61.44 Msamp/sec and the PLL is configured to operate at 4x, the GC1115’s internal clock rate
will be 245.76 MHz. The GC1115’s functional blocks require four internal clock cycles per sample. This rule
affects the selection of related decimation and interpolation factors at a given input sampling rate. In addition,
the GC1115’s PLL divide-by-1 output frequency must fall between 100 MHz and 305 MHz. The 100 MHz
minimum PLL output clock rate is driven by the PLL design, while the 305 MHz maximum PLL output clock rate
is limited by the GC1115’s internal logic design. Alternately, the GC1115’s internal PLL can be bypassed,
effectively using IN_CLK directly as the GC1115 chip clock. However, in this mode, each input sample must be
presented to the input port(s) for four consecutive clock cycles, and the DECIM register must be set to 4. Using
this bypass PLL configuration allows users to operate the GC1115 at input sampling rates lower than 25
Msamp/sec.
NOTE:
Users may have to adjust the clock phase, relative to the data, for proper operation
during bypass PLL mode. Note that DECIM_SYNC may also have to be enabled on a
particular user-selected sample phase (1 of 4 phases) in order to achieve proper
operation during bypass PLL mode.
GC1115 users should be aware that the choice of input operating mode affects IN_CLK and thus also affects
the PLL clock. Specifically, GC1115 users must ensure the relationships shown in Table 5:
Table 5. IN_CLK, PLL Mode, and Core Clock
IN_CLK
(MHz)
PLL MODE
GC1115 CORE CLOCK
(MHz)
25 - 75
4x
100 - 305
50 - 130
2x
100 - 260
100 - 130
1x
100 - 130
1 - 125
Bypass
1 - 125
GC1115 users should also be aware that the core clock affects the choice of output operating mode.
Specifically, GC1115 users must ensure the relationships shown in Table 6. Notice that the odd-even output
mode requires that the interpolator operate in one of its two real-output modes: 2x real or 4x real.
Table 6. Core Clock and Interp Mode
GC1115 CORE CLOCK
(MHz)
INTERP MODE
OUTPUT FORMAT
OUTPUT CLOCK RATE
(MHz)
100 - 305
Bypass
Parallel
25 - 75
100 - 260
Bypass
Muxed I/Q
50 - 130
100 - 260
2x (complex)
Parallel
50 - 130
100 - 130
2x (complex)
Muxed I/Q
100 - 130
100 - 305
2x (real)
Odd/Even
25 - 75
100 - 260
4x (real)
Odd/Even
50 - 130
Summary of Registers Affecting GC1115 Clocks
The following GC1115 registers affect the input, core, and output clocks:
• PLL_CONTROL (0x1): determines PLL multiplier (1x, 2x, 4x, bypass) and source of Tx feedback
• CLK_CONTROL (0x2): determines relationship of IN_CLK and OUT_CLK to CORE_CLK
• IO_MODE (0x9): determines the number of channels (1 or 2), the input data format (parallel, muxed), and
the output data format (parallel, muxed, odd-even)
• DECIMATE (0xC): determines the downsampling of the input stream prior to GC1115 processing
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•
INTERP_CTL (0x80): determines the interpolator operating mode (bypass, 2x complex, 2x real, 4x real).
Note that INTERP_CTL and IO_MODE must be consistent to ensure proper operation!
Figure 7 demonstrates the GC111 registers that determine the various internal clock frequencies.
PLL feedback
PLL_CONTROL
9 8
1 0
2
1
3
0
PLL_CORE
OUT_CLK
FCLK
to LOOP_SEL
PLL mult
CTRL
IN_CLK
RCLK
IN_CLK phase
÷1
÷2
÷4
3
2
1
0
loads
CLK_CORE
PLL bypass
OUT_CLK select
CLK_CONTROL
15 14 13 12
98
3 2 1 0
LOOP_IN
0PLL_OUT
FCLK
RCLK
÷1
÷2
÷4
3
2
1
0
.
÷2
÷4
CLK_OUT
LOOP_OUT
LOOP_SEL
Figure 7. PLL_CONTROL and CLK_CONTROL Registers
DETAILED DESCRIPTION OF GC1115 FUNCTIONAL BLOCKS
Microprocessor Interface Registers and Interrupts
The GC1115’s microprocessor interface presents the device as a set of memory-mapped registers to the
controlling microprocessor or DSP. All aspects of the GC1115 are configured, monitored, and controlled through
these registers. The microprocessor interface consists of a 16-bit bi-directional data bus D[15:0], an 8-bit
address bus A[7:0], a write strobe WR, a read strobe RD, and a chip select CS. Two-pin or three-pin mode is
selected by using (or grounding) the RD pin:
• three-pin mode (RD is used): separate read strobe on RD pin and write strobe on WR pin
• two-pin mode (RD is grounded): WR low (gnd) means "write to GC1115"; WR high (3.3 V) means "read
GC1115".
NOTE:
The GC1115 rev0 silicon does not support three-pin mode. Please use two-pin mode
with rev0 silicon.
Figure 8 demonstrates a glueless interface between a generic Texas Instruments TMS320Cxx DSP chip and a
GC1115, assuming that the CG1115 is the only device in the DSP’s I/O memory space. If the TMS320Cxx DSP
controls multiple devices in its I/O memory space, additional external address decoding is required to generate
CS.
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DETAILED DESCRIPTION OF GC1115 FUNCTIONAL BLOCKS (continued)
The microprocessor or DSP can configure the GC1115 to generate an interrupt at the occurrence of various
GC1115 internal events. Please refer to the description of the INT_MAP and INT_MASK registers for a complete
description of these events.
The GC1115 microprocessor interface operates at speeds between 33 MHz and 100 MHz. Register read/write
accesses are faster than RAM read/write accesses. RAM access is used for snapshot RAM and shadow RAM.
Please refer to the timing diagrams for specific information on GC1115 register access rates. RAM access is
limited to 33 MHz.
GC1115
TMS320Cxx
A[7:0]
A[7:0]
D[15:0]
D[15:0]
RD_
RD/WR
WR_
IOS
CS_
INT_A
INT_
Figure 8. TMS320Cxx – GC1115 Interface
Users configure the GC1115 by writing control information into a set of 16-bit memory-mapped registers. The
registers are accessed using the GC1115’s A[7:0], D[15:0], CS, RD, and WR pins. The complete register map is
described in detail in a subsequent section. Certain GC1115 registers can be modified at any time during
GC1115 operation, while other registers may not be modified until certain conditions are met. Table 7
summarize these restrictions. The GC1115 will strictly enforce the update restrictions listed in Table 7. If a
particular update condition is not met, the GC1115 will not update the specified register.
Table 7. GC1115 Register Updates
ADDRESS
NAME
WHEN CAN REGISTER BE UPDATED?
0
RESET
Any time
1
PLL_CONTROL
Any time
2
CLK_CONTROL
Any time
3
CONTROL
Any time
4
INT_MAP
After GC1115 sends an interrupt
5
INT_MASK
Any time
6
MASK_REV
READ ONLY
7
SW_TRIGGER
Any time
8
IO_CONTROL
Any time
After GC1115 receives IN_CLK
9
IO_MODE
10 (0xA)
POWER_CTL
Any time
11 (0xB)
POWER
READ ONLY
12 (0xC)
DECIMATE
Any time (after change, output may be invalid for a few samples)
13 (0xD)
TIMER_HI_RST
When timer is OFF
14 (0xE)
TIMER_LO_RST
When timer is OFF
15 (0xF)
CANCEL_MODE
Any time
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DETAILED DESCRIPTION OF GC1115 FUNCTIONAL BLOCKS (continued)
Table 7. GC1115 Register Updates (continued)
18
ADDRESS
NAME
WHEN CAN REGISTER BE UPDATED?
16 (0x10)
CANCEL_LENGTH
Any time
17 (0x11)
CANCEL_ADDRESS
Any time
18 (0x12)
CANCEL_DATA
Any time
19 (0x13)
RESOURCE_MASK
Any time
20 (0x14)
DELAY_MASK
Any time
21 (0x15)
SIG_GEN_CTL
Any time
22 (0x16)
SIG_GEN_BASE
Any time
23 (0x17)
SIG_GEN_INC
Any time
24 (0x18)
CRC_RESULT
Any time
25 (0x19)
RCV_SYNC
Any time (after change, output may be invalid for a few samples)
26 (0x1A)
STAGE_SYNC
Any time (after change, output may be invalid for a few samples)
27 (0x1B)
DECIM_SYNC
Any time (after change, output may be invalid for a few samples)
28 (0x1C)
TIMER_SYNC
Any time (after change, output may be invalid for a few samples)
29 (0x1D)
DELAY_SYNC
Any time (after change, output may be invalid for a few samples)
30 (0x1E)
CANCEL_SYNC
Any time (after change, output may be invalid for a few samples)
31 (0x1F)
RESOURCE_SYNC
Any time (after change, output may be invalid for a few samples)
32 (0x20)
INTERP_SYNC
Any time (after change, output may be invalid for a few samples)
33 (0x21)
OUTGAIN_SYNC
Any time
34 (0x22)
OUTPIN_SYNC
Any time
35 (0x23)
SIG_GEN_SYNC
Any time
36 (0x24)
SNAP_A_SYNC
Any time
37 (0x25)
SNAP_B_SYNC
Any time
48 (0x30)
RESOURCE_CNT1
Any time
49 (0x31)
DETECT_TSQD1
Any time
50 (0x32)
GAIN_TSQD1
Any time
51 (0x33)
CANCEL_DELAY1
Any time
56 (0x38)
RESOURCE_CNT2
Any time
57 (0x39)
DETECT_TSQD2
Any time
58 (0x3A)
GAIN_TSQD2
Any time
59 (0x3B)
CANCEL_DELAY2
Any time
64 (0x40)
RESOURCE_CNT3
Any time
65 (0x41)
DETECT_TSQD3
Any time
66 (0x42)
GAIN_TSQD3
Any time
67 (0x43)
CANCEL_DELAY3
Any time
72 (0x48)
RESOURCE_CNT4
Any time
73 (0x49)
DETECT_TSQD4
Any time
74 (0x4A)
GAIN_TSQD4
Any time
75 (0x4B)
CANCEL_DELAY4
Any time
96 (0x60)
SNAP_A_CONTROL
Any time
97 (0x61)
SNAP_A_STATUS
READ ONLY
98 (0x62)
SNAP_A_ADDRESS
Any time
99 (0x63)
SNAP_A_DATA
Any time
100 (0x64)
SNAP_A_MINVAL
When Snap A is OFF
101 (0x65)
SNAP_A_MAXVAL
When Snap A is OFF
102 (0x66)
SNAP_A_SCALER
When Snap A is OFF
103 (0x67)
SNAP_A_HISTCOUNT
When Snap A is OFF
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DETAILED DESCRIPTION OF GC1115 FUNCTIONAL BLOCKS (continued)
Table 7. GC1115 Register Updates (continued)
ADDRESS
NAME
112 (0x70)
SNAP_B_CONTROL
WHEN CAN REGISTER BE UPDATED?
Any time
113 (0x71)
SNAP_B_STATUS
READ ONLY
114 (0x72)
SNAP_B_ADDRESS
Any time
115 (0x73)
SNAP_B_DATA
Any time
116 (0x74)
SNAP_B_MINVAL
When Snap B is OFF
117 (0x75)
SNAP_B_MAXVAL
When Snap B is OFF
118 (0x76)
SNAP_B_SCALER
When Snap B is OFF
119 (0x77)
SNAP_B_HISTCOUNT
When Snap B is OFF
127 (0x7F)
COUNTER_VAR
Any time
128 (0x80)
INTERP_CTL
When interpolator is bypassed
129 (0x81)
(reserved)
(reserved)
130 (0x82)
D0_COEF0
When interpolator is bypassed
...
...
...
169 (0xA9)
D3_COEF9
When interpolator is bypassed
192 (0xC2)
SOFT_LENGTH
When soft limiter is bypassed
193 (0xC3)
SOFT_TSQD
When soft limiter is bypassed
194 (0xC4)
SOFT_COEF0
When soft limiter is bypassed
...
...
...
209 (0xD1)
SOFT_COEF15
When soft limiter is bypassed
210 (0xD2)
SOFT_TAB_SCALE
When soft limiter is bypassed
211 (0xD3)
SOFT_INVGAIN0
When soft limiter is bypassed
...
...
...
242 (0xF2)
SOFT_INVGAIN31
When soft limiter is bypassed
243 (0xF3)
OUT_GAIN0
When soft limiter is bypassed
244 (0xF4)
OUT_GAIN1
When soft limiter is bypassed
245 (0xF5)
OUT_OFFSET_I0
When soft limiter is bypassed
246 (0xF6)
OUT_OFFSET_Q0
When soft limiter is bypassed
247 (0xF7)
OUT_OFFSET_I1
When soft limiter is bypassed
248 (0xF8)
OUT_OFFSET_Q1
When soft limiter is bypassed
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Setting Detection Thresholds and Target Peak Levels
The most obvious user-specified parameter for a CFR processor is the desired output PAR. The output PAR
determines the largest sample magnitude on the output ports of the GC1115. Ultimately, the PAR determines
the maximum Vin voltage of the PA. This maximum value is then adjusted to fit just under the 1 dB compression
point of the PA. The average power of the GC1115 input samples (0 dB point on the CCDF curve) can be
calculated from a group of input samples. TI provides a Matlab function that uses a group of input samples to
calculate the 16-bit threshold-squared values that are loaded into the GC1115’s DETECT_TSQD and
GAIN_TSQD registers (one pair of registers for each of four stages; total of eight TSQD registers). Upon
request, TI will provide the Matlab source code (m-file) for the threshold calculations based on input samples.
Alternately, GC1115 users can use the GC1115’s built-in hardware power measurement capability to determine
the average input power. The detection thresholds and target peak levels can then be calculated from the
average input power.
GC1115 threshold settings are based on a threshold SQUARED (power) value, not a threshold (magnitude)
value. The following example demonstrates how the GC1115’s threshold-squared values are calculated, using
the Matlab language:
%
%
%
Calculate the average power of the complex input array x, and the desired fractional (magnitude)
threshold, given the user-specified target peak level (in dB).
avgMag
frac
%
%
%
%
%
%
= sqrt(mean(abs(x).^2));
= avgMag * 10 ^ (dB_target / 20);
Derive the following threshold-related values from the target PAR magnitude:
thresh
threshSqd
thresh
threshSqd
bits
signed, 14-bit threshold value (a magnitude!)
threshold set as a 16-bit mag-squared value (reduced from a 29-bit mag-squared value)
= floor (frac * 2^13);
= floor((thresh ^ 2)/ (2^13));
%
%
set the threshold relative to signed 14-bit samples
mag-sqd of a 14-bit value = 28 bits plus an add = 29
%
Divide by 2^13 to convert to 16-bit thresh-sqd value
The GC1115 uses four sequential PDC stages to achieve the desired output PAR. For output PAR levels below
8 dB, both cEVM and PCDE performance is improved if the earlier stages have higher detection thresholds (set
to 8 dB or 7 dB), while later stages contain the final, desired threshold (7 dB, 6 dB, or 5 dB, for instance). In all
cases, the GAIN_TSQD registers should be set to the target peak level (desired output PAR). When the desired
output PAR is at or above 8 dB, the DETECT_TSQD and GAIN_TSQD registers are set as shown in Table 8:
Table 8. Detection and Gain Thresholds, PAR ≥ 8 dB
STAGE
DETECT_TSQD
GAIN_TSQD
1
my_tsqd
my_tsqd
2
my_tsqd
my_tsqd
3
my_tsqd
my_tsqd
4
my_tsqd
my_tsqd
When the desired output PAR is below 8 dB, the recommended DETECT_TSQD and GAIN_TSQD register
settings are set as shown in Table 9:
Table 9. Detection and Gain Thresholds, PAR < 8 dB
20
STAGE
DETECT_TSQD
GAIN_TSQD
1
min(8 dB, my_tsqd + 2 dB)
my_tsqd
2
min(7 dB, my_tsqd+1 dB)
my_tsqd
3
my_tsqd
my_tsqd
4
my_tsqd
my_tsqd
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Designing Cancellation Pulse Coefficients
Cancellation pulse coefficient design is identical to FIR filter design. The goal of designing cancellation pulses is
to mirror the signal energy of the input signal. If the input signal contains one carrier, the cancellation pulse’s
center frequency and bandwidth will have the same center frequency and bandwidth as that carrier. For
multi-carrier signals, multiple single-carrier cancellation pulses are added together to create a spectrum that is
identical to the spectrum of the multi-carrier input signal. The goal of cancellation pulse design is to place energy
ONLY in those frequency regions where the input signal has appreciable energy, i.e. in the carrier bands
themselves. This design method ensures that cancellation pulse energy is inserted only where input signal
energy is already present, and to avoid placing any additional energy outside those bands, since such
out-of-band energy would worsen ACLR performance.
Upon request, TI will provide Matlab code that demonstrates how cancellation pulses are designed. This Matlab
software requires the following input parameters:
• Input sampling rate
• Single-carrier bandwidth
• Carrier center frequencies
• Desired cancellation pulse length (an odd number; from 15 to 255 for real cancel pulses, and from 15 to 127
for complex cancel pulses)
The Matlab cancellation pulse design software then calls a standard Matlab FIR filter design function (such as
fir1, firls, or remez) to design a prototype cancellation pulse whose bandwidth matches the single-carrier
bandwidth input parameter. If the input signal contains two or more carriers, copies of this prototype filter will be
translated to the center frequency of each carrier and the copies summed together.
Cancellation Coefficient Shadow RAM
The GC1115 uses a derivative-based approximation method to calculate highly accurate phase shifts of the
cancellation pulse. The approximation method requires not only the cancellation coefficients themselves to be
stored in the GC1115, but also the coefficients’ first and second derivatives. The cancellation coefficient shadow
RAM contains 768 unique addresses that hold up to 256 unique cancellation coefficients and their first and
second derivatives.
NOTE:
Upon request, TI will provide a Matlab script that calculates the proper first and
second derivatives from user-designed cancellation coefficients.
Shadow RAM is physically distinct from canceler RAM. This distinction is fully explained in the section entitled
Shadow RAM and Canceler RAMs, below. The microprocessor or DSP controlling the GC1115 can only access
the shadow RAM.
Cancellation coefficient shadow RAM is used differently, depending on the CANCEL_MODE setting (real or
complex coefficients; unique or mirrored coefficients). Table 10, Table 11, and Table 12 illustrate how
cancellation coefficients are stored and accessed in the GC1115’s cancellation coefficient shadow RAM.
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Table 10. Real, Unique Coefficients
TYPE OF DATA
ADDRESS
COEFFICIENT
Coefficients
0
coef[0]
1
coef[1]
2
coef[2]
...
...
CANCEL_LENGTH-1
coef[CANCEL_LENGTH-1]
256
deriv1[0]
257
deriv1[1]
258
deriv1[2]
...
...
255+CANCEL_LENGTH
deriv1[CANCEL_LENGTH-1]
512
deriv2[0]
513
deriv2[1]
514
deriv2[2]
...
...
511+CANCEL_LENGTH
deriv2[CANCEL_LENGTH-1]
First derivative
Second derivative
Coefficient access pattern:
coef[0], coef[1], …, coef[CANCEL_LENGTH-2], coef[CANCEL_LENGTH-1]
Table 11. Real, Mirrored Coefficients
TYPE OF DATA
ADDRESS
COEFFICIENT
Coefficients
Same as Table 10
Same as Table 10
First derivative
Same as Table 10
Same as Table 10
Second derivative
Same as Table 10
Same as Table 10
Coefficient access pattern:
coef[0], coef[1], …, coef[CANCEL_LENGTH-2], coef[CANCEL_LENGTH-1], coef[CANCEL_LENGTH-2],
coef[CANCEL_LENGTH-3], …, coef[1], coef[0].
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Table 12. Complex Coefficients
TYPE OF DATA
ADDRESS
COEFFICIENT
Complex coefs (real part)
0
coef_re[0]
1
coef_re[1]
2
coef_re[2]
...
...
CANCEL_LENGTH-1
coef_re[CANCEL_LENGTH-1]
128
coef_im[0]
129
coef_im[1]
130
coef_im[2]
...
...
127+CANCEL_LENGTH
coef_im[CANCEL_LENGTH-1]
256
deriv1_re[0]
257
deriv1_re[1]
258
deriv1_re[2]
...
...
255+CANCEL_LENGTH
deriv1_re[CANCEL_LENGTH-1]
384
deriv1_im[0]
385
deriv1_im[1]
386
deriv1_im[2]
...
...
383+CANCEL_LENGTH
deriv1_im[CANCEL_LENGTH-1]
512
deriv2_re[0]
513
deriv2_re[1]
514
deriv2_re[2]
...
...
511+CANCEL_LENGTH
deriv2_re[CANCEL_LENGTH-1]
640
deriv2_im[0]
641
deriv2_im[1]
642
deriv2_im[2]
...
...
639+CANCEL_LENGTH
deriv2_im[CANCEL_LENGTH-1]
Complex coefs (imaginary part)
First derivative (real part)
First derivative (imaginary part)
Second derivative (real part)
Second derivative (imaginary part)
Coefficient access pattern:
{coef_re[0], coef_im[0]}, {coef_re[1], coef_im[1]}, …,
{coef_re[CANCEL_LENGTH-1], coef_im[CANCEL_LENGTH-1]}
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Writing Cancellation Coefficients to Shadow RAM
The GC1115 uses the CANCEL_ADDR register as a coefficient memory pointer to access cancellation
coefficient shadow RAM. This indirect addressing method requires only two registers (CANCEL_ADDR and
CANCEL_DATA) in the GC1115 memory map, while allowing GC1115 users access to 768 unique shadow
RAM addresses.
To access a particular shadow RAM location, the microprocessor or DSP that controls the GC1115 first writes
the desired address into the CANCEL_ADDR register. To write to the shadow RAM, the microprocessor or DSP
then writes the desired coefficient value to the CANCEL_DATA register. A write to (or read from) the
CANCEL_DATA register automatically post-increments the address in the CANCEL_ADDR register. The
following example demonstrates how the CANCEL_ADDR auto-increment feature is used to initialize the first
three cancellation coefficient shadow RAM locations mem(0), mem(1), and mem(2):
STEP
REGISTER
VALUE
CANCEL_ADDR
AUTO-INCREMENT
COMMENTS
1
CANCEL_ADDR
0
0
addr = 0
2
CANCEL_DATA
0x111
0→1
mem(0) = 0x111
3
CANCEL_DATA
0x456
1→2
mem(1) = 0x456
4
CANCEL_DATA
0x321
2→3
mem(2) = 0x321
Alternately, the microprocessor or DSP software can specify a shadow RAM address (0..767) with each
CANCEL_DATA access. This mode is useful when updating non-contiguous shadow RAM addresses. The
following example demonstrates how the CANCEL_ADDR direct-addressing mode is used to initialize the first
three cancellation coefficient shadow RAM locations mem(0), mem(2), and mem(1), in non-sequential order (just
to demonstrate the direct addressing capability):
STEP
REGISTER
VALUE
CANCEL_ADDR
AUTO-INCREMENT
COMMENTS
1
CANCEL_ADDR
0
0
addr = 0
2
CANCEL_DATA
0x111
0→1
mem(0) = 0x111
3
CANCEL_ADDR
2
2
addr = 2
4
CANCEL_DATA
0x321
2→3
mem(2) = 0x321
5
CANCEL_ADDR
1
1
addr = 1
6
CANCEL_DATA
0x456
1→2
mem(1) = 0x456
Shadow RAM and Canceler RAMs
The GC1115 contains eight unique canceler RAM memories that hold cancellation coefficients and their
derivatives. Each of the eight unique canceler RAMs can be accessed up to four times per IN_CLK clock period,
and each of the cancelers has its own canceler RAM pointer. This structure allows four cancelers to be
supported by one canceler RAM per IN_CLK clock period. This structure also makes it possible to store eight
different cancellation coefficient sets in the GC1115 (although this option is not recommended). With a total of
eight canceler RAMs, the GC1115 can have up to 32 cancelers running independently per channel (four
cancelers per canceler RAM per channel). Cancellation pulse resources are allocated in groups of four per
channel, i.e. one canceler RAM at a time, to the four PDC stages. The registers RESOURCE_CNT1 thru
RESOURCE_CNT4 specify how many canceler RAMs are allocated to each PDC stage. The total number of
resources cannot exceed 8.
The CANCEL_ADDR and CANCEL_DATA registers are used to write to an independent “shadow RAM”. Using
the CANCEL_ADDR and CANCEL_DATA registers, the GC1115’s controlling microprocessor or DSP writes
cancellation coefficients and derivative values to this shadow RAM, and not directly to the canceler RAMs
themselves. When a COEF_SYNC synchronization event occurs, the contents of the shadow RAM are copied
(one value per internal GC1115 clock cycle) to those canceler RAMs whose corresponding bit is set in the
RESOURCE_MASK register. Using the RESOURCE_CNT registers, cancelers may be separately taken off-line,
updated, and brought back on-line in seamless operation. This approach ensures that the GC1115 is never
without cancellation resources.
To summarize, cancellation coefficients and their derivatives are written to canceler RAMs as follows:
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1. Using CANCEL_ADDR and CANCEL_DATA, write up to 768 canceler coefficients and their derivatives to
shadow RAM
2. Using the RESOURCE_MASK register, specify which canceler RAMs are to be initialized from shadow RAM
when the COEF_SYNC event occurs
3. Using the COEF_SYNC register, specify which event (SW_TRIGGER, timer, SYNC_A, SYNC_B, etc.) will
trigger the COEF_SYNC event
4. After the COEF_SYNC event occurs, the GC1115 copies 3 × CANCEL_LENGTH values from shadow RAM
to the canceler RAMs selected by the RESOURCE_MASK register. During each internal clock cycle, one
shadow RAM value is copied simultaneously to the canceler RAMs enabled by their corresponding
RESOURCE_MASK bits. The total canceler RAM copy time depends on CANCEL_LENGTH and on the
time spent waiting for the selected RAMs to become idle, not on how many canceler RAMs are enabled for
update in the RESOURCE_MASK register.
5. After the GC1115 has copied 3 × CANCEL_LENGTH values from shadow RAM to canceler RAM, the
microprocessor or DSP can optionally be interrupted, if bit 6 of INT_MASK was set prior to Step 3.
Alternately, bit 6 of INT_MAP can be polled to determine when the shadow RAM copy completes.
Once the shadow RAM has been initialized, the process of copying the shadow RAM values to the canceler
RAMs occurs very quickly. For example, assuming an IN_CLK frequency of 61.44 MHz (16.3 ns), a
GC1115-internal clock rate of 4 × 61.44 MHz (4.1 ns), and a CANCEL_LENGTH of 87, the GC1115 only
requires 3 × 87 × 4.1 ns = 1.07 µs to initialize all RESOURCE_MASK-enabled canceler RAMs, assuming all
cancelers to be updated were idle when the CANCEL_SYNC trigger occurred.
CANCEL_LENGTH and CANCEL_DELAY
In many GC1115 applications, a symmetric set of cancellation coefficients is chosen to match a symmetric
carrier configuration (i.e. the center frequencies of the carrier configuration are symmetric about DC). When
cancellation coefficients are symmetric, the delay introduced by a cancellation pulse with N coefficients is N/2, or
half the cancellation pulse length. The number of samples between the first coefficient and the largest coefficient
determines CANCEL_DELAY. Since the largest coefficient of symmetric filters is usually at the midpoint of the
filter, the delay is half the filter length.
Figure 9 illustrates a typical, symmetric FIR filter impulse response, whose largest coefficient is at tap 50, at the
midpoint of the 99-coefficient filter.
Figure 9. Typical Symmetric Cancel Pulse Impulse Response, CANCEL_DELAY = 50
It is possible, however, to generate cancellation pulses whose largest coefficient is less than
CANCEL_LENGTH/2. Such cancellation pulses are called minimum phase pulses. Minimum-phase cancellation
pulses reduce the effective delay through the GC1115. Figure 10 illustrates the impulse response of a minimum
phase cancellation pulse. Notice that the largest magnitude coefficient (tap 7) is significantly closer to tap 1 than
to the middle coefficient (tap 25). The GC1115 can use either non-minimum phase or minimum phase
cancellation pulses. If a non-minimum phase filter is being used, CANCEL_DELAY = CANCEL_LENGTH / 2. If a
minimum phase filter is being used, CANCEL_DELAY < CANCEL_LENGTH / 2. CANCEL_DELAY must be
properly initialized to compensate for the cancellation pulse delay.
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Figure 10. Minimum Phase Cancel Pulse Impulse Response, CANCEL_DELAY = 7
Software Timer
The GC1115 provides a flexible, user-controlled software timer that can serve as a programmable
synchronization source. The timer is controlled through the TIMER_SYNC register, which allows users to select
the event that triggers the timer. Before enabling the timer to start (via the TIMER_CTL register), the user
specifies a timer period using the TIMER_HI_RST and TIMER_LO_RST registers. The timer is decremented
with each internal clock edge (normally at a frequency of 4 x IN_CLK). When the TIMER_SYNC event occurs,
the timer copies the 32-bit values contained in TIMER_HI_RST and TIMER_LO_RST into a GC1115-internal
32-bit timer register. This 32-bit timer is then decremented with each internal chip clock (normally chip clock = 4
x IN_CLK). When the timer reaches zero, the timer is re-loaded from TIMER_HI_RST and TIMER_LO_RST
(periodic timer event), or the timer is disabled (for one-time timer events). Bit 15 of the TIMER_SYNC register
determines the timer mode (periodic or one-time).
The microprocessor or DSP can be interrupted when the timer expires by setting bit 4 of INT_MASK. It is
expected that software-initiated timer start operation will most often be used in one-time mode (and not periodic
mode), thus giving the microprocessor or DSP time to monitor a GC1115 event, such as reading the snapshot
RAM contents.
Signal Generator and CRC Generator
The GC1115 contains a simple signal generator that can be used to drive the GC1115 PDC stages. The signal
generator capability is useful when debugging a board containing a GC1115, or to debug the GC1115 itself.
When enabled, the signal generator output drives the input of PDC Stage 1. The signal generator can be
configured to generate one of several types of signals:
• A DC level
• A sawtooth waveform
• A pseudo-LFSR waveform with PAR of approximately 10 dB
The signal generator is configured using the SIG_GEN_CTL, SIG_GEN_BASE, and SIG_GEN_INC registers.
The signal generator period is determined by SIG_GEN_CTL, SIG_GEN_BASE, SIG_GEN_INC, and
SIG_GEN_SYNC registers. In LFSR mode, the LFSR generator and the CRC generators are reset whenever a
SIG_GEN_SYNC trigger occurs. Because the GC1115 pipeline must contain predictable information, the
minimum SIG_GEN_SYNC period should be at least 1000 IN_CLK periods.
The GC1115 also contains a cyclic redundancy check (CRC) generator. The CRC generator receives its input
from the output of PDC Stage 4. The CRC generator is enabled whenever the signal generator is enabled. The
CRC generator can also be fed using user-provided data on Input Port A and B, and by setting SIG_GEN_CTL
to 0x3. CRC generation using sawtooth or LFSR data provides a predictable, periodic way to determine proper
internal GC1115 operation, independent of a user-provided input sequence. Note that the LFSR sequence is not
bandlimited, but the distribution of its magnitudes is Gaussian.
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Contact TI to receive an appropriate set of CRC initialization and test parameters.
Snapshot RAM Operation
The GC1115 contains two independent, identically operating snapshot RAMs for signal capture and histogram
generation. The snapshot RAMs operate in one of three modes:
• No operation (OFF)
• Capture mode (RAM is configured as a 2k × 16-bit memory, with I and Q samples interleaved)
• Histogram mode (RAM is configured with even addresses storing the 16 MSBs, and odd addresses storing
the 16 LSBs, of 32-bit counters)
These RAMs can capture or histogram sample streams at five independent locations within the GC1115:
• At the GC1115’s input (after the decimator and prior to Stage 1)
• After PDC Stage 1
• After PDC Stage 2
• After PDC Stage 3
• After PDC Stage 4
In capture mode, the 16 MSBs of each 18-bit sample are stored in the snapshot RAM as follows:
ADDRESS
VALUE
i=0,2,4,…
I[17:2] (sixteen MSBs of 18-bit I value)
j=1,3,5,…
Q[17:2] (sixteen MSBs of 18-bit Q value)
In histogram mode, each snapshot RAM monitors the output of a function generator that generates one of the
following values from its I & Q source samples:
• I sample
• Q sample
• Magnitude squared (I*I + Q*Q)
The arithmetic processing of samples in histogram mode is shown in Figure 11. First, the user-selected function
of the complex input sample I + jQ is calculated. Second, the calculated value is compared to SNAP_MINVAL
and SNAP_MAXVAL. If the calculated value is not within the desired range, no further action occurs for this
sample. If the calculated value is within the desired range, then SNAP_MINVAL is subtracted from the
calculated value, and the result is multiplied by SNAP_SCALE to generate a 10-bit histogram index (between 0
and 1023).
Let us consider a histogram example in which users are interested in monitoring the power of samples above
the average power (to calculate CCDF, for instance). Assume that the average power corresponds to 16-bit
samples with mag-squared values of 2 × (100002), or 2 × 108. For 16-bit samples, the largest possible
mag-squared value is 2 × 327672 = 2.14x 109. The GC1115 removes the lower 16 bits from each 32-bit
mag-squared values, so that the function generator output is always in the signed 16-bit range. The initial values
for SNAP_MINVAL, SNAP_MAXVAL, and SNAP_SCALE are calculated as follows:
• SNAP_MINVAL = 3052 (2 × [100002] / 216)
• SNAP_MAXVAL = 32767 (2 × [327672] / 216)
• SNAP_SCALE = 1024 / (32767 – 3052) = 0.03446 (= 1129 as a signed 16-bit integer)
If users wanted to monitor the input signal for 30 seconds (about 1.8 × 109 samples – plenty of statistical
significance), SNAP_HISTCOUNT = 27465 (1.8 × 109 / 65536).
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SNAP_MAXVAL
I
Q
18
Function
Generator
(I, Q, mag^2)
18
SNAP_SCALE
16
16
min & max
range check
−
16
10
x
16
SNAP_MINVAL
HISTOGRAM
INDEX
10
Histogram bin
update
(fetch bin count,
increment,
store inc’d count)
Histogram bins
(1k x 32 bits)
Figure 11. Snapshot RAM Histogram Operation
•
•
•
SNAP_MINVAL: minimum value of interest (-32768..+32767)
SNAP_MAXVAL: maximum value of interest (-32768..+32767)
SNAP_SCALE: a 16-bit multiplier that scales the 16-bit (value – SNAP_MINVAL) into the 10-bit range
0..1023.
In C pseudo-code, the GC1115 histogram index calculation and bin update is performed as follows:
if ( (funcGen[i]
j
=
index =
index &=
>= SNAP_MINVAL) && (funcGen[i] <= SNAP_MAXVAL) ) {
funcGen[i]
SNAP_MINVAL;
int(j * SNAP_SCALE);
0x3FF;
hist[index]++
}
The minimum histogram index will never be less than 0, while the maximum histogram index should never
exceed 1023. The SNAP_MINVAL and SNAP_MAXVAL values allow GC1115 users to bracket specific sample
ranges of interest, while ignoring values outside of this range. The SNAP_SCALE multiplier then maps the range
of interest into the available histogram bins (0..1023).
In histogram mode, the GC1115 snapshot RAMs collect statistics on the frequency of occurrence of certain
sample or magnitude-squared values. Since the GC1115 contains two snapshot RAMs, these statistics can be
used to simultaneously monitor the signal at two different stages of processing (such as at the input and at the
output). After a time, the histograms stored in RAM A and RAM B are read by the microprocessor or DSP, which
allows derived values (such as CCDF) to be obtained from the histogram bin counts.
Snapshot RAMs can be individually cleared (i.e. all entries set to zero) via control bits in the
SNAP_A_CONTROL and SNAP_B_CONTROL registers. Snapshot RAMs must be cleared prior to histogram
processing in order to zero all histogram counts.
Table 13 below shows how the snapshot RAM memory is used in capture and histogram modes. The addresses
in Table 13 are those that appear in the SNAP_A_ADDRESS or SNAP_B_ADDRESS registers.
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Table 13. Snapshot RAM Addressing in Capture and Histogram Modes
MODE
ADDRESS
CONTENTS
Capture
0
I[0] (1)
1
Q[0] (1)
2
I[1] (1)
3
Q[1] (1)
Histogram
(1)
...
...
2046
I[1023] (1)
2047
Q[1023] (1)
0
HIST_MSW[0]
1
HIST_LSW[0]
2
HIST_MSW[1]
3
HIST_LSW[1]
...
...
2046
HIST_MSW[1023]
2047
HIST_LSW[1023]
In capture mode, the 16 MSBs of the 18-bit samples are saved. MSW = most significant word (upper
16 bits), LSW = least significant word (lower 16 bits)
The SNAP_ADDRESS registers autoincrement with each SNAP_DATA access. This autoincrementing can
result in addresses that exceed the allowed snapshot RAM address range. The GC1115 resolves this address
overflow condition by resetting the SNAP_ADDRESS register to zero if an autoincrement generates an address
value greater than 2047.
Input Decimator
When the input signal is highly oversampled, the GC1115 user may want to decimate the complex input stream
prior to PDC processing. The DECIMATE register is provided for such circumstances. Under most conditions,
decimating an input signal will result in decreased performance because the higher, non-decimated sampling
rate better represents the signal. However, if the GC1115 is unable to accept the original input sampling rate,
decimation by 2 is provided as an option. GC1115 users wanting to use the 2x decimation settings must be
aware of decimation’s effects on GC1115 clock generation. Please refer to the Operating Modes section of this
document for details about how DECIMATE = 2 affects GC1115 operation.
Interpolation Operation
The GC1115 contains an interpolator stage after the fourth (final) PDC Stage. This interpolation stage can be
bypassed by clearing bit 4 of the CONTROL register. The interpolation stage also provides the following optional
capability:
• Interpolate by 2, real output, fs/4 modulation at the upsampled sampling rate
• Interpolate by 2, complex output
• Interpolate by 4, real output, fs/4 modulation at the upsampled sampling rate
The interpolate-by-4 stage uses 40 interpolation coefficients. These interp-by-4 coefficients are stored at
addresses 0x82 thru 0xA9. When the interpolate-by-4 stage is bypassed, the GC1115 requires the interp-by-4
coefficients shown in Table 14 (these are the default interp-by-4 values after a GC1115 RESET):
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Table 14. Interpolate-by-4 Bypass Coefficients
ADDRESS RANGE
INTERP-BY-4 COEFFICIENTS
0x82 – 0x85
0x8000, 0, 0, 0
0x86 – 0x89
0, 0, 0, 0
0x8A – 0x8D
0, 0, 0, 0
0x8E – 0x91
0, 0, 0, 0
0x92 – 0x95
0, 0, 0, 0
0x96 – 0x99
0, 0, 0, 0
0x9A – 0x9D
0, 0, 0, 0
0x9E – 0xA1
0, 0, 0, 0
0xA2 – 0xA5
0, 0, 0, 0
0xA6 – 0xA9
0, 0, 0, 0
When the interpolate-by-4 stage is active, the GC1115 requires the interp-by-4 coefficients shown in Table 15:
Table 15. Interpolate-by-4 2x and 4x Interpolation Coefficients
ADDRESS RANGE
INTERP-BY-4 COEFFICIENTS (decimal)
INTERP-BY-4 COEFFICIENTS (hex)
0x82 – 0x85
0, -4, -21, -35
0x0, 0XFFFC, 0XFFEB, 0XFFDD
0x86 – 0x89
0, 122, 287, 319
0x0, 0x7A, 0x11F, 0x13F
0x8A – 0x8D
0, -700, -1401, -1372
0x0, 0xFD44, 0xFA87, 0xFAA4
0x8E – 0x91
0, 2519, 4781, 4558
0x0, 0x9D7, 0x12AD, 0x11CE
0x92 – 0x95
0, -8970, -20028, -29203
0x0, 0xDCF6, 0xB1C4, 0x8DED
0x96 – 0x99
-32768, -29203, -20028, -8970
0x8000, 0x8DED, 0xB1C4, 0xDCF6
0x9A – 0x9D
0, 4558, 4781, 2519
0x0, 0x11CE, 0x12AD, 0x9D7
0x9E – 0xA1
0, -1372, -1401, -700
0x0, 0xFAA4, 0xFA87, 0xFD44
0xA2 – 0xA5
0, 319, 287, 122
0x0, 0x13F, , 0x11F, 0x7A
0xA6 – 0xA9
0, -35, -21, -4
0x0, 0xFFDD, 0xFFEB, 0xFFFC
When the interp-by-4 stage operates in real output mode (i.e. not in complex output mode), it also modulates the
input (baseband) signal to an intermediate frequency. For example, if IN_CLK is 61.44 Msamp/sec, interp-by-2
real mode would raise the sampling rate to 122.88 Msamp/sec (real samples) and the interpolated output signal
would be centered at 122.88 / 4 = 30.72 MHz after the interpolate-by-4 stage.
If the interpolated output sampling rate exceeds 130 Msamp/sec, the output ports must be configured in
odd/even mode. In odd/even mode, successive samples are demultiplexed between OUT_A and OUT_B ports,
effectively lowering the sampling rate on each output port by a factor of 2.
Soft Limiter Operation
NOTE:
Under nearly all operating conditions, the GC1115 Soft Limiter can safely be
bypassed by clearing bit 5 of the CONTROL register at address 0x3. The Soft Limiter
is only required for output PAR levels below 6 dB, when PDC canceler resources
may become continuously busy. However, at PAR levels below 6 dB, the cEVM and
PCDE levels are also likely to be out of spec, even if the Soft Limiter is enabled.
The soft limiter block is the final block in the GC1115 processing chain. The soft limiter provides a final check of
the output samples values after all four PDC stages, can optionally apply a user-specified, multiplicative
attenuation curve to over-threshold samples. When enabled, the soft limiter limits the output samples to the
SOFT_TSQD threshold-squared value. Values above SOFT_TSQD are adjusted over N samples, where N is
specified by the 2 LSBs in SOFT_LENGTH. Valid values for N are 5, 9, 17, or 33. Longer soft limiter lengths
provide more gradual roll-offs and thus provide smaller ACLR increases when the soft limiter is active.
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A user-specified, normalized taper table (maximum of 16 table entries) is stored starting at address 0xC2. The
taper table entries are read twice: once in the forward direction, and once in the reverse direction. The taper
table is always used starting at SOFT_COEF0.
The inverse gain table (32 entries) works in conjunction with the SOFT_TAB_SCALE value. When the soft
limiter block finds an over-threshold peak, it calculates the difference between the peak’s mag-squared value
and the SOFT_TSQD threshold, and then shifts the difference to the right by SOFT_TAB_SCALE bits. The
resulting value should always be between 0 and 31, as this shifted value is used as the index into the inverse
gain lookup table. If the scaled index is greater than 31, the GC1115 hardware sets the index to 31. The inverse
gain lookup is applied to the taper table and (with a bit of extra math), the scaled taper table values are applied
to the input samples. After this soft limiter processing, the over-threshold peak’s amplitude is reduced to a value
that is just below the SOFT_TSQD threshold.
In pseudo-code, the soft limiter performs the following operations:
//
k is the index of the current sample.
in_pwr = in_I[k] ^ 2 + in_Q[k] ^ 2;
if (in_pwr > SOFT_TSQD) {
//
//
The difference between the current over-threshold sample’s
//
power and the threshold power is a measure of how much
//
over threshold the current sample is.
//
//
Because the inverse gain lookup table has only 32 entries, we
//
must guarantee that the lookup table index does not exceed 31.
//
diff = in_pwr - SOFT_TSQD;
table_index = diff >> SOFT_TAB_SCALE;
if (table_index > 31)
table_index = 31;
//
//
Get the inverse gain for this over-threshold peak. We
//
will use the inverse gain to scale the normalized taper
//
coefficients (SOFT_COEFS).
//
inverse_gain = SOFT_INVGAIN[table_index];
//
//
Scale the tapered gain with the inverse gain, and apply
//
the tapered, scaled values to the input samples
//
//
N is the number of samples in the taper coefficient table.
//
//
We will taper N/2 samples BEFORE the peak and N/2 samples
//
AFTER the peak.
//
j = k - (N/2);
for (i=0; i<N; i++, j++) {
sampleGain = 1 - (inverse_gain * SOFT_COEF[i]);
sample[j] *= sampleGain;
}
}
Output Gain and Offset Operation
The GC1115 includes output gains OUT_GAIN0 and OUT_GAIN1, which can provide up to a 4x increase in the
output signal’s gain. The OUT_GAIN registers allow users to apply a signed 16-bit output gain to both the I and
Q output sample streams just prior to output formatting (rounding to the user-selected number of output bits and
conversion to unsigned binary if requested).
The GC1115 also implements two or four DC offset adjustments (which are applied after the OUT_GAIN0 and
OUT_GAIN1 adjustments) for the I and Q data paths, to adjust for DC offsets in quadrature modulators that may
be present in the transmit chain after GC1115 processing. GC1115 users must calibrate the transmit path to
determine the appropriate values for the OUT_OFFSET_I0, _Q0, _I1, and _Q1 registers. When the GC1115 is
configured for real output, only the OUT_OFFSET_I0 value, and the OUT_OFFSET_I1 value if in two-channel
mode, are used.
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Power Measurement
The GC1115 can measure signal power of a complex I/Q signal at one of two locations in the GC1115 datapath:
• at the input to PDC Stage 1, and
• at the output of PDC Stage 4
The POWER_CTL and POWER_CNT registers configure the GC1115 to measure power at one of these two
locations. The total number of samples observed during power measurement is POWER_CNT ×
POWER_CTL[13:0]. After power measurement has completed, the resulting average power value is available in
the POWER register.
The total number of samples used for the power calculation is the product of an inner loop count (determined by
the POWER_CNT register) and an outer loop count (determined by bits [13:0] of POWER_CTL):
POWER_CNT
--------0x1
0x3
0x7
0xF
inner loop count (# samples)
--------------------------16
256
4096
65536
The outer loop count is specified by the lower 14 bits of the POWER_CTL register, but only the most-significant
"1" matters - the other bits are ignored:
POWER_CTL[13:0]
--------------1
2 3
4 7
8 15
16 31
32 63
64 127
128 255
256 511
512 - 1023
1024 - 2047
2048 - 4095
4096 - 8191
8192 - 16383
outer loop count (# samples)
---------------------------1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
For example, to calculate the average power over about a million samples, the GC1115 registers would be
initialized as follows:
POWER_CNT = 0xF (inner loop count = 65536)
POWER_CTL = 0x10 (outer loop count = 16)
Total # samples used to calculate power: 16 × 65536 = 1 048 576 samples
To summarize, the GC1115 performs the following steps during power measurement:
1. Use 18 bits I and 18 bits Q from each sample to calculate a 37-bit power value
NOTE:
Input samples must be left-justified, i.e. the input sample’s most significant bit is
always aligned to bit 17 (MSB) of input ports IN_A and IN_B.
2. Add the upper 16 bits of each 37-bit power value to a 40-bit power accumulator
3. Accumulate N = POWER_CNT × POWER_CTL[13:0]) sample powers
4. Shift the final accumulator value by 4 to 18 bits to calculate the average power over N samples, depending
on how POWER_CNT and POWER_CTL are set. The GC1115 does this shifting (divide by N) automatically.
5. Transfer the resulting 16 bits to the POWER register.
GC1115 users will also need to set the two MSBs of POWER_CTL properly, to specify whether the input or
output power is to be measured, and (in two-channel configuration) the channel number (channel 0 or channel
1) whose power is to be measured.
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High-Speed Real Output: Odd/Even Mode
When the output sampling rate exceeds 130 MHz (which may occur when the interp-by-4 block is enabled), the
GC1115 provides a high-speed odd-even output mode. This high-speed output mode requires that the
interp-by-4 block is either in interp-by-2, real output mode, or in interp-by-4, real output mode. The special
high-speed output mode is configured using bits [3:2] of IO_MODE (address 0x9): IO_MODE[3:2] = 11.
NOTE:
GC1115 users should only use the odd/even output mode when the output
pin-toggling rate on OUT_A and OUT_B exceeds 130 MHz.
SYNCHRONIZATION
Figure 12 demonstrates the various registers, input and output pins, and functional blocks that are involved in
synchronizing a variety of functional blocks within the GC1115. GC1115 synchronization involves three
functional areas:
• SYNC sources
• SYNC’d functional blocks, and
• SYNC registers
Refer to Figure 12 for the following discussion.
SYNC Sources
The GC1115 uses two hardware SYNC sources (pins), SYNC_A and SYNC_B. SYNC_A or SYNC_B events are
edge-triggered. Because hardware SYNC sources are active-low signals, the SYNC trigger occurs at the rising
edge, i.e. when SYNC is de-asserted.
The GC1115 has two software SYNC sources: SW_TRIGGER and TIMER. The SW_TRIGGER register
generates a trigger signal for each “1” in the SW_TRIGGER register. The SW_TRIGGER has individual SYNC
bits for each of the functional blocks that can be triggered. The software TIMER is a general-purpose, 32-bit
timer that controls the duration of various events, such as the number of samples captured by a snapshot RAM.
The software TIMER can be configured (via bit 15 of TIMER_SYNC) either to run once or periodically, resetting
to its initial value whenever the timer count reaches zero. Whenever the software timer’s count reaches zero (it
is a count-down timer), it generates a timer SYNC event.
Two other SYNC sources are provided for completeness: NEVER (i.e. the functional block will never be
triggered) and ALWAYS (i.e. the functional block will be updated as soon as its corresponding parameter is
updated). For some functional blocks that are comprised of multiple registers (such as the snapshot RAMs or
the cancellation coefficients), the ALWAYS state is invalid.
NOTE:
Setting a functional block’s SYNC register to NEVER is not the same as disabling the
functional block!
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Functional Blocks and SYNC Registers
The operation of thirteen GC1115 functional blocks can be triggered by one of the SYNC sources:
• The receive block (GC1115 input) [use only SYNC_A or SYNC_B!]
• The pipeline stages [use only SYNC_A or SYNC_B!]
• The decimation function (to select a particular input sample phase) [use only SYNC_A or SYNC_B!]
• The software timer
• The PDC stage delay values (CANCEL_DELAY registers)
• The cancellation pulse coefficient shadow RAM
• The canceler RAM allocation variables (RESOURCE_CNT registers)
• The interpolate-by-4 block [use only SYNC_A or SYNC_B!]
• The output gain registers (OUT_GAIN0 and OUT_GAIN1)
• The SYNC_OUT pin (for debugging or for synchronizing multiple GC1115s)
• The signal generator functions
• Snapshot RAM A
• Snapshot RAM B
As shown in Table 16, SYNC selection registers control which SYNC source is assigned to each functional
block. Table 16 summarizes the SYNC source selection encoding, using the 3 LSBs of each SYNC register.
Table 16. SYNC Register Source Selection
34
SYNC SELECTION
SYNC REGISTER VALUE
(3 LSBs)
NEVER
0
SW_TRIGGER
1
TIMER
2
SYNC_A
3
SYNC_B
4
ALWAYS
5
(reserved)
6
(reserved)
7
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Input Pins:
Microprocessor
write
SYNC_A SYNC_B
”NEVER”
SW_TRIGGER
SYNC
Sources
Timer
trigger
”ALWAYS”
TIMER
RCV_SYNC
Receive Block
STAGE_SYNC
Pipeline Stage Blocks
DECIM_SYNC
Decimate Block
TIMER_SYNC
SW Timer Block
DELAY_SYNC
Cancel Delay Block
CANCEL_SYNC
Cancel Coef Block
RESOURCE_SYNC
Cancel Resource Blk
INTERP_SYNC
Interp−by−4 Block
OUTGAIN_SYNC
OUT_GAIN0, 1 values
OUTPIN_SYNC
SYNC_OUT_ pin
SIG_GEN_SYNC
Signal Gen, CRC control
SNAP_A_SYNC
Snap A RAM
SNAP_B_SYNC
Snap B RAM
SYNC
Registers
Functional
Blocks
Figure 12. GC1115 Synchronization Elements
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REGISTER MAP
Global Registers (Addresses 0 – 14)
RESET
0x0
Type: Read/Write Value at RESET: 0x0033
The RESET register provides separate bits to reset the GC1115 registers, the datapath, and the two PLLs.
Writing a 1 at a given bit location resets the functions mapped to that bit. Multiple bits can be set during each
write to the RESET register. The RESET register is unclocked, i.e. IN_CLK does not have to be toggling to
change RESET.
BITS
Configuration Reset
0 = running
1 = reset
1
Datapath Reset
0 = running
1 = reset
[3:2]
Reserved
4
CORE_PLL Reset
0 = running
1 = reset
5
TX_PLL Reset
0 = running
1 = reset
[16:6]
PLL_CONTROL
DESCRIPTION
0
0x1
Reserved
Type: Read/Write Value at RESET: 0x0000
The PLL_CONTROL register provides separate bits to control the GC1115’s core and transmit PLLs. The
PLL_CONTROL register is unclocked, i.e. IN_CLK does not have to be toggling to change
PLL_CONTROL.
Figure 7 demonstrates how the various bits of the PLL_CONTROL and CLK_CONTROL registers interact to
determine various GC1115 clock frequencies.
BITS
[1:0]
00: PLL_CLL = IN_CLK
01: PLL_CLK = 2 × IN_CLK
10: Reserved
11: PLL_CLK = 4 × IN_CLK
[7:2]
Reserved
[9:8]
Transmit PLL Control:
[15:10]
36
DESCRIPTION
Core PLL Control:
00: PLL_CLL = IN_CLK
01: PLL_CLK = 2 × IN_CLK
10: Reserved
11: PLL_CLK = 4 × IN_CLK
Reserved
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CLK_CONTROL
0x2
Type: Read/Write Value at RESET: 0x1310
The CLK_CONTROL register provides separate bits to control the GC1115’s input, core, and output clocks. The
CLK_CONTROL register is unclocked, i.e. IN_CLK does not have to be toggling to change
CLK_CONTROL.
Figure 7 demonstrates how the various bits of the PLL_CONTROL and CLK_CONTROL registers interact to
determine various GC1115 clock frequencies.
BITS
[1:0]
DESCRIPTION
OUT_CLK source:
00: CLK_TX (after pad)
01: CLK_CORE (before buf)
10: CLK_CORE (after
buf)
11: CLK_TX (before pad)
2
IN_CLK edge selector
0 = rising, 1 = falling
3
PLL bypass
0 = use PLLs, 1 = bypass PLLs
[5:4]
Input clock rate:
00 – OFF
01 – inClk = PLL_CLK / 4
10 – inClk = PLL_CLK /
2
11 – inClk = PLL_CLK
[7:6]
Reserved
[9:8]
Core clock rate:
00 – OFF
01 – coreClk = PLL_CLK / 4
10 – coreClk = PLL_CLK 11 – coreClk = PLL_CLK
/2
[11:10]
Reserved
[13:12]
Output clock rate:
00 – OFF
01 – outClk = PLL_CLK / 4
10 – outClk = PLL_CLK / 11 – outClk = PLL_CLK
2
[15:14]
CONTROL
0x3
Reserved
Type: Read/Write Value at RESET: 0x0000
The CONTROL register provides separate bits to enable or to bypass the four peak detection and cancellation
(PDC) stages, the interpolate-by-4 block, and the soft limiter. If all bits are cleared, the GC1115 is in bypass
mode, during which no peaks are processed but the samples still flow through the GC1115’s internal delay
buffers.
BITS
DESCRIPTION
0
PDC Stage 1
0 = bypassed, 1 = enabled
1
PDC Stage 2
0 = bypassed, 1 = enabled
2
PDC Stage 3
0 = bypassed, 1 = enabled
3
PDC Stage 4
0 = bypassed, 1 = enabled
4
Interpolator
0 = bypassed, 1 = enabled
5
Soft limiter
0 = bypassed, 1 = enabled
[15:6]
Reserved
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INT_MAP
0x4
Type: Read/Write Value at RESET: 0x0000
The INT_MAP register indicates the reason(s) for a GC1115-initiated interrupt on the INT pin. Read INT_MAP to
determine whether that condition occurred (indicated by a “1”). Write a “1” to individual bits of INT_MAP to clear
(reset) specific interrupt conditions. INT_MAP operates in conjunction with INT_MASK (0x5) in generating an
INT signal.
The INT_MAP and INT_MASK registers work together to control interrupt sources that trigger the INT (interrupt)
output pin, which is normally tied to the hardware interrupt pin of the microprocessor or DSP chip that controls
the GC1115. Setting one or more bits of the INT_MASK register unmasks (enables) the corresponding interrupt
source in the INT_MAP register. The GC1115 contains eight possible interrupt sources. When the
microprocessor receives a signal on its INT pin, INT_MAP should be read to determine the specific cause (or
causes) of the interrupt.
BITS
0
Snapshot RAM A capture/histogram completion
1
Snapshot RAM B capture/histogram completion
2
Snapshot RAM A histogram bin overflow
3
Snapshot RAM B histogram bin overflow
4
Timer counted down to zero
5
Input power measurement completed
6
Cancellation update has completed
7
CRC is available in the CRC_RESULT register
[15:8]
INT_MASK
DESCRIPTION
0x5
Reserved
Type: Read/Write Value at RESET: 0x0000
The INT_MASK register determines whether the corresponding individual interrupt conditions in the INT_MAP
register will cause an INT interrupt. A “0” in a bit position disables the condition from causing an INT interrupt. A
“1” in a bit position allows the condition to cause an INT interrupt. The INT_MAP and INT_MASK registers work
together to control interrupt sources that trigger the INT (interrupt) output pin, which is normally tied to the
hardware interrupt pin of the microprocessor or DSP chip that controls the GC1115. Setting one or more bits of
the INT_MASK register unmasks (enables) the corresponding interrupt source in the INT_MAP register.
BITS
Snapshot RAM A capture/histogram completed: disable (0) or enable (1) interrupt
1
Snapshot RAM B capture/histogram completed: disable (0) or enable (1) interrupt
2
Snapshot RAM A histogram bin overflow occurred: disable (0) or enable (1) interrupt
3
Snapshot RAM B histogram bin overflow occurred: disable (0) or enable (1) interrupt
4
Timer counted down to zero:
disable (0) or enable (1)
5
Input power measurement
completed:
disable (0) or enable (1)
6
Cancellation update
completed:
disable (0) or enable (1)
7
CRC available in
CRC_RESULT:
disable (0) or enable (1)
[15:8]
38
DESCRIPTION
0
Reserved
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MASK_REV
0x6
Type: Read Only
Value at RESET: 0x0001 (HW-version dependent)
The MASK_REV register allows the controlling microprocessor or DSP to determine the hardware revision of a
particular GC1115. MASK_REV is useful in determining, via software, which version of the GC1115 is present
on a board or in a system, in the event that different functionality exists in two or more revisions of GC1115
silicon.
BITS
[15:0]
SW_TRIGGER
0x7
DESCRIPTION
GC1115 mask revision (a 16-bit, non-zero value)
Type: Read/Write Value at RESET: 0x0000
The SW_TRIGGER register is a software trigger source that can synchronize one or more of thirteen internal
GC1115 components via software command. If a component’s SYNC register (from Address 0x19 to Address
0x25) selects SW_TRIG as its SYNC source, setting that component’s bit in the SW_TRIGGER register will sync
the component. The GC1115 automatically clears the SW_TRIGGER bits after the trigger occurs.
BITS
DESCRIPTION
0
RCV_SYNC (receive datapath)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
1
STAGE_SYNC (PDC stage)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
2
DECIM_SYNC (decimator)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
3
TIMER_SYNC (SW timer)
0 = no effect, 1 = trigger
4
DELAY_SYNC (apply CANCEL_DELAY)
0 = no effect, 1 = trigger
5
CANCEL_SYNC (change cancel coefs)
0 = no effect, 1 = trigger
6
RESOURCE_SYNC (apply
RESOURCE_CNT)
0 = no effect, 1 = trigger
7
INTERP_SYNC (sync interp-by-4 block)
0 = no effect, 1 = trigger (SW_TRIGGER not
recommended)
8
OUTGAIN_SYNC (change outgain)
0 = no effect, 1 = trigger
9
OUTPIN_SYNC (apply OUT_SYNC)
0 = no effect, 1 = trigger
10
SIG_GEN_SYNC (signal generator)
0 = no effect, 1 = trigger
11
SNAP_A_SYNC (Snapshot RAM A)
0 = no effect, 1 = trigger
12
SNAP_B_SYNC (Snapshot RAM B)
0 = no effect, 1 = trigger
[15:13]
Reserved
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IO_CONTROL
0x8
Type: Read/Write Value at RESET: 0x0000
The IO_CONTROL register controls various input and output port characteristics.
BITS
Input port format
0 = 2's complement
1 = unsigned
1
Output port format
0 = 2's complement
1 = unsigned
2
Output Port A enable (1)
0 = high-impedance
state
1 = enabled
3
Output Port B enable (1)
0 = high-impedance
state
1 = enabled
4
Output “force zeros (2)
0 = normal
1 = "force zeros"
[6:5]
Output sample width (3)
(2)
(3)
(4)
IO_MODE
00: 18 bits
01: 16 bits
10: 14 bits
11: 12 bits
7
Reserved
8
Non-Port Output Enable (4) 0 = high-impedance
state
[15:9]
(1)
DESCRIPTION
0
1 = driven
Reserved
If Bit 2 AND Bit 3 are both zeros, OUT_CLK, OUT_IQ_SEL, SYNC_OUT, and INT will all be put into a
high-impedance state.
When forcing zeros, the output port format (Bit 1) determines the values used to drive the output ports.
Two's complement drives the output ports with all zeros, while unsigned drives the output ports with a
“1” for the MSB and zeros for all other output bits.
The output samples are always MSB-justified. Bits [6:5] simply determine the GC1115’s internal
convergent rounding point for the output samples.
Bit 8 affects all output pins (OUT_CLK, OUT_IQ_SEL, SYNC_OUT, and INT) except Port A and Port B
pins, which are separately enabled using Bits 2 and 3.
0x9
Type: Read/Write Value at RESET: 0x0000
The IO_CONTROL register controls various input and output port characteristics.
BITS
DESCRIPTION
0
Number of channels
0 = one channel
1 = two channels
1
Input port I/Q mux
0 = parallel
1 = muxed
[3:2]
Bits [3:2]: One-channel output port mode:
Bits 3:2
OUT_A
OUT_B
00
Reserved
Reserved
01 (complex)
I/Q muxed samples
(not used)
10 (complex)
I sample
Q sample
11 (real)
Samples 0, 2, 4, . . .
Samples 1, 3, 5, . . .
During two-channel operation, the interp-by-4 mode determines which samples are carried
on Ports A and B:
[15:4]
40
Interp-b-4 mode
OUT_A
OUT_B
Bypass
Channel 0, I/Q muxed
Channel 1, I/Q muxed
2x (complex)
Channel 0, I/Q muxed
Channel 1, I/Q muxed
2x (real)
Channel 0, real samples
Channel 1, real samples
4x (real)
Channel 0, real samples
Channel 1, real samples
Reserved
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POWER_CTL
0xA (10) Type: Read/Write Value at RESET: 0x0000
The POWER_CTL register controls various power measurement parameters. Power measurement begins
automatically when bits [13:0] of POWER_CTL contain a non-zero value. The results of power measurement are
returned in the POWER register. The microprocessor controlling the GC1115 can request an interrupt at the
conclusion of power measurement by setting Bit 5 of INT_MASK (address 0x5).
BITS
[13:0]
(1)
(2)
POWER
DESCRIPTION
Number of POWER_CNT
8191).
blocks (1)
used to measure the average power (a value from 0 to
14
Measure in/out power
0 = input
15
Measure Channel 0/Channel 1
power (2)
0 = Channel 0 1 = Channel 1
1 = output
The number of samples per block is specified in the POWER_CNT register (address 0x7F). Normally
POWER_CNT is set to 0xFFFF (65,536 samples per block).
During one-channel operation, setting POWER_CTL[15] to 1 will result in unpredictable power
measurements!
0xB (11) Type: Read Only
Value at RESET: 0x0000
The POWER register contains the results of a power measurement process that was initiated according to the
parameters in the POWER_CTL register. The microprocessor controlling the GC1115 can request an interrupt at
the conclusion of power measurement by setting Bit 5 of INT_MASK (address 0x5).
BITS
[15:0]
DECIMATE
DESCRIPTION
Average power measurement (0x0000 to 0xFFFF)
0xC (12) Type: Read/Write Value at RESET: 0x0001
The DECIMATE register determines the decimation factor at the input of the GC1115. When set to 2, only every
second input sample is processed by the GC1115 datapath. A decimation factor of 2 is only required when input
clock rates below 25 MHz or above 75 MHz are used. When DECIMATE = 2, the GC1115 user must provide a
properly aligned synchronization signal (normally SYNC_A or SYNC_B) to select which input sample phase is
used to align the GC1115’s decimator. The DECIM_SYNC register selects the source of the decimator’s SYNC
signal.
BITS
[1:0]
DESCRIPTION
Decimation factor:
01: no decimation
[15:2]
TIMER_HI_RST
10: decimate by 2
Reserved
0xD (13) Type: Read/Write Value at RESET: 0x0000
The TIMER_HI_RST and TIMER_LO_RST registers (each 16 bits wide) determine the reset value of the
GC1115’s programmable software timer. This timer can be enabled to control the occurrence of SYNC events
during GC1115 processing. TIMER_HI_RST and TIMER_LO_RST are combined into a 32-bit unsigned value
that is clocked with every internal GC1115 clock. The TIMER_HI_RST and TIMER_LO_RST registers operate in
conjunction with the TIMER_SYNC register.
BITS
[15:0]
DESCRIPTION
Upper 16 bits of the GC1115’s 32-bit timer reset value.
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TIMER_LO_RST
0xE (14) Type: Read/Write Value at RESET: 0x0000
The TIMER_LO_RST and TIMER_HI_RST registers (each 16 bits wide) determine the reset value of the
GC1115’s programmable software timer. This timer can be enabled to control the occurrence of SYNC events
during GC1115 processing. TIMER_HI_RST and TIMER_LO_RST are combined into a 32-bit unsigned value
which is clocked with every internal GC1115 clock. The TIMER_HI_RST and TIMER_LO_RST registers operate
in conjunction with the TIMER_SYNC register.
BITS
[15:0]
DESCRIPTION
Lower 16 bits of the GC1115’s 32-bit timer reset value.
Cancellation Coefficient Registers (Addresses 15 – 20)
CANCEL_MODE
0xF (15) Type: Read/Write Value at RESET: 0x0000
The CANCEL_MODE register sets the characteristics of the cancellation coefficients. The GC1115 operates
using either real (symmetric carrier spectra) or complex (asymmetric carrier spectra) cancellation coefficients.
For symmetric spectra, the cancellation coefficients can also be unique or mirrored. Mirrored coefficients are
only needed when a cancellation pulse with more than 255 coefficients is desired. [Note: cancellation pulses
with about 100 unique coefficients are more than adequate to meet all 3G or cdma2000 requirements].
Mirrored mode is also useful because only half of the coefficients need be downloaded, thus shortening the time
required to provide the GC1115 with a new set of cancellation coefficients. When mirrored mode is used, the
GC1115 applies N real cancellation coefficients in the following order:
coef[0], coef[1], …, coef[N-2], coef[N-1], coef[N-2], …, coef[1], coef[0]
Bits [11:8] of CANCEL_MODE contain a peak hysteresis (timeout) count whose value is determined during
cancellation pulse design. Under most operating conditions, the hysteresis count is zero. However, for some
configurations with large gaps between carriers (“missing” carriers), the hysteresis count will have a non-zero
value of 6 or less. Please contact TI to determine how to calculate the peak hysteresis count for your
cancellation coefficients.
BITS
42
DESCRIPTION
0
Cancel coef format
0 = real
1 = complex
1
Mirrored coefs
0 = unique
1 = mirrored
[7:2]
Reserved
[11:8]
Peak hysteresis count (0
to 6)
[15:12]
Reserved
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CANCEL_LENGTH
0x10 (16)
Type: Read/Write Value at RESET: 0x0000
The CANCEL_LENGTH register determines the number of unique cancellation coefficients present in each
cancellation pulse (ignoring the “mirror” mode bit of the CANCEL_MODE register). The CANCEL_LENGTH must
be an odd value. See Table 10, Table 11, and Table 12 for details on the proper use of CANCEL_LENGTH.
Note that CANCEL_LENGTH and CANCEL_DELAY are related – see the discussion in the earlier section
entitled CANCEL_LENGTH and CANCEL_DELAY.
BITS
[7:0]
[15:8]
DESCRIPTION
Number of unique cancellation coefficients:
For real coefficients:
odd number from 5 to 255
For complex
coefficients:
odd number from 5 to 127
Reserved
NOTE:
In most circumstances, CANCEL_LENGTH should be at least 15. For 3GPP
processing, CANCEL_LENGTH of 101 or less achieves all relevant requirements.
CANCEL_ADDR
0x11 (17)
Type: Read/Write
Value at RESET: 0x0000
The CANCEL_ADDR register is used to access the GC1115 shadow RAM memory. The earlier Cancellation
Coefficient Shadow RAM section described the structure of the cancellation coefficient shadow RAM. After
writing a unique address (from 0 to 767) to CANCEL_ADDR, subsequent writes to (or reads from) the
CANCEL_DATA register will auto-increment CANCEL_ADDR. The auto-increment and direct address modes
were described earlier in Writing Cancellation Coefficients to the GC1115.
BITS
[9:0]
[15:10]
CANCEL_DATA
DESCRIPTION
Cancellation coefficient shadow RAM memory address (0 to 767)
Reserved
0x12 (18)
Type: Read/Write
Value at RESET: 0x0000
The CANCEL_DATA register holds the 12-bit value to be written to (or read from) GC1115 cancellation
coefficient shadow RAM. The structure of the cancellation coefficient memory is described in Cancellation
Coefficient Shadow RAM. After writing a unique address (from 0 to 767) to CANCEL_ADDR, subsequent writes
to (or reads from) the CANCEL_DATA register will auto-increment CANCEL_ADDR.
BITS
[15:0]
DESCRIPTION
Value written to (or read from) cancellation coefficient shadow RAM at the address
specified in CANCEL_ADDR.
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RESOURCE_MASK
0x13 (19)
Type: Read/Write Value at RESET: 0x00FF
The RESOURCE_MASK register contains an 8-bit field that determines which canceler RAMs will be initialized
after a CANCEL_SYNC trigger. By setting RESOURCE_MASK one bit at a time, canceler RAMs can be
updated one at a time. If all canceler RAMs were updated at the same time, there would be some short time
period (a few microseconds) in which no cancelers would be active. During this time, over-threshold peaks
would pass through the GC1115 without being canceled, which may be undesirable. Changing canceler RAMs
one PDC stage at a time allows subsets of canceler RAMs to be modified without disabling all cancelers.
BITS
DESCRIPTION
0
Canceler RAM 0 update
status:
0 = do not update
1 = update
1
Canceler RAM 1 update
status:
0 = do not update
1 = update
2
Canceler RAM 2 update
status:
0 = do not update
1 = update
3
Canceler RAM 3 update
status:
0 = do not update
1 = update
4
Canceler RAM 4 update
status:
0 = do not update
1 = update
5
Canceler RAM 5 update
status:
0 = do not update
1 = update
6
Canceler RAM 6 update
status:
0 = do not update
1 = update
7
Canceler RAM 7 update
status:
0 = do not update
1 = update
[15:8]
Reserved
NOTE:
The GC1115 user must ensure that the values in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 sum to 8 or less,
since there are only 8 canceler RAMs.
DELAY_MASK
0x14 (20)
Type: Read/Write
Value at RESET: 0x00FF
The DELAY_MASK register determines which peak detect and cancel (PDC) stages are updated when the
CANCEL_DELAY value is changed (i.e. when a DELAY_SYNC event occurs). Each of the four PDC stages has
its own CANCEL_DELAY value, so that different cancellation pulse delays could in theory be used by each PDC
stage. Under normal circumstances, however, CANCEL_DELAY will be identical for all PDC stages, since the
same cancellation pulse is normally stored in all canceler RAMs.
BITS
PDC Stage 0 update
status:
0 = do not update
1 = update
1
PDC Stage 1 update
status:
0 = do not update
1 = update
2
PDC Stage 2 update
status:
0 = do not update
1 = update
3
PDC Stage 3 update
status:
0 = do not update
1 = update
[15:4]
44
DESCRIPTION
0
Reserved
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Signal Generator and CRC Registers (Addresses 21– 24)
SIG_GEN_CTL
0x15 (21)
Type: Read/Write
Value at RESET: 0x0000
The SIG_GEN_CTL register controls the operation of a signal generator. When enabled, the signal generator’s
outputs feed the I and Q inputs of PDC Stage 1. In pseudo-LFSR mode, the GC1115 generates a signal with a
PAR of approximately 10 dB. In order to properly generate a periodic signal and its related periodic CRC, the
GC1115 must be initialized by parameters provided by TI. If CRC generation is not required, the CRC_RESULT
register can simply be ignored, and the signal generator can be used without any restrictions.
Bit 7 of INT_MAP indicates when the CRC result is available. When Bit 7 of INT_MASK is set, the GC1115 will
interrupt the controlling microprocessor or DSP to indicate that the CRC_RESULT register can be read. Once
this bit is set, the microprocessor or DSP must manually clear Bit 7 of INT_MAP prior to subsequent “CRC result
available” interrupts.
BITS
[1:0]
DESCRIPTION
Signal generator and CRC control:
00 = Signal Generator and CRC Generator are DISABLED
01 = Signal Generator in DC or sawtooth mode (CRC enabled)
if SIG_GEN_INC = 0, generate DC value of SIG_GEN_BASE
if SIG_GEN_INC > 0, generate a sawtooth waveform
10 = pseudo-LFSR with 10 dB PAR (CRC generator enabled)
11 = External (CRC generator enabled)
[15:2]
SIG_GEN_BASE
Reserved
0x16 (22)
Type: Read/Write
Value at RESET: 0x0000
The SIG_GEN_BASE register specifies the output value for DC signal generation, or the starting accumulator
value for sawtooth signal generation. While SIG_GEN_BASE is a 16-bit value, the GC1115 DC/sawtooth signal
generator uses an 18-bit signed accumulator. SIG_GEN_BASE initializes the 16 LSBs of this 18-bit accumulator,
with proper sign extension. If bit 15 of SIG_GEN_BASE is set, bits 17, 16, and 15 of the internal 18-bit
accumulator will also be set. If bit 15 of SIG_GEN_BASE is clear, bits 17, 16, and 15 of the internal 18-bit
accumulator will also be clear. When the signal generator is enabled in DC or sawtooth mode, the 18-bit
accumulator value drives the 18-bit I input of PDC Stage 1. The bit-reversed version of the 18-bit accumulator
drives the 18-bit Q input of PDC Stage 2.
If GC1115 users want to observe the signal generator output at OUT__A and OUT__B, the detection and gain
thresholds for all enabled PDC stages should be set to 0xFFFF (i.e. no peaks will be found). Alternately, there
are two ways of achieving this: 1. All PDC stages are disabled in the CONTROL register, 2. No cancelers are
assigned to any PDC stages (using the four RESOURCE_CNT registers).
BITS
[15:0]
SIG_GEN_INC
DESCRIPTION
Signal generator accumulator value (for DC and sawtooth signals)
[initial value of a signed, 18-bit internal accumulator]
0x17 (23)
Type: Read/Write
Value at RESET: 0x0000
The SIG_GEN_INC register specifies the signed increment value for sawtooth signal generation. At each
IN_CLK, the signal generator adds the signed, 16-bit SIG_GEN_INC value to the current 18-bit accumulator.
BITS
[15:0]
DESCRIPTION
Signal generator increment value (for sawtooth signals)
[increment value applied to a signed, 18-bit internal accumulator]
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CRC_RESULT
0x18 (24)
Type: Read Only
Value at RESET: 0x0000
The CRC_RESULT register holds the CRC generator value. The signal generator must be properly configured to
ensure a periodic signal for the CRC_RESULT to be repeatable. The SIG_GEN_SYNC event must have the
same period as the signal generator, otherwise the CRC_RESULT will be invalid. Contact TI to receive an
appropriate set of signal generator configuration and CRC_RESULT values.
BITS
[15:0]
DESCRIPTION
CRC result (reaches steady state after four SIG_GEN_SYNC events)
Synchronization Registers (Addresses 25 – 37)
RCV_SYNC
0x19 (25)
Type: Read/Write
Value at RESET: 0x0000
The RCV_SYNC register selects the synchronization source for the GC1115’s receive datapath. SYNC_A or
SYNC_B must be used as the RCV_SYNC source.
BITS
[2:0]
[15:3]
STAGE_SYNC
DESCRIPTION
RCV_SYNC selection:
0: invalid
1: invalid
2: invalid
3: SYNC_A
4: SYNC_B
5: invalid
6: invalid
7: invalid
Reserved
0x1A (26)
Type: Read/Write
Value at RESET: 0x0000
The STAGE_SYNC register selects the synchronization source for the GC1115’s PDC stages. SYNC_A or
SYNC_B must be used as the STAGE_SYNC source.
BITS
[2:0]
[15:3]
DECIM_SYNC
DESCRIPTION
STAGE_SYNC selection:
0: invalid
1: invalid
2: invalid
3: SYNC_A
4: SYNC_B
5: invalid
6: invalid
7: invalid
Reserved
0x1B (27)
Type: Read/Write
Value at RESET: 0x0000
The DECIM_SYNC register selects the synchronization source for the GC1115’s decimator. Because the
decimator processes input samples, a hardware synchronization source (SYNC_A or SYNC_B) must be used
when DECIMATE = 2, allowing the user to select which phase of the input signal stream is processed by the
decimator.
BITS
[2:0]
[15:3]
46
DESCRIPTION
STAGE_SYNC selection:
0: invalid
1: invalid
2: invalid
3: SYNC_A
4: SYNC_B
5: invalid
6: invalid
7: invalid
Reserved
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TIMER_SYNC
0x1C (28)
Type: Read/Write Value at RESET: 0x0000
The TIMER_SYNC register selects the synchronization source for the GC1115’s software timer. In addition, Bit
15 of TIMER_SYNC determines whether the software timer runs once (Bit 15 = 0) or runs repeatedly (Bit 15 =
1).
BITS
[2:0]
[14:3]
15
DELAY_SYNC
DESCRIPTION
STAGE_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
Timer repeat:
0x1D (29)
0: do not repeat (run
once)
Type: Read/Write
1: repeat
Value at RESET: 0x0000
The DELAY_SYNC register selects the synchronization source that triggers the GC1115’s CANCEL_DELAY
being copied to PDC stages selected by DELAY_MASK. Under normal circumstances, all cancel RAMs contain
the same set of cancellation coefficients. When this is the case, DELAY_MASK is set to 0xF, and
CANCEL_DELAY1 thru CANCEL_DELAY4 are copied to their respective internal registers as soon as
DELAY_SYNC is triggered. Under normal circumstances, DELAY_SYNC can be set to ALWAYS, i.e. as soon as
CANCEL_DELAY1 thru CANCEL_DELAY4 are written, their corresponding internal registers are immediately
updated.
BITS
[2:0]
[15:3]
CANCEL_SYNC
DESCRIPTION
DELAY_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
0x1E (30)
Type: Read/Write
Value at RESET: 0x0000
The CANCEL_SYNC register selects the synchronization source that causes the GC1115’s cancel coefficient
shadow RAM values to be copied to the canceler RAMs whose corresponding RESOURCE_MASK bit is set. At
GC1115 initialization, all cancel RAMs are normally initialized using the same set of cancellation coefficients.
When this occurs, RESOURCE_MASK is set to 0xFF and the shadow RAM coefficients are copied to all
canceler RAMs as soon as the CANCEL_SYNC trigger occurs. It is convenient for the microprocessor or DSP to
use SW_TRIGGER as the CANCEL_SYNC source. As soon as the shadow RAM has been initialized, the
microprocessor or DSP can then simply write a 0x20 to SW_TRIGGER, causing a trigger that only affects the
CANCEL_SYNC functional block.
BITS
[2:0]
[15:3]
DESCRIPTION
CANCEL_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
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RESOURCE_SYNC
0x1F (31)
Type: Read/Write Value at RESET: 0x0000
The RESOURCE_SYNC register determines the synchronization source when canceler resources are allocated
or re-allocated. The GC1115 contains a total of 32 cancelers, which can be assigned in groups of four to the four
PDC stages. Each stage contains a RESOURCE_CNT register that specifies how many canceler RAMs (0 to 8)
are assigned to that stage. The canceler allocation changes when the RESOURCE_SYNC trigger occurs. The
RESOURCE_SYNC register determines the source of the trigger event that configures the GC1115 with the
specified RESOURCE_CNT values. It is convenient for the microprocessor or DSP to use SW_TRIGGER as the
RESOURCE_SYNC source. As soon as the RESOURCE_CNT registers have been initialized, the
microprocessor or DSP can then simply write a 0x40 to SW_TRIGGER, causing a sync event that only affects
the RESOURCE_SYNC functional block.
BITS
[2:0]
[15:3]
INTERP_SYNC
DESCRIPTION
RESOURCE_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
0x20 (32)
Type: Read/Write Value at RESET: 0x0000
The INTERP_SYNC register determines the synchronization source for the GC1115’s interpolator. The
GC1115’s interpolator operates in four modes:
1. Bypass,
2. 2x interp (real output, fs/4),
3. 2x interp (complex output),
4. 4x interp (real output, fs/4).
To ensure proper operation in the non-bypass interpolator modes, the GC1115 interpolator must use either
SYNC_A or SYNC_B as its synchronization source.
BITS
[2:0]
[15:3]
OUTGAIN_SYNC
DESCRIPTION
INTERP_SYNC selection:
0: invalid
1: invalid
2: invalid
3: SYNC_A
4: SYNC_B
5: invalid
6: invalid
7: invalid
Reserved
0x21 (33)
Type: Read/Write Value at RESET: 0x0000
The OUTGAIN_SYNC register determines the synchronization source for the GC1115’s output gain and offset
values, stored in the OUT_GAIN0, OUT_GAIN1, OUT_OFFSET_I0, OUT_OFFSET_I1, OUT_OFFSET_Q0, and
OUT_OFFSET_Q1 registers. OUTGAIN_SYNC can normally be set to ALWAYS, so that the microprocessor or
DSP’s writing to the OUT_GAINx and OUT_OFFSETy registers immediately causes the change. All OUT_GAIN
and OUT_OFFSET registers are modified when the OUT_SYNC trigger occurs.
BITS
[2:0]
[15:3]
48
DESCRIPTION
OUTGAIN_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
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OUTPIN_SYNC
0x22 (34)
Type: Read/Write Value at RESET: 0x0000
The OUTPIN_SYNC register determines the synchronization source for the SYNC_OUT pin. Because the
SYNC_OUT pin is often used to synchronize hardware that follows the GC1115, OUTPIN_SYNC is normally set
to SYNC_A or SYNC_B.
BITS
[2:0]
[15:3]
SIG_GEN_SYNC
DESCRIPTION
OUTPIN_SYNC
selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
0x23 (35)
Type: Read/Write
Value at RESET: 0x0000
The SIG_GEN_SYNC register determines the synchronization source for the GC1115’s internal signal
generator. After the SIG_GEN_CTL, SIG_GEN_BASE, and SIG_GEN_INC registers have been initialized, a
SIG_GEN_SYNC trigger starts the signal generator. It is convenient for the microprocessor or DSP to use
SW_TRIGGER as the SIG_GEN_SYNC source. As soon as the SIG_GEN_CTL, SIG_GEN_BASE, and
SIG_GEN_INC registers have been initialized, the microprocessor or DSP can then simply write a 0x400 to
SW_TRIGGER, causing a sync event that only affects the SIG_GEN_SYNC functional block.
BITS
[2:0]
[15:3]
DESCRIPTION
SIG_GEN_SYNC
selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
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SNAP_A_SYNC
0x24 (36)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_A_SYNC register determines the synchronization source for the GC1115’s Snapshot RAM A. After
the appropriate SNAP_A registers (from SNAP_A_CONTROL to SNAP_A_HISTCOUNT) have been initialized, a
SNAP_A_SYNC trigger enables Snapshot RAM A. Snapshot RAM A can be triggered either by software or by
hardware. If a particular Snapshot RAM A timing relationship must be established with the input samples,
SNAP_A_SYNC should be associated with SYNC_A or SYNC_B. Alternately, the microprocessor or DSP can
initiate a Snapshot RAM A capture by assigning SW_TRIGGER as the SNAP_A_SYNC event. Snapshot RAM A
and Snapshot RAM B can operate simultaneously, and both may be triggered by the same SYNC event.
NOTE:
SNAP_A_SYNC cannot be associated with a repeating TIMER trigger.
BITS
[2:0]
[15:3]
SNAP_B_SYNC
DESCRIPTION
SNAP_A_SYNC
selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
0x25 (37)
Type: Read/Write Value at RESET: 0x0000
The SNAP_B_SYNC register determines the synchronization source for the GC1115’s Snapshot RAM B. After
the appropriate SNAP_B registers (from SNAP_B_CONTROL to SNAP_B_HISTCOUNT) have been initialized, a
SNAP_B_SYNC trigger enables Snapshot RAM B. Snapshot RAM B can be triggered either by software or by
hardware. If a particular Snapshot RAM B timing relationship must be established with the input samples,
SNAP_B_SYNC should be associated with SYNC_A or SYNC_B. Alternately, the microprocessor or DSP can
initiate a Snapshot RAM B capture by assigning SW_TRIGGER as the SNAP_B_SYNC event. Snapshot RAM A
and Snapshot RAM B can operate simultaneously, and both may be triggered by the same SYNC event.
NOTE:
SNAP_B_SYNC cannot be associated with a repeating TIMER trigger.
BITS
[2:0]
[15:3]
50
DESCRIPTION
SNAP_B_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
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Cancellation Stage Control Registers (Addresses 48 – 75)
RESOURCE_CNT1
0x30 (48)
Type: Read/Write
Value at RESET: 0x0000
The RESOURCE_CNT1 register specifies how many canceler RAMs are associated with PDC Stage 1.
RESOURCE_CNT1 contains a value between 0 and 8. The sum of canceler RAMs in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 must be 8 or less. Resource allocations
become effective only after a RESOURCE_SYNC event occurs. The RESOURCE_SYNC register selects the
source of the RESOURCE_SYNC event.
BITS
DETECT_TSQD1
DESCRIPTION
[3:0]
Number of canceler RAMs assigned to PDC Stage 1 (from 0 to 8)
[15:4]
Reserved
0x31 (49)
Type: Read/Write
Value at RESET: 0x0000
The DETECT_TSQD1 register contains the detection threshold-squared value for PDC Stage 1. The detection
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 1 whose magnitude is above DETECT_TSQD1 will be decreased to the
magnitude-squared value specified in GAIN_TSQD1, assuming that PDC Stage 1 has an available canceler.
BITS
[15:0]
GAIN_TSQD1
DESCRIPTION
Detection threshold-squared value for PDC Stage 1.
0x32 (50)
Type: Read/Write
Value at RESET: 0x0000
The GAIN_TSQD1 register contains the gain threshold-squared value for PDC Stage 1. The gain
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 1 whose magnitude is above DETECT_TSQD1 will be decreased to the
magnitude-squared value specified in GAIN_TSQD1, assuming that PDC Stage 1 has an available canceler.
BITS
[15:0]
CANCEL_DELAY1
DESCRIPTION
Gain threshold-squared value for PDC Stage 1.
0x33 (51)
Type: Read/Write
Value at RESET: 0x0000
The CANCEL_DELAY1 register contains the PDC Stage 1 cancellation pulse delay, in samples. For real
cancellation pulses, CANCEL_DELAY = (CANCEL_LENGTH – 1) / 2. If minimum-phase cancellation pulses are
used, CANCEL_DELAY < (CANCEL_LENGTH – 1) / 2. The contents of the CANCEL_DELAY1 register are
applied to the GC115 hardware delay block only after a CANCEL_SYNC event occurs.
BITS
DESCRIPTION
[7:0]
Cancel pulse delay for PDC Stage 1 (a value from 5 to 255)
[15:8]
Reserved
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RESOURCE_CNT2
0x38 (56) Type: Read/Write Value at RESET: 0x0000
The RESOURCE_CNT2 register specifies how many canceler RAMs are associated with PDC Stage 2.
RESOURCE_CNT2 contains a value between 0 and 8. The sum of canceler RAMs in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 must be 8 or less. Resource allocations
become effective only after a RESOURCE_SYNC event occurs. The RESOURCE_SYNC register selects the
source of the RESOURCE_SYNC event.
BITS
DETECT_TSQD2
DESCRIPTION
[3:0]
Number of canceler RAMs assigned to PDC Stage 2 (from 0 to 8)
[15:4]
Reserved
0x39 (57)
Type: Read/Write Value at RESET: 0x0000
The DETECT_TSQD2 register contains the detection threshold-squared value for PDC Stage 2. The detection
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 2 whose magnitude is above DETECT_TSQD2 will be decreased to the
magnitude-squared value specified in GAIN_TSQD2, assuming that PDC Stage 2 has an available canceler.
BITS
[15:0]
GAIN_TSQD2
DESCRIPTION
Detection threshold-squared value for PDC Stage 2.
0x3A (58)
Type: Read/Write Value at RESET: 0x0000
The GAIN_TSQD2 register contains the gain threshold-squared value for PDC Stage 2. The gain
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 2 whose magnitude is above DETECT_TSQD2 will be decreased to the
magnitude-squared value specified in GAIN_TSQD2, assuming that PDC Stage 2 has an available canceler.
BITS
[15:0]
CANCEL_DELAY2
DESCRIPTION
Gain threshold-squared value for PDC Stage 2.
0x3B (59) Type: Read/Write
Value at RESET: 0x0000
The CANCEL_DELAY2 register contains the PDC Stage 2 cancellation pulse delay, in samples. For real
cancellation pulses, CANCEL_DELAY = (CANCEL_LENGTH – 1) / 2. If minimum-phase cancellation pulses are
used, CANCEL_DELAY < (CANCEL_LENGTH – 1) / 2. The contents of the CANCEL_DELAY2 register are
applied to the GC115 hardware delay block only after a CANCEL_SYNC event occurs.
BITS
52
DESCRIPTION
[7:0]
Cancel pulse delay for PDC Stage 2 (a value from 5 to 255)
[15:8]
Reserved
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RESOURCE_CNT3
0x40 (64)
Type: Read/Write Value at RESET: 0x0000
The RESOURCE_CNT3 register specifies how many canceler RAMs are associated with PDC Stage 3.
RESOURCE_CNT3 contains a value between 0 and 8. The sum of canceler RAMs in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 must be 8 or less. Resource allocations
become effective only after a RESOURCE_SYNC event occurs. The RESOURCE_SYNC register selects the
source of the RESOURCE_SYNC event.
BITS
DETECT_TSQD3
DESCRIPTION
[3:0]
Number of canceler RAMs assigned to PDC Stage 3 (from 0 to 8)
[15:4]
Reserved
0x41 (65)
Type: Read/Write
Value at RESET: 0X0000
The DETECT_TSQD3 register contains the detection threshold-squared value for PDC Stage 3. The detection
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 3 whose magnitude is above DETECT_TSQD3 will be decreased to the
magnitude-squared value specified in GAIN_TSQD3, assuming that PDC Stage 3 has an available canceler.
BITS
[15:0]
GAIN_TSQD3
DESCRIPTION
Detection threshold-squared value for PDC Stage 1.
0x42 (66)
Type: Read/Write
Value at RESET: 0X0000
The GAIN_TSQD3 register contains the gain threshold-squared value for PDC Stage 3. The gain
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 3 whose magnitude is above DETECT_TSQD3 will be decreased to the
magnitude-squared value specified in GAIN_TSQD3, assuming that PDC Stage 3 has an available canceler.
BITS
[15:0]
CANCEL_DELAY3
DESCRIPTION
Gain threshold-squared value for PDC Stage 3.
0x43 (67) Type: Read/Write
Value at RESET: 0X0000
The CANCEL_DELAY3 register contains the PDC Stage 3 cancellation pulse delay, in samples. For real
cancellation pulses, CANCEL_DELAY = (CANCEL_LENGTH – 1) / 2. If minimum-phase cancellation pulses are
used, CANCEL_DELAY < (CANCEL_LENGTH – 1) / 2. The contents of the CANCEL_DELAY3 register are
applied to the GC115 hardware delay block only after a CANCEL_SYNC event occurs.
BITS
DESCRIPTION
[7:0]
Cancel pulse delay for PDC Stage 3 (a value from 5 to 255)
[15:8]
Reserved
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RESOURCE_CNT4
0x48 (72) Type: Read/Write Value at RESET: 0x0000
The RESOURCE_CNT4 register specifies how many canceler RAMs are associated with PDC Stage 4.
RESOURCE_CNT1 contains a value between 0 and 8. The sum of canceler RAMs in RESOURCE_CNT1,
RESOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 must be 8 or less. Resource allocations
become effective only after a RESOURCE_SYNC event occurs. The RESOURCE_SYNC register selects the
source of the RESOURCE_SYNC event.
BITS
DETECT_TSQD4
DESCRIPTION
[3:0]
Number of canceler RAMs assigned to PDC Stage 4 (from 0 to 8)
[15:4]
Reserved
0x49 (73)
Type: Read/Write
Value at RESET: 0x0000
The DETECT_TSQD4 register contains the detection threshold-squared value for PDC Stage 4. The detection
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 4 whose magnitude is above DETECT_TSQD4 will be decreased to the
magnitude-squared value specified in GAIN_TSQD4, assuming that PDC Stage 4 has an available canceler.
BITS
[15:0]
GAIN_TSQD4
DESCRIPTION
Detection threshold-squared value for PDC Stage 4.
0x4A (74)
Type: Read/Write Value at RESET: 0x0000
The GAIN_TSQD4 register contains the gain threshold-squared value for PDC Stage 4. The gain
threshold-squared value is usually calculated from the average power (0 dB point) of the GC1115 input signal.
Interpolated peaks found by PDC Stage 4 whose magnitude is above DETECT_TSQD4 will be decreased to the
magnitude-squared value specified in GAIN_TSQD4, assuming that PDC Stage 4 has an available canceler.
BITS
[15:0]
CANCEL_DELAY4
DESCRIPTION
Gain threshold-squared value for PDC Stage 4.
0x4B (75)
Type: Read/Write
Value at RESET: 0x0000
The CANCEL_DELAY4 register contains the PDC Stage 4 cancellation pulse delay, in samples. For real
cancellation pulses, CANCEL_DELAY = (CANCEL_LENGTH – 1) / 2. If minimum-phase cancellation pulses are
used, CANCEL_DELAY < (CANCEL_LENGTH – 1) / 2. The contents of the CANCEL_DELAY4 register are
applied to the GC115 hardware delay block only after a CANCEL_SYNC event occurs.
BITS
54
DESCRIPTION
[7:0]
Cancel pulse delay for PDC Stage 4 (a value from 5 to 255)
[15:8]
Reserved
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Snapshot RAM Registers (Addresses 96 – 119)
SNAP_A_CONTROL 0x60 (96)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_A_CONTROL register controls the operation of Snapshot RAM A, including the selection of its data
source and the type of data being captured. When using Snapshot RAM A in histogram mode, the RAM must
first be cleared by writing a 0x0002 to SNAP_A_CONTROL. If the GC1115 is operating in two-channel mode,
Snapshot RAM A can monitor the samples of either Channel 0 or Channel 1. Snapshot RAM A will not begin a
capture or histogram until the SNAP_A_SYNC event occurs. SNAP_A_SYNC cannot be triggered by a periodic
TIMER event.
BITS
[1:0]
DESCRIPTION
Snapshot RAM A command:
00 – DISABLE (ignore all other bits in word)
01 – ENABLE (observe all other bits)
1x – CLEAR_RAM (ignore all other bits)
2
[5:3]
Two-channel data source:
0 = Channel 0
1 = Channel 1
Snapshot RAM A data source:
001: input
010: after Stage 1
011: after Stage 2
100: after Stage 3
101: after Stage 4
[7:6]
Snapshot RAM A operating mode: 00 = capture 1k samples
10 = histogram Q samples
01 = histogram I samples
11 = histo. mag2(I + jQ)
[15:8 Reserved
]
SNAP_A_STATUS
0x61 (97)
Type: Read only
Value at RESET: 0x0000
The SNAP_A_STATUS register can be read to determine the current status (state) of Snapshot RAM A. After
sending a 0x2 command (clear RAM) to SNAP_A_CONTROL, SNAP_A_STATUS can be polled to determine
when the RAM has been cleared. After a Snapshot RAM A capture completes, the microprocessor or DSP can
receive an interrupt by enabling bit 0 of INT_MASK. During histogram operation, if one or more Snapshot RAM
A histogram bins overflows its 32-bit count, bit 2 of INT_MAP will be set. If bit 2 of INT_MASK is set, a Snapshot
RAM A bin overflow will also generate an interrupt. Snapshot RAM A will not begin a capture or histogram until
the SNAP_A_SYNC event occurs. SNAP_A_SYNC cannot be triggered by a periodic TIMER event.
BITS
[2:0]
DESCRIPTION
Snapshot RAM A
status:
000 – OFF
001 – enabled (waiting)
010 – active (capturing) 011 – capture complete
100 – resetting (clearing all snapshot RAM bins)
[15:3]
Reserved
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SNAP_A_ADDRESS
0x62 (98)
Type: Read only
Value at RESET: 0x0000
The SNAP_A_ADDRESS register contains a pointer into Snapshot RAM A memory (2048 locations × 16 bits per
locations). SNAP_A_ADDRESS is written by the microprocessor or DSP. As when accessing cancellation
coefficient shadow RAM, SNAP_A_ADDRESS auto-increments after each SNAP_A_DATA register access (read
or write). In capture mode, Snapshot RAM A contains I samples at even addresses (0, 2, 4, …), and Q samples
at odd addresses (1, 3, 5, …). In histogram mode, Snapshot RAM A contains 32-bit counter entries, with the
upper 16 bits at even addresses (0, 2, 4, …) and the lower 16 bits at odd addresses (1, 3, 5, …).
BITS
DESCRIPTION
[10:0]
Snapshot RAM A address: 0 to 2047
In capture mode:
Snap_RAM_A[0] = sample_I(0) [16 MSBs of 18-bit I sample]
Snap_RAM_A[1] = sample_Q(0) [16 MSBs of 18-bit Q samp]
...
Snap_RAM_A[2046] = sample_I(1023) [16 MSBs of I sample]
Snap_RAM_A[2047] = sample_Q(1023) [16 MSBs of Q sample]
In histogram mode:
Snap_RAM_A[0] = hist_hi_word(0)
Snap_RAM_A[1] = hist_lo_word(0)
...
Snap_RAM_A[2046] = hist_hi_word(1023)
Snap_RAM_A[2047] = hist_lo_word(1023)
[15:11]
SNAP_A_DATA
Reserved
0x63 (99)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_A_DATA register allows access to the Snapshot RAM A memory location addressed by
SNAP_A_ADDRESS. Snapshot RAM A contains 2048 × 16-bit values, whose organization is described with
SNAP_A_ADDRESS. After SNAP_A_DATA is read or written, the value in SNAP_A_ADDRESS is
auto-incremented.
BITS
[15:0]
SNAP_A_MINVAL
DESCRIPTION
Snapshot RAM A data
0x64 (100)
Type: Read/Write Value at RESET: 0x0000
The SNAP_A_MINVAL register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed. The minimum value of
interest is SNAP_A_MINVAL, while the maximum value of interest is SNAP_A_MAXVAL. Input values SNAP_A_MINVAL will be counted in Snapshot RAM A’s histogram bin 0. Input values SNAP_A_MAXVAL will
be counted in Snapshot RAM A’s histogram bin 1023.
BITS
[15:0]
56
DESCRIPTION
Snapshot RAM A (in histogram mode): minimum allowable value
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SNAP_A_MAXVAL
0x65 (101) Type: Read/Write Value at RESET: 0x0000
The SNAP_A_MAXVAL register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed. The minimum value of
interest is SNAP_A_MINVAL, while the maximum value of interest is SNAP_A_MAXVAL. Input values ≤
SNAP_A_MINVAL will be counted in Snapshot RAM A’s histogram bin 0. Input values ≥ SNAP_A_MAXVAL will
be counted in Snapshot RAM A’s histogram bin 1023.
BITS
DESCRIPTION
[15:0]
SNAP_A_SCALE
Snapshot RAM A (in histogram mode): maximum allowable value
0x66 (102) Type: Read/Write
Value at RESET: 0x0000
The SNAP_A_SCALE register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed, using SNAP_A_MINVAL and
SNAP_A_MAXVAL. However, the difference between SNAP_A_MAXVAL and SNAP_A_MINVAL can be larger
than the number of histogram bins (1024). SNAP_A_SCALE is used to scale the difference between the input
value (to be histogrammed) and SNAP_A_MINVAL into the allowed 10-bit histogram index range (0..1023). The
GC1115 user is responsible for ensuring that SNAP_A_SCALE limits histogram indices to the range 0..1023.
SNAP_A_SCALE is interpreted as an unsigned 14-bit fractional value, from 0x0000 = 0.0 to 0x3FFF = 1.0.
BITS
DESCRIPTION
[13:0]
Snapshot RAM A (in histogram mode): maximum allowable value
[15:14]
Reserved
Histogram index calculation:
if ( (sample[i] >= SNAP_MINVAL) && (sample[i] <= SNAP_MAXVAL) ) {
j = sample[i] - SNAP_MINVAL;
index = int(j * SNAP_SCALE);
hist[index]++
}
The GC1115 user is responsible for ensuring that index (the product of j × SNAP_SCALE) is in the allowed
range of 0..1023.
SNAP_A_HISTCOUNT
0x67 (103)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_A_HISTCOUNT register determines how many groups of samples will be observed in histogram
mode. SNAP_A_HISTCOUNT is used only during Snapshot RAM A histogram mode operation.
SNAP_A_HISTCOUNT works in conjunction with POWER_CNT (0x7F). The number of samples in a group is
specified in POWER_CNT, while the number of groups monitored during histogram mode is specified in
SNAP_A_HISTCOUNT. Thus the total number of samples observed in histogram mode is POWER_CNT ×
SNAP_A_HISTCOUNT. At reset, POWER_CNT = 0xFFFF, or 65535.
BITS
[15:0]
DESCRIPTION
Number of POWER_CNT sample groups to be histogrammed.
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SNAP_B_CONTROL
0x70 (112)
Type: Read/Write Value at RESET: 0x0000
The SNAP_B_CONTROL register controls the operation of Snapshot RAM A, including the selection of its data
source and the type of data being captured. When using Snapshot RAM A in histogram mode, the RAM must
first be cleared by writing a 0x0002 to SNAP_B_CONTROL. If the GC1115 is operating in two-channel mode,
Snapshot RAM A can monitor the samples of either Channel 0 or Channel 1. Snapshot RAM A will not begin a
capture or histogram until the SNAP_B_SYNC event occurs. SNAP_B_SYNC cannot be triggered by a periodic
TIMER event.
BITS
[1:0]
DESCRIPTION
Snapshot RAM A command:
00 – DISABLE (ignore all other bits in word)
01 – ENABLE (observe all other bits)
1x – CLEAR_RAM (ignore all other bits)
2
Channel-channel data source:
0 = Channel 0
1 = Channel 1
[5:3]
Snapshot RAM A data source:
001: input
010: after Stage 1
011: after Stage 2
100: after Stage 3
101: after Stage 4
[7:6]
Snapshot RAM A operating mode:
00 = capture 1k samples
01 = histogram I samples
10 = histogram Q samples
11 = histo. mag2(I + jQ)
[15:8] Reserved
SNAP_B_STATUS
0x71 (113) Type: Read only
Value at RESET: 0x0000
The SNAP_B_STATUS register can be read to determine the current status (state) of Snapshot RAM A. After
sending a 0x2 command (clear RAM) to SNAP_B_CONTROL, SNAP_B_STATUS can be polled to determine
when the RAM has been cleared. After a Snapshot RAM A capture completes, the microprocessor or DSP can
receive an interrupt by enabling bit 0 of INT_MASK. During histogram operation, if one or more Snapshot RAM
A histogram bins overflows its 32-bit count, bit 2 of INT_MAP will be set. If bit 2 of INT_MASK is set, a Snapshot
RAM A bin overflow will also generate an interrupt. Snapshot RAM A will not begin a capture or histogram until
the SNAP_B_SYNC event occurs. SNAP_B_SYNC cannot be triggered by a periodic TIMER event.
BITS
[2:0]
DESCRIPTION
Snapshot RAM A
status:
000 – OFF
001 – enabled (waiting)
010 – active (capturing)
011 – capture complete
100 – resetting (clearing all snapshot RAM bins)
[15:3]
58
Reserved
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SNAP_B_ADDRESS
0x72 (114)
Type: Read only
BITS
Value at RESET: 0x0000
DESCRIPTION
[10:0]
Snapshot RAM A address: 0 to 2047
In capture mode:
Snap_RAM_A[0] = sample_I(0) [16 MSBs of 18-bit I sample]
Snap_RAM_A[1] = sample_Q(0) [16 MSBs of 18-bit Q samp]
...
Snap_RAM_A[2046] = sample_I(1023) [16 MSBs of I sample]
Snap_RAM_A[2047] = sample_Q(1023) [16 MSBs of Q sample]
In histogram mode:
Snap_RAM_A[0] = hist_hi_word(0)
Snap_RAM_A[1] = hist_lo_word(0)
...
Snap_RAM_A[2046] = hist_hi_word(1023)
Snap_RAM_A[2047] = hist_lo_word(1023)
[15:11]
SNAP_B_DATA
Reserved
0x73 (115) Type:
Read/Write
Value at RESET: 0x0000
The SNAP_B_DATA register allows access to the Snapshot RAM A memory location addressed by
SNAP_B_ADDRESS. Snapshot RAM A contains 2048 × 16-bit values, whose organization is described in the
discussion of SNAP_B_ADDRESS. After SNAP_B_DATA is read or written, the value in SNAP_B_ADDRESS is
auto-incremented.
BITS
[15:0]
SNAP_B_MINVAL
DESCRIPTION
Snapshot RAM A data
0x74 (116)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_B_MINVAL register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed. The minimum value of
interest is SNAP_B_MINVAL, while the maximum value of interest is SNAP_B_MAXVAL. Input values ≤
SNAP_B_MINVAL will be counted in Snapshot RAM A’s histogram bin 0. Input values ≥ SNAP_B_MAXVAL will
be counted in Snapshot RAM A’s histogram bin 1023.
BITS
[15:0]
DESCRIPTION
Snapshot RAM A (in histogram mode): minimum allowable value
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SNAP_B_MAXVAL
0x75 (117)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_B_MAXVAL register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed. The minimum value of
interest is SNAP_B_MINVAL, while the maximum value of interest is SNAP_B_MAXVAL. Input values SNAP_B_MINVAL will be counted in Snapshot RAM A’s histogram bin 0. Input values SNAP_B_MAXVAL will
be counted in Snapshot RAM A’s histogram bin 1023.
BITS
DESCRIPTION
[15:0]
SNAP_B_SCALE
Snapshot RAM A (in histogram mode): maximum allowable value
0x76 (118) Type: Read/Write
Value at RESET: 0x0000
The SNAP_B_SCALE register is used only during Snapshot RAM A histogram mode. In histogram mode, the
microprocessor or DSP can specify a desired range of values to be histogrammed, using SNAP_B_MINVAL and
SNAP_B_MAXVAL. However, the difference between SNAP_B_MAXVAL and SNAP_B_MINVAL can be larger
than the number of histogram bins (1024). SNAP_B_SCALE is used to scale the difference between the input
value (to be histogrammed) and SNAP_B_MINVAL into the allowed 10-bit histogram index range (0..1023). The
GC1115 user is responsible for ensuring that SNAP_B_SCALE limits histogram indices to the range 0..1023.
SNAP_B_SCALE is interpreted as an unsigned 14-bit fractional value, from 0x0000 = 0.0 to 0x3FFF = 1.0.
BITS
DESCRIPTION
[13:0]
Snapshot RAM A (in histogram mode): maximum allowable value
[15:14]
Reserved
Histogram index calculation:
if ( (sample[i] >= SNAP_MINVAL) && (sample[i] <= SNAP_MAXVAL) ) {
j = sample[i] - SNAP_MINVAL;
index = int(j * SNAP_SCALE);
hist[index]++
}
The GC1115 user is responsible for ensuring that index (the product of j × SNAP_SCALE) is in the allowed
range of 0..1023.
SNAP_B_HISTCOUNT
0x77 (119)
Type: Read/Write
Value at RESET: 0x0000
The SNAP_B_HISTCOUNT register determines how many groups of samples will be observed in histogram
mode. SNAP_B_HISTCOUNT is used only during Snapshot RAM A histogram mode operation.
SNAP_B_HISTCOUNT works in conjunction with POWER_CNT (0x7F). The number of samples in a group is
specified in POWER_CNT, while the number of groups monitored during histogram mode is specified in
SNAP_B_HISTCOUNT. Thus the total number of samples observed in histogram mode is POWER_CNT *
SNAP_B_HISTCOUNT. At reset, POWER_CNT = 0xFFFF, or 65535.
BITS
[15:0]
60
DESCRIPTION
Number of POWER_CNT sample groups to be histogrammed.
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POWER_CNT
0x7F (127)
Type: Read/Write
Value at RESET: 0xFFFF
The POWER_CNT register determines how many samples are used in each group during power measurement
and during Snapshot RAM operation. During power measurement, the total number of samples observed for
power measurement is POWER_CNT × POWER_CTL[13:0]. During Snapshot RAM histogram operation, the
total number of samples observed for the histogram is POWER_CNT × SNAP_HISTCOUNT. At GC1115 reset,
POWER_CNT = 0xFFFF (65535).
BITS
[15:0]
DESCRIPTION
Number of samples in a power measurement or histogram group (0 to 65535)
Interpolate-by-4 Registers (Addresses 128 – 169)
INTERP_CTL
0x80 (128)
Type: Read/Write
Value at RESET: 0x0000
BITS
[1:0]
DESCRIPTION
Interpolator
operation:
00: Interp by 2, complex output
01: Interp by 2, fs/4 enabled, real output
1x: Interp by 4, fs/4 enabled, real output
[15:2]
Reserved
NOTE:
To bypass the interp-by-4 stage, clear bit 4 of the CONTROL register, set 0x82 to
0x8000, and clear 0x83 to 0xA9.
INTERP_COEFS
0x82 – 0xA9
(130 – 169)
Type:
Read/Write
Value at RESET: 0x8000 (0x82), 0x0000 (0x83 – 0xA9)
Addresses 0x82 to 0xA9 store the interpolation stage’s 40 interpolation coefficients. These coefficients are
accessed even if the interpolation stage is bypassed, i.e. even when bit 4 of CONTROL (0x2) is cleared.
GC1115 users must therefore ALWAYS initialize the interpolation coefficients. After RESET, the interpolation
coefficients are initialized for bypass operation (value at address 0x82 = 0x8000; all other interpolation
coefficients = 0). The earlier section entitled Interpolate-by-4 Operation described the required interp-by-4
coefficients during interpolation.
BITS
[15:0]
DESCRIPTION
Signed, 16-bit interp-by-4 coefficient, from –32768 to +32767
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Soft Limiter Block (Addresses 192 – 248)
NOTE:
The Soft Limiter block can safely be bypassed under almost all operating conditions.
The Soft Limiter is only required when very low PAR levels (≤ 5 dB output PAR)
cause PDC canceler resources to be overwhelmed. At these low PAR levels, the
cEVM and PCDE specifications already cannot be met, and the soft limiter will
probably make the ACLR worse.
SOFT_LENGTH
0xC0 (192)
Type: Read/Write
Value at RESET: 0x0000
The SOFT_LENGTH register controls the operation of the GC1115’s soft limiter. In addition to providing a final
limiter after the interpolation stage, the soft limiter also contains I and Q gain and offset values that can
compensate for gain and offset imbalances in I/Q modulators that follow the GC1115. The soft limiter is
bypassed by clearing bit 5 of the CONTROL register.
When SOFT_LENGTH[1:0] = 01, taper table uses SOFT_COEF0 to SOFT_COEF3
When SOFT_LENGTH[1:0] = 10, taper table uses SOFT_COEF0 to SOFT_COEF7
When SOFT_LENGTH[1:0] = 11, taper table uses SOFT_COEF0 to SOFT_COEF15
Because the I/Q gain and I/Q offset registers are always in the GC1115 datapath (even when the soft limiter is
bypassed), GC1115 users must initialize the gain and offset register appropriately.
The default OUT_GAIN0 and OUT_GAIN1 values are 0, so the GC1115 will output zeros at RESET. In order to
generate non-zero GC1115 output values, OUT_GAIN0 and OUT_GAIN1 must be set to non-zero values
(preferably 0x2000, which equates to 1.0). OUT_GAIN0 and OUT_GAIN1 must be written by the
microprocessor or DSP, or the OUT_A and OUT_B ports will always output zeros.
The default I and Q offset is 0 (i.e. I and Q samples are not offset at RESET).
BITS
[1:0]
DESCRIPTION
Number of samples in the soft
limiting interval:
01: 9-sample soft limit length (4 coefs)
10: 17-sample soft limit length (8 coefs)
11: 33-sample soft limit length (16 coefs)
The middle soft limiter coefficient is always an implied “1”
[15:2]
SOFT_TSQD
Reserved
0xC1 (193)
Type: Read/Write
Value at RESET: 0xFFFF
The SOFT_TSQD register contains the soft limiter’s threshold-squared value. This threshold-squared value is
scaled identically to the DETECT_TSQD and GAIN_TSQD PDC Stage thresholds. Note that the default
SOFT_TSQD value is 0xFFFF, ensuring that the soft limiter’s threshold is set to its maximum value at RESET.
BITS
[15:0]
62
DESCRIPTION
Soft limiter threshold-squared value
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SOFT_COEF0..15
0xC2 – 0xD1 (194 – 209) Type: Read/Write
Value at RESET: 0x0000
The sixteen SOFT_COEF registers hold the soft limiter’s taper table. The taper table contains 4, 8, or 16
normalized coefficients, whose values are scaled by a variable that is proportional to the size of the detected,
over-threshold soft limiter peak. SOFT_COEF0 at address 0xC2 is the smallest coefficient, while SOFT_COEFn
(n=3, 7, or 15) is the largest coefficient (near to a normalized value of 1.0). The soft limiter uses an internal,
normalized value of 1.0 at SOFT_COEFm (m = 4, 8, or 16) that is NOT stored in the SOFT_COEF taper table.
The taper table’s values are applied to the N samples before the detected peak, and again to the N samples
after the detected peak (N = 4, 8, or 16). Please refer to the section of this document entitled Soft Limiter
Operation for a detailed description of the soft limiter taper table.
When SOFT_LENGTH[1:0] = 01, taper table uses SOFT_COEF0 to SOFT_COEF3
When SOFT_LENGTH[1:0] = 10, taper table uses SOFT_COEF0 to SOFT_COEF7
When SOFT_LENGTH[1:0] = 11, taper table uses SOFT_COEF0 to SOFT_COEF15
BITS
[15:0]
SOFT_TAB_SCALE
DESCRIPTION
Soft limiter taper table coefficient (unsigned, 16-bit value)
0xD2 (210) Type: Read/Write
Value at RESET: 0xFFFF
The SOFT_TAB_SCALE register contains the soft limiter’s lookup table scale factor. For a desired shift value of
N bits, SOFT_TAB_SCALE should be set to N – 17. The valid range for SOFT_TAB_SCALE is 0 to 15, encoded
in the 4 LSBs.
BITS
DESCRIPTION
[3:0]
Soft limiter lookup table scale factor (# bits to shift, 0 to 15)
[15:4]
Reserved
SOFT_INVGAIN0..31 0xD3 – 0xF2 (211 – 242)
Type: Read/Write
Value at RESET: 0x000
The thirty-two SOFT_INVGAIN registers hold the soft limiter’s inverse gain lookup table. The taper table contains
31 inverse gain values between 1.0 and g, where g is the maximum expected over-threshold value. For
example, if the soft limiter expects to see a peak after PDC Stage 4 that is at most 50% higher than the
SOFT_TSQD threshold, g would be set to 1.5. SOFT_INVGAIN0 (0xD3) contains the smallest inverse gain
value. SOFT_INVGAIN31 contains the largest inverse gain value. Please refer to the section of this document
entitled Soft Limiter Operation for a detailed description of the inverse gain lookup table.
BITS
[15:0]
DESCRIPTION
Soft limiter inverse gain lookup coefficient (unsigned, 16-bit value)
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OUT_GAIN0
0xF3 (243)
Type: Read/Write
Value at RESET: 0x0000
The OUT_GAIN0 register contains the OUT_A output gain. Under normal circumstances, the microprocessor or
DSP should initialize OUT_GAIN0 to 0x2000, which corresponds to a normalized gain of 1.0. OUT_GAIN0 can
provide up to two bits of boost: an OUT_GAIN0 value of 0x3FFF corresponds to a normalized gain of 3.999939.
OUT_GAIN0 is a signed value, so negative OUT_GAIN0 values are permitted. Users should be aware that a
negative OUT_GAIN0 value would cause a 180-degree phase inversion of the OUT_A output signal.
The default OUT_GAIN0 value is 0, so the GC1115 will output zeros at RESET. In order to generate non-zero
GC1115 output values, OUT_GAIN0 and OUT_GAIN1 must be set to non-zero values (preferably 0x2000,
which equates to 1.0). OUT_GAIN0 and OUT_GAIN1 must be written by the microprocessor or DSP, or
the OUT_A and OUT_B will always output zeros.
BITS
DESCRIPTION
[14:0]
Output Port A gain (2 MSBs are
GAIN bits):
0x7FFF = gain of
3.999939
0x4000 = gain of 2.0
0x2000 = gain of 1.0
0x1FFF = gain of 0.999893
0x0000 = gain of 0.0 (zeros are output)
15
OUT_GAIN1
Output gain sign bit:
0xF4 (244)
0 = positive gain
Type: Read/Write
1 = negative gain
Value at RESET: 0x0000
The OUT_GAIN1 register contains the OUT_B output gain. Under normal circumstances, the microprocessor or
DSP should initialize OUT_GAIN1 to 0x2000, which corresponds to a normalized gain of 1.0. OUT_GAIN1 can
provide up to two bits of boost; an OUT_GAIN1 value of 0x3FFF corresponds to a normalized gain of 3.999939.
OUT_GAIN1 is a signed value, so negative OUT_GAIN1 values are permitted. Users should be aware that a
negative OUT_GAIN1 value would cause a 180-degree phase inversion of the OUT_B output signal.
The default OUT_GAIN1 value is 0, so the GC1115 will output zeros at RESET. In order to generate non-zero
GC1115 output values, OUT_GAIN0 and OUT_GAIN1 must be set to non-zero values (preferably 0x2000,
which equates to 1.0). OUT_GAIN0 and OUT_GAIN1 must be written by the microprocessor or DSP, or
the OUT_A and OUT_B will always output zeros.
BITS
DESCRIPTION
[14:0]
Output Port B gain (2 MSBs are
GAIN bits):
0x7FFF = gain of
3.999939
0x4000 = gain of 2.0
0x2000 = gain of 1.0
0x1FFF = gain of 0.999893
0x0000 = gain of 0.0 (zeros are output)
15
OUT_OFFSET_I0
Output gain sign bit:
0xF5 (245)
0 = positive gain
1 = negative gain
Type: Read/Write Value at RESET: 0x0000
The OUT_OFFSET_I0 register contains the OUT_A offset value for the I0 channel. In one-channel operation, I0
is the I-channel offset. OUT_OFFSET register values are signed, 16-bit values that are aligned with the 16
MSBs of the 18-bit signed I-channel sample. OUT_OFFSET_I0 is also the Channel 0 offset applied to the real
output samples in real-output modes (i.e. when the interpolate block is generating 2x real or 4x real samples).
BITS
[15:0]
64
DESCRIPTION
Channel 0, I leg DC offset (also the Channel 0 real offset in real output mode)
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OUT_OFFSET_Q0
0xF6 (246)
Type: Read/Write
Value at RESET: 0x0000
The OUT_OFFSET_Q0 register contains the OUT_A offset value for the Q0 channel. In one-channel operation,
Q0 is the Q-channel offset. OUT_OFFSET register values are signed, 16-bit values that are aligned with the 16
MSBs of the 18-bit signed Q-channel sample.
BITS
[15:0]
OUT_OFFSET_I1
DESCRIPTION
Channel 0, Q leg DC offset
0xF7 (247)
Type: Read/Write Value at RESET: 0x0000
The OUT_OFFSET_I1 register contains the OUT_B I-offset value for the second channel during two-channel
operation. OUT_OFFSET register values are signed, 16-bit values that are aligned with the 16 MSBs of the
18-bit signed I-channel sample. OUT_OFFSET_I1 is also the Channel 1 offset applied to the real output
samples in real-output modes (i.e. when the interpolate block is generating 2x real or 4x real samples).
BITS
[15:0]
OUT_OFFSET_Q1
DESCRIPTION
Channel 1, I leg DC offset (also the Channel 1 real offset in real output mode)
0xF8 (248)
Type: Read/Write
Value at RESET: 0x0000
The OUT_OFFSET_Q1 register contains the OUT_B Q-offset value for the second channel during two-channel
operation. OUT_OFFSET register values are signed, 16-bit values that are aligned with the 16 MSBs of the
18-bit signed Q-channel sample.
BITS
[15:0]
DESCRIPTION
Channel 1, Q leg DC offset
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GC1115 Power Consumption
While GC1115 power consumption varies, depending on the number of input channels, the IN_CLK frequency,
the output PAR level, etc., the following GC1115 power consumption values were measured at room
temperature and nominal voltage conditions using a 4-carrier W-CDMA Test Model 3 input signal, output PAR =
6 dB, 4 PDC stages, cancel pulse length 127.
Table 17. GC1115 Power Consumption
GC1115 CONDITIONS
DECIMATION
POWER
30.72 Msamp/sec
2
1.1 W
61.44 Msamp/sec
1
1.6 W
40.00 Msamp/sec
2
1.5 W
80.00 Msamp/sec
1
2.0 W
120.0 Msamp/sec
2
2.1 W
30.72 Msamp/sec
1
1.8 W
40.00 Msamp/sec
1
2.3 W
61.44 Msamp/sec
2
2.5 W
One-channel operation
Two-channel operation
Factors Affecting GC1115 Power Consumption
• GC1115 IN_CLK frequency linearly affects power consumption: the higher the GC1115 IN_CLK rate, the
higher the power consumption.
• For higher (less demanding) output PAR levels, GC1115 users may consider disabling PDC stages 3 and 4,
which reduces power consumption by as much as 30%.
• GC1115 power consumption can be decreased by simultaneously enabling 2× decimation of the input signal
and 2× interpolation of the output signal. With the 2× decimate/2× interp enabled, the GC1115 input and
output rates are equivalent, but the PDC stages operate at half speed, decreasing power consumption by as
much as 30%. However, users considering this option should determine whether the decrease (usually
small) in composite EVM and peak code domain error due to this 2× decimate/2× interpolate process is
acceptable.
• Power consumption increases with decreasing output PAR levels - as more peaks are cancelled, power
consumption increases. This effect is small.
• Power consumption increases with cancel pulse length - the longer the cancel pulse, the higher the power
consumption. This effect is small.
Latency
The latency (in samples) through the GC1115 is determined by the number of PDC stages enabled and by the
CANCEL_DELAY value for a given cancel pulse. All PDC stages normally use the same CANCEL_DELAY
value. Given these two paramenters, the sample latency through the GC1115 (in samples) is calculated as
follows:
Latency = ((# of PDC stages disabled × 1.5) + (# of PDC stages enabled × (CANCEL_DELAY + 47.5)) + 16.5)
A fractional sample latency should be increased to the next-larger integer.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VDD
Core supply voltage range
-0.3 V to 1.32 V
VDD1
PLL digital supply voltage range
-0.3 V to 1.32 V
VDDA1,2
PLL analog supply voltage range
-0.3 V to 1.32 V
VDDSHV
Input supply voltage range
VIN
Input voltage range
TJmax
Maximum junction temperature
TC
Operating case temperature
–40°C to +85°C
Tstg
Storage temperature
–55°C to 150°C
(1)
-0.3 V to 3.6 V
-0.3 V to VDDSHV + 0.3 V
105°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
Supply voltage, VSS
MAX
UNIT
0
V
Core supply votlage, VDD
1.14
1.2
1.26
V
PLL digital supply voltage, VDD1
1.08
1.2
1.32
V
PLL analog supply voltage, VDDA1,2
1.14
1.2
1.26
V
I/O supply voltage, VDDSHV
3.0
3.3
3.6
V
Input voltage range, VIN
3.0
3.3
VDDSHV
+ 0.3
V
Power consumption
Operating case temperature, TC
-45
25
Maximum junction temperature, TJmax
(1)
3.3 (1)
W
85
°C
105
°C
Two-channel operation, IN_CLK = 80 MHz, decimate by 2, interpolate by 2.
PACKAGE THERMAL RESISTANCE CHARACTERISTICS (1) (2)
PACKAGE
AIRFLOW (m/sec)
θJA (°C/W)
θJB (°C/W)
θJC (°C/W)
0
18.3
10.0
5.9
1
16.2
10.0
5.9
2.5
15.3
10.0
5.9
IZDJ
(1)
(2)
Simulations based on 1S2P board type as defined by JEDEC, tested at 85°C ambient temperature. Reference JEDEC Standard
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements.
Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GC1115IZDJ
package:
•
An array of 36 land pads must be added on the top layer of the PCB where the package will be mounted.
•
The PCB land pads should be the same diameter as the vias in the package substrate for optimal board level reliability temperature
cycle performance.
•
The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be
connected to the ground plane for heat dissipation.
•
A solid internal plane is preferred for spreading the heat.
SWITCHING CHARACTERISTICS
PARAMETER
MIN
MAX
UNIT
JTAG:
tperiod
JTAG clock period 14 ns
14
ns
tjt_ckh
tjt_su
JTAG clock high time tjt_ckl JTAG clock low time
5
ns
JTAG input (TDI or TMS) setup time before TCK goes high
1
ns
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SWITCHING CHARACTERISTICS (continued)
PARAMETER
MIN
MAX
UNIT
JTAG:
tjt_hd
JTAG input (TDI or TMS) hold time after TCK goes high
4
ns
tjt_dly
JTAG output (TDO) delay from falling edge of TCK
4
ns
tjt_oh
JTAG output (TDO) hold time from falling edge of TCK
1
ns
FUNC DATAPATH:
tin_duty_cycle
tperiod
tin_ckh
Clock duty cycle
43.75%
1:4x (1)
Clock period
1:2, 1:x (1)
Clock high time
56.25%
12.5
ns
7.7
ns
1:4x (1)
5.47
7.03
ns
1:2, 1:x (1)
3.37
4.33
ns
1:4x (2)
5.47
7.03
ns
1:2, 1:x (2)
3.37
4.33
ns
tin_ckl
Clock low time
tin_su
Input setup before clock goes high
0.5
ns
tin_hd
Input hold time after clock goes high
1.0
ns
tout_dly
Output delay from rising edge of clock
2.4
tout_hd
Output hold time from rising edge of clock
ns
0.2
ns
MPUREG 2 WIRE MODE:
tup_cenh
CE_N high time
4
ns
tup_cenl
CE_N low time
7
ns
tup_a_su
Address setup time before read or write
6
ns
tup_a_hd
Address hold time after read or write
3
ns
tup_rc_su
Control setup time before read
6
ns
tup_wc_su
Control setup time before write
2
ns
tup_rc_hd
Control hold after read
0
ns
tup_wc_hd
Control hold after write
2
ns
tup_wd_su
Control data setup before read or write
2
ns
tup_wd_hd
Control data hold after read or write
3
tup_dly
Control ouput delay CE low and A stable to C(read operation)
ns
6.5
ns
MUPRAM 2 WIRE MODE:
tup_cenh
CE_N high time
tup_cenl (3)
3
ns
CE_N low time
tup_a_su
Address setup time before read or write
2 × tcore
ns
7
tup_a_hd
Address hold time after read or write
ns
3.5
ns
tup_rc_su
tup_wc_su
Control setup time before read
7
ns
Control setup time before write
4
ns
tup_rc_hd
Control hold after read
0
ns
tup_wc_hd
Control hold after write
0
ns
tup_wd_su
Control data setup before read or write
2
ns
tup_wd_hd
Control data hold after read or write
tup_dly (3)
Control output delay CE low and A stable to C(read operation)
(1)
(2)
(3)
68
3.5
ns
2 × tcore
ns
These are for different clocking modes. One clocking mode is identified as (1:4:x) and means the internal clock is 4x the chip's input
clock (IN_CLK) and the transmit clock can be 1x, 2x or 4x IN_CLK's rate. The second clocking mode is (1:2,1:x) and means the internal
clock is 2x or 1x the chip's input clock (IN_CLK) and the transmit clock can be 1x (or 2x if the core clock is 2x) IN_CLK's rate.
These are for different clocking modes. One clocking mode is identified as (1:4:x) and means the internal clock is 4x the chip's input
clock (IN_CLK) and the transmit clock can be 1x, 2x or 4x IN_CLK's rate. The second clocking mode is (1:2,1:x) and means the internal
clock is 2x or 1x the chip's input clock (IN_CLK) and the transmit clock can be 1x (or 2x if the core clock is 2x) IN_CLK's rate.
tup_cenl and tup_dly are a function of tcore, the GC1115 internal clock period. tcore's relationship to IN_CLK is determined by the core
PLL setup (options are 1x, 2x, and 4x multiples of the IN_CLK rate). Under normal operating conditions, the core PLL is set to 4 x
IN_CLK. Under these conditions, the duration of tcore is 1/4 of IN_CLK.
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TIMING PARAMETER INFORMATION
Control Timing for Edge With Single Strobe (2-Wire Mode)
tup_cenl
CE_N
tup_cenh
WR_N
tup_a_su
A[7:0]
tup_dly
C[15:0]
Figure 13. Read Cycle –RD Held Low
tup_cenl
CE_N
tup_cenh
tup_wc_su
WR_N
tup_wc_hd
tup_a_su
A[7:0]
tup_a_hd
tup_wd_su
C[15:0]
tup_wd_hd
Figure 14. Write Cycle –RD Held Low
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CK
tin_su
tin_hd
IN
tout_hd
tout_dly
OUT
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇ
Figure 15. Generic Data Setup and Hold. Data Output Hold and Delay
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DEVICE INFORMATION
ZDJ Package (Bottom View)
1
2
T
VSS
VSS
R
VSS
VSS
3
4
5
6
7
8
9
10
15
16
OUT_A12OUT_A15 OUT_IQ_
OUT_B1 OUT_B3 OUT_B5 OUT_B6 OUT_B8 OUT_B11OUT_B14OUT_B17 SYNC_B
SEL
VSS
VSS
T
OUT_A11OUT_A14OUT_A17 OUT_B0 OUT_B2 OUT_B4 OUT_B7 OUT_B10OUT_B13OUT_B15 SYNC_ SYNC_A
OUT
VSS
VSS
R
13
14
VSS
IN_B17
IN_B15
P
VDD
VSS
VDD
IN_B13
IN_B12
N
VDD
VSS
VDD
IN_B9
M
VSS
VSS
VDD
VDDSHV IN_B16
IN_B8
IN_B7
L
VSS
VSS
VSS
VDD
VDDSHV IN_B14
IN_B6
IN_B5
K
VSS
VSS
VSS
VSS
VDD
VDDSHV IN_B11
IN_B4
IN_B3
J
VSS
VSS
VSS
VSS
VDD
VDDSHV
IN_B0
IN_B2
IN_B1
H
OUT_A9 OUT_A10
VSS
VDD
N
OUT_A6 OUT_A8
VDD
VSS
VDD
M
OUT_A3 OUT_A5 VDDSHV
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VSS
VSS
OUT_A0 OUT_A1 OUT_A7 VDDSHV
12
VDD
P
L
11
VDDSHV OUT_A13OUT_A16 LOOP
OUT_B9 OUT_B12OUT_B16VDDSHV
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
VDDSHV IN_B10
K
D0
J
D2
D1
H
D3
D4
D7
VDDSHV
VDD
VSS
VSS
G
D5
D6
D9
VDDSHV
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDSHV IN_A14
IN_A16
IN_A17
G
F
D8
D10
D13
VDDSHV
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDSHV IN_A11
IN_A13
IN_A15
F
E
D11
D12
VDDSHV
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VDD
VDDSHV IN_A10
IN_A12
E
D
D14
D15
VDD
VSS
VDD
VDD
VSS
VDD
IN_A8
IN_A9
D
C
A1
A0
VSS
VDD
VDDSHV
A2
A6
TCK
IN_A3
VDDA2
VSS1
IN_CLK
VDD
VSS
VSSA1
VDDA1
C
B
VSS
VSS
A3
A5
A7
RD
TEST_
MODE
TRST
TMS
IN_A2
IN_A5
IN_A7
RESET
VDD1
VSS
VSS
B
INT
WR
CS
TDO
TDI
4
5
A
OUT_CLK OUT_A4 VDDSHV
OUT_A2 VDDSHV
VSS
VSS
A4
1
2
3
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
6
7
8
IN_A0
9
IN_A1
VPP
IN_A4
IN_A6
10
11
12
13
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14
VSS
VSS
15
16
A
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (Alphabetical Listing)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
A[7:0]
B5, C7, B4, A3, B3,
C6, C1, C2
I
Address Bus – Active high inputs
CS
A6
I
CHIP SELECT – Active low chip select
D[15:0]
D2, D1, F3, E2, E1,
F2, G3, F1, H3, G2,
G1, H2, H1, J1, J2,
K1
IN_A[17:0]
G16, G15, F16,
G14, F15, E16, F14,
E15, D16, D15, B12,
A13, B11, A12, C9,
B10, A10, A9
I
Input Port A, bits 17 (MSB) through 0 (LSB). IN_A carries I samps in parallel input mode; I/Q
samps in muxed one-channel input mode
IN_B[17:0]
P15, L14, P16, K14,
N15, N16, J14, M15,
M16, L15, L16, K15,
K16, J15, J16, H15,
H16, H14
I
Input Port B, bits 17 (MSB) through 0 (LSB) IN_B carries Q samples in parallel mode; I/Q
samples of second channel in 2-chan mode
IN_CLK
C12
I
Input data clock (drives the PLL that generates CHIP_CLK)
INT
A4
O
INTERRUPT – Active low output
LOOP
P8
O
Output pad for Tx PLL loop-back (MUST BE UNCONNECTED – NO LOAD!!)
OUT_A[17:0]
R5, P7, T4, R4, P6,
T3, R3, P2, P1, N2,
L3, N1, M2, K3, M1,
J3, L2, L1
O
Output Port A, bits 17 (MSB) through 0 (LSB)
OUT_A carries I samps in parallel output mode; I/Q samps in muxed 1-chan output mode
OUT_B[17:0]
T13, P11, R12, T12,
R11, P10, T11, R10,
P9, T10, R9, T9, T8,
R8, T7, R7, T6, R6
O
Output Port B, bits 17 (MSB) through 0 (LSB)
OUT_B carries Q samples in parallel mode; I/Q samples of second channel in 2-channel
mode
OUT_CLK
K2
O
Output data clock (do NOT use to drive other parts – for test purposes only!)
OUT_IQ_SEL
T5
O
Output I/Q select pin (low=I, high=Q) – only active in multiplexed I/Q output modes
RD
B6
I
READ - Active low read input (option: ground RD to use WR as a WR/RD pin)
RESET
B13
I
CHIP RESET – Active low input
SYNC_A
R14
I
Input synchronization pin A (active low)
SYNC_B
T14
I
Input synchronization pin B (active low)
SYNC_OUT
R13
O
Output sync pin (active low)
TCK
C8
TDI
A8
I
JTAG Data In
TDO
A7
O
JTAG Data Out
TEST_MODE
B7
I
Test mode (not required for operation; pull to GND)
TMS
B9
I
JTAG Mode Select
TRST
B8
I
JTAG Reset (during GC1115 reset, TRST must be pulled low, then high)
VDD
C4, C13, D3, D5,
D12, D14, E4, E6,
E7, E8, E9, E10,
E11, E13, F5, F12,
G5, G12, H5, H12,
J5, J12, K5, K12, L5,
L12, M4, M6–M11,
M13, N3, N5, N12,
N14, P4, P13
I
Digital core supply voltage, 1.2 V (40 pins)
VDD1
B14
I
Digital supply voltage for both PLLs (1 pin)
VDDA1
C16
I
PLL 1 analog supply voltage (1 pin)
I/O Data Bus - Active high bidirectional I/O
Note: This pin is also the Scan clock, when GC1115 is in scan mode.
72
I JTAG Clock
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (Alphabetical Listing) (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VDDA2
C10
I
PLL 2 analog supply voltage (1 pin)
VDDSHV
C5, D6–D11, E3,
E14, F4, F13, G4,
G13, H4, H13, J4,
J13, K4, K13, L4,
L13, M3, M14,
N6–N11, P5, P12
I
I/O supply voltage, 3.3 V (31 pins)
VPP
A11
I
E-fuse program supply voltage (not required for operation; pull to GND)
VSS
A1, A2, A15, A16,
B1, B2, B15, B16,
C3, C14, D4, D13,
E5, E12, F6–F11,
G6–G11, H6–H11,
J6–J11, K6–K11,
L6–L11, M5, M12,
N4, N13, P3, P14,
R1, R2, R15, R16,
T1, T2, T15, T16,
I
Digital ground (64 pins)
VSS1
C11
I
Digital ground for both PLLs (1 pin)
VSSA1
C15
I
PLL 1 analog ground (1 pin)
VSSA2
A14
I
PLL 2 analog ground (1 pin)
WR
A5
I
WRITE - Active low write input (option: ground RD to use WR as a WR/RD pin)
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APPLICATION INFORMATION
PC Board Layout Notes
1. Leave the LOOP pin unconnected.
2. Vpp is used only in manufacturing (for die ID). Attach Vpp via a pull-down resistor to GND.
3. SYNC_A and SYNC_B are input synchronization signals. SYNC_OUT is only needed to synchronize
multiple GC1115s, or if exact notification of a GC1115-internal event is needed (such as when a snapshot
RAM capture ends, or when the software timer count reaches zero). Wire SYNC_A, SYNC_B, and
SYNC_OUT_ to test points so they can be observed on a scope or logic analyzer.
4. During chip start-up, TRST must be pulled low and then high, or the GC1115 will not reset. A
general-purpose pin on the microprocessor or DSP that controls the GC1115 can do this operation. All other
JTAG signals are no-connects
5. Place power supply bypass caps on the back side of the board if possible.
Suggested Test Points:
• IN_CLK, OUT_CLK
• a few IN_A, IN_B, OUT_A, and OUT_B pins
• SYNC_A, SYNC_B, SYNC_OUT
• CS, RD, WR, plus a few A[ ] and D[ ] pins.
Power Connections
The PLL supplies should connect to dedicated pads with filtering as shown in Figure 16.
Series 50R
Ferrite Bead
VDDA Dedicated Package
Pin and Bond Pad
VDD Supply
0.1 µF
0.01 µF
VSSA Dedicated Package
Pin and Bond Pad
VSS Supply
Series 50R
Ferrite Bead
VDD Dedicated Package
Pin and Bond Pad
0.1 µF
0.01 µF
VSS Dedicated Package
Pin and Bond Pad
A.
The 50R ferrite beads should be similar to: Murata P/N: BLM31P500SPT.
Figure 16. Power-Supply Filter
The PLL's analog supply wires
• should be 30 µm or wider and located in metal level 2, 3, or 4
• should be routed directly to the PLL's analog supply pads
• should avoid crossing or running parallel to any other supply or signal wires
Recommended GC1115 Board Bring-up Procedures
When customers bring up a GC1115-based printed circuit board for the first time, TI recommends the following
sequence of checks:
74
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SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
APPLICATION INFORMATION (continued)
1.
2.
3.
4.
5.
6.
Check the GC1115 power pins for proper voltage levels (VDD, VDDSHV, VDDA1, VDDA2, and VDD1).
Check IN_CLK pin to verify the expected GC1115 input sampling rate.
Pull TRST low and then high to start the GC1115.
Perform a write/read test of all GC1115 control registers.
Enable the GC1115's internal pattern generator to perform an internal checksum (CRC) test on the GC1115.
Enable the GC1115 to bypass all PDC stages, enable the internal pattern generator to generate a sawtooth
waveform, and verify that the sawtooth waveform is observed on the GC1115 OUT_A and OUT_B pins.
7. While driving the GC1115's IN_A and IN_B pins with a test input signal and while bypassing all PDC stages,
verify that the data on OUT_A and OUT_B pins matches the input data (adjusted for the internal GC1115
delay).
8. If the GC1115 is connected to a DAC, drive the IN_A and IN_B pins with a high-quality sine wave and verify
that the expected SNR is achieved at the DAC output.
9. Finally, after determining the proper threshold and cancellation pulse coefficients, enable the PDC stages
and drive the GC1115 with a test signal whose CCDF, ACLR, cEVM, and PCDE values can be measured by
suitable test equipment.
About the GC1115 JTAG Interface
•
•
The GC1115 JTAG implementation supports both standard boundary scan (used for board test) and chip
identification commands. A BSDL file for the GC1115 is available on the TI web site,
http://focus.ti.com/docs/prod/folders/print/gc1115.html#productmodels.
The GC1115 identification string is a 32-bit string:
Hex:
Binary:
0x8
0x8
0xC
0x1
0x1
0x1
0x5
0x1
1000
1000
1100
0001
0001
0001
0101
0001
sync
•
•
mfr
device ID
chip revision
At GC1115 power-up, the state of the JTAG controller is indeterminate until after TRST is asserted.
For GC1115 designs that do not use JTAG, TRST must be pulled low and then high during initial GC1115
RESET, disabling JTAG. All other JTAG pins can be left unconnected (open).
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SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
APPENDIX – GLOSSARY OF TERMS
3G
Third generation (refers to next-generation wideband cellular systems that use CDMA)
3GPP
3GPP2 Third generation partnership project 2 (cdma2000 specification, www.3gpp2.org)
ACLR
Adjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier)
ACPR
Adjacent channel power ratio
ADC
Analog-to-digital converter
AWGN
Additive white Gaussian noise
BER
Bit error rate
BW
Bandwidth
CCDF
Complementary cumulative distribution function
CDF
Cumulative distribution function
CDMA
Code division multiple access (spread spectrum)
cdma2000
Qualcomm’s next generation CDMA standard (see www.3gpp2.org)
CDP
Code domain power
CEVM
Composite error vector magnitude
CFR
Crest factor reduction
CMOS
Complementary metal oxide semiconductor
DAC
Digital-to-analog converter
dB
decibels
dBm
decibels relative to 1 mW (30 dBm = 1 W)
DSP
Digital signal processing or digital signal processor
DSSS
Direct sequence spread spectrum
DUC
Digital up-converter (usually provides the GC1115 input)
EVM
Error vector magnitude
FIR
Finite impulse response (type of digital filter)
I&Q
In-phase and quadrature (signal representation)
IF
Intermediate frequency
IIR
Infinite impulse response (type of digital filter)
JTAG
Joint Test Action Group (chip debug and test standard 1149.1)
LO
Local oscillator
LSB
Least significant bit
MSB
Most significant bit
Msps
Megasamples per second (1x10E6 samples/sec)
NPR
Noise power ratio
PA
Power amplifier
PAR
Peak-to-average ratio
PCDE
Peak code domain error
PDC
Peak detection and cancellation (stage)
76
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APPENDIX – GLOSSARY OF TERMS (continued)
PDF
Probability density function
RF
Radio frequency
RMS
Root mean square (method to quantify error)
SEM
Spectrum emission mask
SNR
Signal-to-noise ratio (usually measured in dB or dBm)
UMTS
Universal mobile telephone service
VSA
Vector signal analyzer
W-CDMA
Wideband code division multiple access (synonymous with 3GPP)
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Errata Page for rev0 Silicon
1. 3-wire up mode does not work as described – use 2-wire mode.
2. Detection threshold for stages 3 and 4 are wired together under normal operating circumstances.
78
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SLWS144C – FEBRUARY 2005 – REVISED JUNE 2006
Revision History
DATE
REV
PAGE
JUN 06
C
66
Latency
Added an equation to calculate the latency of the device.
71
Device Information
Corrected OUT_A and OUT_B pin labeling.
72
Terminal Information
Corrected OUT_A and OUT_B pin labeling.
13
Operating Modes
Valid decimation values are 1 and 2.
16
Microprocessor I/F
Clarified 2-pin and 3-pin operation.
65
GC1115 Power
New section on power consumption.
66
Recommended
Operating Conditions
Added max. power consumption specification.
67
Switching
Characteristics
Updated tperiod, tout_hd, tout_dly.
69
Figure 15
Updated tout_hd and tout_dly diagram.
71
Terminal Functions
WR_ is used in two-pin mode to distinguish between read and write.
72
Terminal Functions
RD_ is grounded in two-pin mode.
Changed VSS: G7-G11 to G6-G11.
Changed VSS: L7-L11 to L6-L11.
73
Figure 16
Removed extraneous text.
74
GC1115 JTAG
New section on JTAG usage.
2
Functional Block
Diagram
Changed PLL1 to PLL_CORE and PLL2 to PLL_TX.
10
Table 1
Updated cEVM and PCDE performance measurements.
14
Table 4
Corrected PLL_MULT column entries.
30
Table 15
Table was double-labeled (“Table 15. Table 17.”). Also added a column for
hex values as well as decimal values.
43
CANCEL_DATA
Cancel coefficients are 12 bits wide, not 16 bits wide.
44
DELAY_MASK
Changed hex address 0x12 to 0x14 (20 decimal).
66
Tables
Updated various table values (Dissipation, Capacitance, etc.)
Switching
Characteristics
Updated various switching and timing parameters.
68
Timing Parameter
Information
Removed Figure 15, Read Cycle - Normal Mode
73
Application Information
Added a “Recommended Board Bring-up Procedures” section.
–
–
OCT 05
JUL 05
B
A
66-67
FEB 04
*
SECTION
DESCRIPTION
Original version
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
GC1115IZDJ
ACTIVE
BGA
ZDJ
Pins Package Eco Plan (2)
Qty
256
90
Pb-Free
(RoHS)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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