8-Bit CMOS Microcontorller GMS97C2051/L2051 Features TM Compatible with MCS-51 Products 2 Kbytes of programmable EPROM 4.25V to 5.5V Operating Range (GMS97C2051) 2.70V to 3.6V Operating Range (GMS97L2051) Version for 12MHz / 24 MHz Operating frequency (GMS97C2051) Only 12MHz Operating frequency (GMS97L2051) Two-Level Program Memory Lock with encryption array 128 bytes SRAM 15 Programmable I/O Lines Two 16-Bit Timer/Counters Programmable serial USART Five Interrupt Sources Direct LED Drive Outputs On-Chip Analog Comparator Low Power Idle and Power Down Modes Description The GMS97C2051/L2051 is a high-performance CMOS 8-bit microcontroller with 2Kbytes of programmable EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUNDAI MicroElectronics GMS97C2051/L2051 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS97C2051/L2051 provides the following standard features: 2Kbytes of EPROM, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the GMS97C2051/L2051 supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration PDIP/SOP RST (RXD) P3.0 (TXD) P3.1 XTAL2 XTAL1 ( INT0 )P3.2 ( INT1 ) P3.3 (T0) P3.4 (T1) P3.5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 1 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Block Diagram VCC RAM ADDR GND RAM B REGISTER EPROM PROGRAM ADDRESS REGISTER STACK POINTER ACC TMP2 TMP1 BUFFER PC INCREMENTER ALU INTERRUPT, SERIAL PORT AND TIMER BLOCKS PROGRAM COUNTER PSW RST TIMING AND CONTROL INSTRUCTION DPTR REGISTER ANALOG COMPARATOR PORT 3 LATCH PORT 1 LATCH + _ OSC PORT 1 DRIVERS PORT 3 DRIVERS P1.0-P1.7 HYUNDAI MicroElectronics P3.0-P3.5 2 P3.7 8-Bit CMOS Microcontorller GMS97C2051/L2051 Pin Description Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Vcc XTAL2 Supply voltage. Output from the inverting oscillator amplifier. GND Recommended Oscillator Circuit Ground. XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. Port 1 Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 10mA and can drive LED displays directly. When 1s are written to Port1 pins, they can be used as inputs. When pins Figure 1. P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during EPROM programming and program verification. Oscillator Connections C2 XTAL2 Port3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional C1 I/O pins with internal pullups. P3.6 is hard-wired as XTAL1 an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 10mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins GND that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special fea- Notes: C1, C2 = 30pF 10pF for Crystals ture of the GMS97C2051 as listed below: ( include stray capacitance ) Port Pin Alternate Functions P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 RXD ( serial input port ) TXD ( serial output port ) INT0 ( external interrupt 0 ) Figure 2. External Clock Drive Configuration NC INT1( external interrupt 1 ) T0 ( timer 0 external input ) T1 ( timer 0 external input ) Port 3 also receives some control signals for EPROM programming and programming verification. XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. This pin is also receives the 12.75V programming supply voltage ( Vpp ) during EPROM programming. GND XTAL1 3 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the Table1, Table 2 and Table 3. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 1. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. GMS97C2051/L2051 SFR Map and Reset Values 0F8H 0F0H 0FFH B 00000000 0F7H 0E8H 0E0H 0EFH ACC 00000000 0E7H 0D8H 0D0H 0DFH PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H 0B0H 0A8H IP XXX00000 P3 11111111 IE 0XX00000 0BFH 0B7H 0AFH 0A0H 98H 90H 88H 80H 0A7H SCON 00000000 P1 11111111 TCON 00000000 SBUF XXXXXXXX 9FH 97H TMOD 00000000 SP 00000111 HYUNDAI MicroElectronics TL0 TL1 TH0 TH1 00000000 00000000 00000000 00000000 DPL DPH 00000000 00000000 4 8FH PCON 0XXX0000 87H 8-Bit CMOS Microcontorller GMS97C2051/L2051 Table 2. Bit Assignment of SFRs Address Register 81H SP 82H DPL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 83H DPH 87H PCON SMOD - - - GF1 GF0 PD IDLE 88H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD GATE C/ T M1 M0 GATE C/ T M1 M0 8AH TL0 8BH TL1 8CH TH0 8DH TH1 90H P1 98H SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 99H SBUF A8H IE EA - - ES ET1 EX1 ET0 EX0 B0H P3 B8H IP - - - PS PT1 PX1 PT0 PX0 D0H PSW CY AC F0 RS1 RS0 OV F1 P E0H ACC F0H B - : This Bit Location is reserved Bit manipulation is available Bit manipulation is not available 5 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Table 3. SFR lists and their addresses Symbol Name Address * ACC *B DPH DPL * PSW SP Accumulator B Register Data Pointer High Byte Data Pointer Low Byte Program Status Word Stack Pointer E0H F0H 83H 82H D0H 81H * IE * IP Interrupt Enable Control Interrupt Priority Control A8H B8H * P1 * P3 Port 1 Port 3 90H B0H * SCON SBUF Serial Control Serial Data Buffer 98H 99H * TCON TH0 TH1 TL0 TL1 * TMOD Timer/Counter Control Timer/Counter 0 High Bytes Timer/Counter 1 High Bytes Timer/Counter 0 Low Bytes Timer/Counter 1 Low Bytes Timer/Counter Mode Control 88H 8CH 8DH 8AH 8BH 89H * = Bit addressable SFR Timer/Counter 0 and 1 The GMS97C2051/L2051 has two 16-bit Timer/ Counter register : Timer0 and Timer1 . As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin P3.4/T0 and P3.5/T1. Since 2 machine cycles Table 4. Timer / Counter 0 and 1 Operating Modes Mode are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. External inputs P3.2/INT0 and 3.3/INT1 can be programmed to function as a gate to facilitate pulse width measurements. Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4. Figure 3 illustrates the input clock logic. Description TMOD Gate C/T M1 M0 0 8-bit Timer/Counter with 5-bit prescaler × × 0 0 1 16-bit timer/counter × × 0 1 2 8-bit Auto-Reload Timer/Counter × × 1 0 3 (Timer 0) : TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit Timer and is controlled by Timer 1 (Timer 1) : stop × × 1 1 HYUNDAI MicroElectronics 6 8-Bit CMOS Microcontorller GMS97C2051/L2051 Figure 3. Time/Counter 0 and 1 Input Clock Logic 12 fosc fosc/12 C/T TMOD 0 P3.4/T0 P3.5/T1 max fosc/24 Timer 0/1 Input Clock 1 Control TR 0/1 TCON & Gate =1 TMOD 1 P3.2/INT0 P3.3/INT1 Serial Interface (USART) The serial port is full duplex, meaning it can transmit and receive simultaneously. And it can operate in four modes (one synchronous mode, three asynchronous mode) as illustrated in table 5. The possiTable 5. USART Operating Modes Mode 0 1 SCON SM0 SM1 0 0 0 1 ble baud rates can be calculated using the formulas given in table 6. Baud Rate Description fosc / 12 ( fixed ) Shift Register : Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted / received, with the LSB first. 8-bit UART : Ten bits are transmitted through TXD, or received through RXD a start bit (0), 8 data bits (LSB first), and a stop bit (1) 9-bit UART : Eleven bits are transmitted through TXD, or received through RXD a start bit (0), 8 data bits (LSB first), a programmable ninth data bit , and a stop bit (1) 9-bit UART : The same as Mode 2 except the variable baud rate. Set by Timer ( variable ) 2 1 0 fosc / 64 or fosc / 32 ( fixed ) 3 1 1 Set by Timer ( variable ) 7 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Table 6. Formulas for calculating Baud rates Baud Rate generated from Serial Port Mode Oscillator 0 2 Timer1 (Timer1 Mode2) 1,3 1,3 Interrupt Baud Rate fosc / 12 SMOD x fosc) / 64 (2 SMOD (2 x Timer1 overflow rate) / 32 SMOD x fosc) / [32 x 12 x (256-TH1)] (2 System The GMS97C2051/L2051 provides 5 interrupt sources ( two external interrupts, two timer interrupts and serial port interrupt ) with two priority levels. Figure 4 gives a general overview of the interrupt sources and illustrates the request and control flags. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence like Table 8. Figure 4. Interrupt Request Sources P3.2/ High Priority Low Priority IE0 INT0 TCON.1 IT0 TCON.0 Timer 0 Overflow EX0 PX0 IE.0 IP.0 TF0 TCON.5 P3.3/ ET0 PT0 IE.1 IP.1 EX1 PX1 IE.2 IP.2 IE1 INT1 TCON.3 IT1 TCON.2 Timer 1 Overflow TF1 TCON.7 R1 USART SCON.0 ET1 PT1 IE.3 IP.3 1 T1 ES PS SCON.1 IE.4 IP.4 EA IE.7 HYUNDAI MicroElectronics 8 8-Bit CMOS Microcontorller GMS97C2051/L2051 Table 7. Interrupt Sources and their corresponding Interrupt Vectors Interrupt Source Vector Address External interrupt 0 Timer0 External Interrupt 1 Timer1 Serial Port Interrupt System Reset IE0 TF0 IE1 TF1 RI + TI RST 0003H 000BH 0013H 001BH 0023H 0000H Table 8. Interrupt Priority-Within-Level Interrupt Source External interrupt 0 Timer0 interrupt External Interrupt 1 Timer1 interrupt Serial Port Interrupt Priority IE0 TF0 IE1 TF1 RI + TI Highest Lowest Restrictions on Certain Instructions rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved. The GMS97C2051/L2051 is an economical and costeffective member of HYUNDAI MicroElectronics growing family of microcontrollers. It contains 2Kbytes of EPROM program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. 2. MOVX-related instructions, Data Memory: The GMS97C2051/L2051 contains 128 bytes of internal data memory. Thus, in the GMS97C2051/L2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the GMS97C2051/L2051). Violating the physical space limits may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same 9 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Power Down Mode Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to ‘0’ if no external pullups are used, or set to ‘1’ if external pullups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following one that invokes Idle should not be one that writes to a port pin or to external memory. GMS97C2051/L2051 have two power saving modes, Idle and Power Down. The bits PD and IDLE of the register PCON select the Power Down mode and the Idle mode, respectively. If 1s are written to PD and IDLE at the same time, PD takes precedence. Table 9 gives a general overview of the Power saving modes. In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that Vcc is not reduced before the Power Down mode is invoked, and that Vcc is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power down mode also restarts the oscillator. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). Table 9. Power Saving Modes Overview Mode Ex. instruction to enter To terminate Idle mode ORL PCON, #01H Enabled interrupt, Hardware Reset - CPU is gated off - CPU status registers maintain their data. - Peripherals are active Power-down Mode ORL PCON, #02H Hardware Reset - Oscillator stops - Contents of on-chip RAM and SFRs are maintained - Reset redefines all the SFRs but does not change the on-chip RAM HYUNDAI MicroElectronics 10 Remarks 8-Bit CMOS Microcontorller GMS97C2051/L2051 to the appropriate levels. Output data can be read at the port P1 pins. At this time P3.0 should not be changed. 8. To program a byte at the next address location, P3.0 level transition is needed to advance the internal address counter. Apply new data to the port P1 pins. 9. Repeat step 5 through 8, changing data and advancing the address counter for the entire 2K bytes array. Programming The EPROM The GMS97C2051/L2051 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the P3.2( PROG ) . The GMS97C2051/L2051 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by HME . Table 10 shows the logic levels for reading the signa- Program Verify : ture byte, and for programming the program memory, If lock bits LB1 and LB2 have not been programmed, the encryption table, and the security bits. The circuit code data can be read back via port P1 pins. configuration and waveforms for quick-pulse pro- 1. Set the internal address counter to 07FFH by bringing RST from ‘L’ to ‘H’ and reset the gramming are shown in Figures 5 and Figure 8. internal address counter to 0000H by bringing P3.0 Figure 6 shows the circuit configuration for normal from ‘H’ to ‘L’. program memory verification. 2. Apply the appropriate control signals for Read Code data to pins P3.3, P3.4, P3.5, P3.7 and read EPROM Programming and Verification the output data at the port P1 pins. 3. The P3.0 level transition is taken to advance the Internal Address Counter : internal address counter. The GMS97C2051/L2051 contains an internal EPROM 4. Read the next code data byte at the port P1 pins. address counter which is always set to 07FFH on the 5. Repeat step 3 and 4 until the entire array is read. rising edge of RST after setting P3.0 to ‘H’ and is advanced by applying continuous level transition to pin Program Memory Lock Bits P3.0. The two-level Program Lock system consists of 2 Lock Programming Algorithm : To program the GMS97C2051/L2051, the following bits and a 32-byte Encryption Array which are used to protect the program memory against software piracy. sequence is recommended. 1. Power-up Sequence Encryption Array : Apply power between VCC and GND pins with Within the EPROM array are 32 bytes of Encryption crystal oscillation. Array that are initially unprogrammed (all 1s). Every Set P3.0 to ‘H’. time that a byte is addressed during a verify, address Set RST to GND. lines are used to select a byte of the Encryption array. With all other pins floating, wait for greater than This byte is then exclusive-NORed (XNOR) with the 10ms. code byte, creating an Encrypted Verify byte. 2. Set pin RST to ‘H’ and pin P3.2 to ‘H’. The algorithm, with the array in the unprogrammed 3. Apply the appropriate combination of ‘H’ or ‘L’ state (all 1s), will return the code in its original, unlogic levels to pins P3.3, P3.4, P3.5, P3.7 to select modified form. It is recommended that whenever the one of the programming operations shown in the Encryption Array is used, at least one of the Lock Bits EPROM Programming Modes. (Table 10). be programmed as well. To program and verify the array 4. The P3.0 level is pulled ‘L’ and apply data for code byte at location 0000H to P1.0 to P1.7 5. Raise RST to 12.75V to enable pr ogramming. 6. The P3.2( PROG ) is pulsed low 10 times as shown in Figure 8. Each programming pulse is low for 100us(±10us) and high for a minimum of 10us. 7. To verify the programmed data, lower RST from 12.75V to logic ‘H’ level and set pins P3.3 to P3.7 11 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller Reading the Signature Bytes : The signature bytes are read by the same procedure as a normal verification of locations 000H and 001H, except that P3.5 and P3.7 need to be pulled to a logic low. Manufacturer ID: (00H) = E0H ( Indicates manufactured by HEI ) Lock Bit Protection Modes Program Lock Bits LB1 LB2 1 U U 2 P U 3 P P Protection Type No program lock features. Further programming of the EPROM is disabled. Same as mode 2, also verify is disabled. Device ID: (01H) = 26H ( Indicates GMS97C2051/L2051 ) U : unprogrammed, P : programmed EPROM Programming Modes Table 10. EPROM Programming Modes Mode RST P3.2/ PROG P3.3 P3.4 P3.5 P3.7 1 1 0 0 0 0 0 1 1 1 0 0 1 1 Read Signature Program Code Data Vpp Verify Code Data 1 1 Pgm encryption table Vpp 0 1 0 1 Pgm encryption bit1 Vpp 1 1 1 1 Pgm encryption bit Vpp 1 1 0 0 Notes:1. '0' = Valid low, '1' = Valid high for that pin. 2. Vpp = 12.75 V 0.25 V 3. Vcc = 5 V 10 % during programming and verification. HYUNDAI MicroElectronics 12 4. P3.2/ PROG receives 10 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100uS (10uS) and high for a minimum of 10uS. 8-Bit CMOS Microcontorller GMS97C2051/L2051 Figure 5. Programming the EPROM Memory GMS97C1051 P3.0 5V GMS97C1051 VCC To Increment Address Counter PROG Figure 6. Verifying the EPROM Memory P1 P3.0 PGM DATA 5V PGM DATA P1 P3.2 P3.3 See EPROM Programming Modes Tables VCC To Increment Address Counter P3.2 5V P3.3 See EPROM Programming Modes Tables P3.4 P3.5 P3.4 P3.5 P3.7 P3.7 XTAL1 XTAL1 4~6MHz 4~6MHz XTAL2 RST Vpp RST XTAL2 GND 5V GND EPROM Programming and Verification Characteristics Table 11. EPROM Programming and Verification Characteristics Parameter Symbol Min Max Programming Supply Voltage VPP 12.5 13.0 V Programming Supply Current IPP 50 mA Oscillator Frequency 1 / tCLCL 4 6 MHz Address Setup to PROG Low tAVGL 48 tCLCL Data Setup to PROG Low tDVGL 48 tCLCL Data Hold after PROG tGHDX 48 tCLCL P3.4 ( ENABLE ) High to VPP tEHSH 48 tCLCL VPP Setup to PROG Low tSHGL 10 us VPP Hold After PROG tGHSL 10 us PROG Width tGLGH 90 PROG High to PROG Low tGHGL 10 P3.4 ( ENABLE ) Low to Data Valid tELQV Data Float after P3.4 ( ENABLE ) tEHQZ 110 Units us us 48 tCLCL 0 48 tCLCL TA= 21 to 27, VCC = 5.0 10% 13 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller EPROM Programming and Verification Waveforms Figure 7. EPROM Programming and Verification Programming Verification VPP LOGIC 1 RST tSHGL (VPP) LOGIC 0 tGHSL tEHSH P3.2 (PROG) tGLGH tGHGL P3.4 tGHDX tDVGL (ENABLE) tELQV DATA IN PORT1 tEHQZ DATA OUT Address (N+1) tAVGL P3.0 Address (N) Figure 8. Programming Waveform 10 PULSES P3.2/ PROG 10 MIN 100 P3.2/ PROG HYUNDAI MicroElectronics 14 ±10 8-Bit CMOS Microcontorller GMS97C2051/L2051 Absolute Maximum Ratings Ambient temperature under bias (TA.)....................... - 40 to + 85 to + 150 Storage temperature (TST) ..... -65 Voltage on VCC pin with respect to Ground(VSS)...........-0.5V to 6.5V Voltage on any pin with respect to Ground(VSS)... -0.5V to VCC+0.5V Input Current on any pin during overload condition.........-10mA to +10mA NOTE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > Vcc or VIN < Vss ) the voltage on Vcc pins with respect to ground (Vss) must not exceed the values defined by the absolute maximum ratings. Absolute sum of all input current during overload condition................... | 100 mA | 15 HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller D.C. Characteristics (5V Version) Vcc = 4.25V to 5.5V, Vss= 0V, O O TA= 0 C to 70 C for the GMS97C2051/C1051 Parameter Symbol Limit Values Min Max Unit Test Condition Input Low Voltage VIL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V IOL=10mA,Vcc=5V Output High Voltage (ports 1,3) VOH V IOH= -80uA, Vcc=5V±10% IOH= -30uA IOH= -12uA 2.4 0.75Vcc 0.9Vcc Logical 0 Input Current (ports 1,3) IIL -50 uA VIN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA VIN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<VIN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=5V Comparator Input VCM Vcc V CIO 10 pF Test Freq.=1MHz, TA=25 C Icc Iccidle Icc Iccidle Ipd 20 12 30 15 100 mA mA mA mA uA Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V, P1.0&P1.1=0 or Vcc 0 Common Mode Voltage Pin Capacitance Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Active mode, 24Mhz Idle mode, 24Mhz Power Down mode HYUNDAI MicroElectronics 16 O 8-Bit CMOS Microcontorller GMS97C2051/L2051 D.C. Characteristics (3V Version) Vcc = 2.7V to 3.6V, Vss= 0V, O O TA= 0 C to 70 C for the GMS97L2051/L1051 Parameter Symbol Limit Values Min Max Unit Test Condition Input Low Voltage VIL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V IOL=6mA,Vcc=2.7V Output High Voltage (ports 1,3) VOH V IOH= -30uA IOH= -12uA 0.75Vcc 0.9Vcc Logical 0 Input Current (ports 1,3) IIL -50 uA VIN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA VIN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<VIN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=3V Comparator Input VCM Vcc V CIO 10 pF Test Freq.=1MHz, TA=25 C Icc Iccidle Ipd 10 5 50 mA mA uA Vcc=3V Vcc=3V, P1.0&P1.1=0 or Vcc Vcc=3V, P1.0&P1.1=0 or Vcc 0 Common Mode Voltage Pin Capacitance Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Power Down mode 17 O HYUNDAI MicroElectonics GMS97C2051/L2051 8-Bit CMOS Microcontroller External Clock drive waveforms tCHCX tCHCX tCHCL tCLCH VCC - 0.5 V 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL External Clock Drive GMS97L2051/L1051 Parameter Min Max Min Max 1/tCLCL Oscillator Frequency 0 12 0 24 tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time - 20 - 20 ns tCHCL Fall Time - 20 - 20 ns AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.2VCC + 0.9V HYUNDAI MicroElectronics VLOAD + 0.1V VLOAD - 0.1V Timing Reference VLOAD 0.2VCC - 0.1V Note: 1. AC Inputs during testing are driven at VCC 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. MHz Float Waveforms(1) TEST POINTS 0.45V GMS97C2051/C1051 Units Symbol Points VOL + 0.1V VOL + 0.1V Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded VOH/VOL level occurs. 18 8-Bit CMOS Microcontorller GMS97C2051/L2051 Package Dimension 20 PDIP unit : mm ( inch ) 20 SOP 19 HYUNDAI MicroElectronics GMS97C2051/L2051 8-Bit CMOS Microcontroller Ordering Information Speed ( MHz) Power Supply 12 2.7V to 3.6V 4.25V to 5.5V 24 4.25V to 5.5V Ordering Code Package GMS97L2051 20 PDIP GMS97L2051-D 20 SOP GMS97C2051 20 PDIP GMS97C2051-D 20 SOP GMS97C2051-24 20 PDIP GMS97C2051-24D 20 SOP Package Type Wide, Plastic Dual Inline Package (PDIP) Wide, Plastic Gull Wing Small Outline (SOP) 20 PDIP 20 Lead, 0.300 20 SOP 20 Lead, 0.300 HYUNDAI MicroElectronics 20 Operation Range Commercial to 70) (0 8-Bit CMOS Microcontorller GMS97C1051/L1051 Features TM Compatible with MCS-51 Products 1 Kbytes of programmable EPROM 4.25V to 5.5V Operating Range (GMS97C1051) 2.70V to 3.6V Operating Range (GMS97L1051) Version for 12MHz / 24 MHz Operating frequency (GMS97C1051) Only 12MHz Operating frequency (GMS97L1051) Two-Level Program Memory Lock with encryption array 64 bytes SRAM 15 Programmable I/O Lines One 16-Bit Timer/Counter Three Interrupt Sources Direct LED Drive Outputs On-Chip Analog Comparator Low Power Idle and Power Down Modes Description The GMS97C1051/L1051 is a high-performance CMOS 8-bit microcontroller with 1Kbytes of programmable EPROM. The device is compatible with the industry standard MCS-51TM instruction set and pinout. The HYUNDAI MicroElectronics GMS97C1051/L1051 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS97C1051/L1051 provides the following standard features: 1Kbytes of EPROM, 64 bytes of RAM, 15 I/O lines, 16-bit timer/counter, a three vector two-level interrupt architecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the GMS97C1051/L1051 supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Configuration PDIP/SOP RST P3.0 P3.1 XTAL2 XTAL1 ( INT0 )P3.2 ( INT1 ) P3.3 (T0) P3.4 P3.5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 21 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Block Diagram VCC RAM ADDR GND RAM B REGISTER EPROM PROGRAM ADDRESS REGISTER STACK POINTER ACC TMP2 TMP1 BUFFER PC INCREMENTER ALU INTERRUPT , TIMER BLOCKS PROGRAM COUNTER PSW RST TIMING AND CONTROL INSTRUCTION DPTR REGISTER ANALOG COMPARATOR PORT 3 LATCH PORT 1 LATCH + _ OSC PORT 1 DRIVERS P1.0-P1.7 HYUNDAI MicroElectronics PORT 3 DRIVERS P3.0-P3.5 22 P3.7 8-Bit CMOS Microcontorller GMS97C1051/L1051 Output from the inverting oscillator amplifier. Pin Description Recommended Oscillator Circuit Vcc XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configGND ured for use as an on-chip oscillator, as shown in FigGround. ure 1. To drive the device from an external clock Port 1 source, XTAL2 should be left unconnected while Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 XTAL1 is driven as shown in Figure 2. to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), Figure 1. Oscillator Connections respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 10mA and can drive LED displays directly. When 1s are written to C2 Port1 pins, they can be used as inputs. When pins XTAL2 P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during EPROM proC1 gramming and program verification. Supply voltage. XTAL1 Port3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is GND not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 10mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins Notes: C1, C2 = 30pF 10pF for Crystals that are externally being pulled low will source current ( include stray capacitance ) (IIL) because of the pullups. Port 3 also serves the functions of various special feaFigure 2. External Clock Drive Configuration ture of the GMS97C1051/L1051 as listed below: Port Pin Alternate Functions P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) NC Port 3 also receives some control signals for EPROM programming and programming verification. XTAL2 EXTERNAL OSCILLATOR SIGNAL XTAL1 RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. This pin is also receives the 12.75V programming supply voltage ( Vpp ) during EPROM programming. GND XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 23 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the Table1, Table 2 and Table 3. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. Table 1. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. GMS97C1051/L1051 SFR Map and Reset Values 0F8H 0F0H 0FFH B 00000000 0F7H 0E8H 0E0H 0EFH ACC 00000000 0E7H 0D8H 0D0H 0DFH PSW 00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H 0B0H 0A8H IP XXX00000 P3 11111111 IE 0XX00000 0BFH 0B7H 0AFH 0A0H 0A7H 98H 90H 88H 80H 9FH P1 11111111 TCON 00000000 97H TMOD 00000000 SP 00000111 HYUNDAI MicroElectronics TL0 TH0 00000000 00000000 DPL DPH 00000000 00000000 24 8FH PCON 0XXX0000 87H 8-Bit CMOS Microcontorller GMS97C1051/L1051 Table 2. Bit Assignment of SFRs Address Register 81H SP 82H DPL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 83H DPH 87H PCON - - - - GF1 GF0 PD IDLE 88H TCON - - TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD - - - - GATE C/ T M1 M0 8AH TL0 8CH TH0 90H P1 A8H IE EA - - - - EX1 ET0 EX0 B0H P3 B8H IP - - - - - PX1 PT0 PX0 D0H PSW CY AC F0 RS1 RS0 OV F1 P E0H ACC F0H B - : This Bit Location is reserved Bit manipulation is available Bit manipulation is not available 25 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Table 3. SFR lists and their addresses Symbol Name Address * ACC *B DPH DPL * PSW SP Accumulator B Register Data Pointer High Byte Data Pointer Low Byte Program Status Word Stack Pointer E0H F0H 83H 82H D0H 81H * IE * IP Interrupt Enable Control Interrupt Priority Control A8H B8H * P1 * P3 Port 1 Port 3 90H B0H Timer/Counter Control Timer/Counter 0 High Bytes Timer/Counter 0 Low Bytes Timer/Counter Mode Control 88H 8CH 8AH 89H * TCON TH0 TL0 * TMOD * = Bit addressable SFR Timer/Counter 0 The GMS97C1051/L1051 has one 16-bit Timer/ Counter register : Timer0 . As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin P3.4/T0. Since 2 machine cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. External inputs P3.2/INT0 and 3.3/INT1 can be programmed to function as a gate to facilitate pulse width measurements. Timer/Counter 0 can be used in four operating modes as listed in Table 4. Figure 3 illustrates the input clock logic. Table 4. Timer / Counter 0 Operating Modes Mode Description TMOD Gate C/T M1 M0 0 8-bit Timer/Counter with 5-bit prescaler × × 0 0 1 16-bit timer/counter × × 0 1 2 8-bit Auto-Reload Timer/Counter × × 1 0 3 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits, TH0 is an 8-bit Timer × × 1 1 HYUNDAI MicroElectronics 26 8-Bit CMOS Microcontorller GMS97C1051/L1051 Figure 3. Time/Counter 0 Input Clock Logic 12 fosc fosc/12 C/T TMOD 0 Timer 0 P3.4/T0 max fosc/24 Input Clock 1 Control TR 0 TCON & Gate =1 TMOD 1 P3.2/INT0 P3.3/INT1 Interrupt System The GMS97C1051/L1051 provides 3 interrupt sources ( two external interrupts and timer interrupt ) with two priority levels. Figure 4 gives a general overview of the interrupt sources and illustrates the request and control flags. A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence like Table 6. Figure 4. Interrupt Request Sources High Priority Low Priority P3.2/ IE0 INT0 TCON.1 IT0 TCON.0 EX0 PX0 IE.0 IP.0 TF0 Timer 0 Overflow TCON.5 ET0 PT0 IE.1 IP.1 EX1 PX1 P3.3/ IE1 INT1 IT1 TCON.2 TCON.3 IP.2 IE.2 EA IE.7 27 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Table 5. Interrupt Sources and their corresponding Interrupt Vectors Interrupt Source Vector Address External interrupt 0 Timer0 External Interrupt 1 System Reset IE0 TF0 IE1 RST 0003H 000BH 0013H 0000H Table 6. Interrupt Priority-Within-Level Interrupt Source External interrupt 0 Timer0 interrupt External Interrupt 1 Priority IE0 TF0 IE1 Highest Lowest Restrictions on Certain Instructions The GMS97C1051/L1051 is an economical and costeffective member of HYUNDAI MicroElectronics growing family of microcontrollers. It contains 1Kbytes of EPROM program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 3FFH for the GMS97C1051/L1051). Violating the physical space limits may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same HYUNDAI MicroElectronics 28 rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family architecture have been preserved. 2. MOVX-related instructions, Data Memory: The GMS97C1051/L1051 contains 64 bytes of internal data memory. Thus, in the GMS97C1051/L1051 the stack depth is limited to 64 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. 8-Bit CMOS Microcontorller GMS97C1051/L1051 Power Down Mode Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to ‘0’ if no external pullups are used, or set to ‘1’ if external pullups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following one that invokes Idle should not be one that writes to a port pin or to external memory. GMS97C1051/L1051 have two power saving modes, Idle and Power Down. The bits PD and IDLE of the register PCON select the Power Down mode and the Idle mode, respectively. If 1s are written to PD and IDLE at the same time, PD takes precedence. Table 7 gives a general overview of the Power saving modes. In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that Vcc is not reduced before the Power Down mode is invoked, and that Vcc is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power down mode also restarts the oscillator. The reset should not be activated before Vcc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. ( similar to power-on reset ). Table 7. Power Saving Modes Overview Mode Ex. instruction to enter To terminate Idle mode ORL PCON, #01H Enabled interrupt, Hardware Reset - CPU is gated off - CPU status registers maintain their data. - Peripherals are active Power-down Mode ORL PCON, #02H Hardware Reset - Oscillator stops - Contents of on-chip RAM and SFRs are maintained - Reset redefines all the SFRs but does not change the on-chip RAM 29 Remarks HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller to the appropriate levels. Output data can be read at the port P1 pins. At this time P3.0 should not be changed. 8. To program a byte at the next address location, P3.0 level transition is needed to advance the internal address counter. Apply new data to the port P1 pins. 9. Repeat step 5 through 8, changing data and advancing the address counter for the entire 1K bytes array. Programming The EPROM The GMS97C1051/L1051 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the P3.2( PROG ) . The GMS97C1051/L1051 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by HME. Table 8 shows the logic levels for reading the signature Program Verify : byte, and for programming the program memory, the If lock bits LB1 and LB2 have not been programmed, encryption table, and the security bits. The circuit con- code data can be read back via port P1 pins. figuration and waveforms for quick-pulse programming 1. Set the internal address counter to 03FFH by bringing RST from ‘L’ to ‘H’ and reset the are shown in Figures 5 and Figure 8. Figure 6 internal address counter to 0000H by bringing P3.0 shows the circuit configuration for normal program from ‘H’ to ‘L’. memory verification. 2. Apply the appropriate control signals for Read Code data to pins P3.3, P3.4, P3.5, P3.7 and read EPROM Programming and Verification the output data at the port P1 pins. 3. The P3.0 level transition is taken to advance the Internal Address Counter : internal address counter. The GMS97C1051/L1051 contains an internal EPROM 4. Read the next code data byte at the port P1 pins. address counter which is always set to 03FFH on the 5. Repeat step 3 and 4 until the entire array is read. rising edge of RST after setting P3.0 to ‘H’ and is advanced by applying continuous level transition to pin Program Memory Lock Bits P3.0. The two-level Program Lock system consists of 2 Lock Programming Algorithm : To program the GMS97C1051/L1051, the following bits and a 32-byte Encryption Array which are used to protect the program memory against software piracy. sequence is recommended. 1. Power-up Sequence Encryption Array : Apply power between VCC and GND pins with Within the EPROM array are 32 bytes of Encryption crystal oscillation. Array that are initially unprogrammed (all 1s). Every Set P3.0 to ‘H’. time that a byte is addressed during a verify, address Set RST to GND. lines are used to select a byte of the Encryption array. With all other pins floating, wait for greater than This byte is then exclusive-NORed (XNOR) with the 10ms. code byte, creating an Encrypted Verify byte. 2. Set pin RST to ‘H’ and pin P3.2 to ‘H’. The algorithm, with the array in the unprogrammed 3. Apply the appropriate combination of ‘H’ or ‘L’ state (all 1s), will return the code in its original, unlogic levels to pins P3.3, P3.4, P3.5, P3.7 to select modified form. It is recommended that whenever the one of the programming operations shown in the Encryption Array is used, at least one of the Lock Bits EPROM Programming Modes. (Table 8). be programmed as well. To program and verify the array 4. The P3.0 level is pulled ‘L’ and apply data for code byte at location 0000H to P1.0 to P1.7 5. Raise RST to 12.75V to enable pr ogramming. 6. The P3.2( PROG ) is pulsed low 10 times as shown in Figure 8. Each programming pulse is low for 100us(±10us) and high for a minimum of 10us. 7. To verify the programmed data, lower RST from 12.75V to logic ‘H’ level and set pins P3.3 to P3.7 HYUNDAI MicroElectronics 30 8-Bit CMOS Microcontorller GMS97C1051/L1051 Reading the Signature Bytes : The signature bytes are read by the same procedure as a normal verification of locations 000H and 001H, except that P3.5 and P3.7 need to be pulled to a logic low. Lock Bit Protection Modes Program Lock Bits LB1 LB2 1 U U 2 P U 3 P P Protection Type No program lock features. Further programming of the EPROM is disabled. Same as mode 2, also verify is disabled. Manufacturer ID: (00H) = E0H ( Indicates manufactured by HEI ) Device ID: (01H) = 16H ( Indicates GMS97C1051/L1051 ) U : unprogrammed, P : programmed EPROM Programming Modes Table 8. EPROM Programming Modes Mode Read Signature Program Code Data Verify Code Data RST P3.2/ PROG P3.3 P3.4 P3.5 P3.7 1 1 0 0 0 0 0 1 1 1 0 0 1 1 Vpp 1 1 Pgm encryption table Vpp 0 1 0 1 Pgm encryption bit1 Vpp 1 1 1 1 Pgm encryption bit Vpp 1 1 0 0 4. P3.2/ PROG receives 10 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100uS (10uS) and high for a minimum of 10uS. Notes:1. '0' = Valid low, '1' = Valid high for that pin. 2. Vpp = 12.75 V 0.25 V 3. Vcc = 5 V 10 % during programming and verification. 31 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Figure 5. Programming the EPROM Memory GMS97C1051 P3.0 5V GMS97C1051 VCC To Increment Address Counter PROG Figure 6. Verifying the EPROM Memory P1 P3.0 PGM DATA 5V PGM DATA P1 P3.2 P3.3 See EPROM Programming Modes Tables VCC To Increment Address Counter P3.2 5V P3.3 See EPROM Programming Modes Tables P3.4 P3.5 P3.4 P3.5 P3.7 P3.7 XTAL1 XTAL1 4~6MHz 4~6MHz XTAL2 RST Vpp RST XTAL2 GND 5V GND EPROM Programming and Verification Characteristics Table 9. EPROM Programming and Verification Characteristics Parameter Symbol Min Max Programming Supply Voltage VPP 12.5 13.0 V Programming Supply Current IPP 50 mA Oscillator Frequency 1 / tCLCL 4 6 MHz Address Setup to PROG Low tAVGL 48 tCLCL Data Setup to PROG Low tDVGL 48 tCLCL Data Hold after PROG tGHDX 48 tCLCL P3.4 ( ENABLE ) High to VPP tEHSH 48 tCLCL VPP Setup to PROG Low tSHGL 10 us VPP Hold After PROG tGHSL 10 us PROG Width tGLGH 90 PROG High to PROG Low tGHGL 10 P3.4 ( ENABLE ) Low to Data Valid tELQV Data Float after P3.4 ( ENABLE ) tEHQZ 110 Units us us 48 tCLCL 0 48 tCLCL TA= 21 to 27, VCC = 5.0 10% HYUNDAI MicroElectronics 32 8-Bit CMOS Microcontorller GMS97C1051/L1051 EPROM Programming and Verification Waveforms Figure 7. EPROM Programming and Verification Programming Verification VPP LOGIC 1 RST tSHGL (VPP) LOGIC 0 tGHSL tEHSH P3.2 (PROG) tGLGH tGHGL P3.4 tGHDX tDVGL (ENABLE) tELQV DATA IN PORT1 tEHQZ DATA OUT Address (N+1) tAVGL P3.0 Address (N) Figure 8. Programming Waveform 10 PULSES P3.2/ PROG 10 MIN 100 ±10 P3.2/ PROG 33 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Absolute Maximum Ratings NOTE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > Vcc or VIN < Vss ) the voltage on Vcc pins with respect to ground (Vss) must not exceed the values defined by the absolute maximum ratings. Ambient temperature under bias (TA.)....................... - 40 to + 85 to + 150 Storage temperature (TST) ..... -65 Voltage on VCC pin with respect to Ground(VSS).........-0.5V to +6.6V Voltage on any pin with respect to Ground(VSS)... -0.5V to VCC+0.5V Input Current on any pin during overload condition.........-10mA to +10mA Absolute sum of all input current during overload condition................... | 100 mA | HYUNDAI MicroElectronics 34 8-Bit CMOS Microcontorller GMS97C1051/L1051 D.C. Characteristics (5V Version) Vcc = 4.25V to 5.5V, Vss= 0V, O O TA= 0 C to 70 C for the GMS97C2051/C1051 Parameter Symbol Limit Values Min Max Unit Test Condition Input Low Voltage VIL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V IOL=10mA,Vcc=5V Output High Voltage (ports 1,3) VOH V IOH= -80uA, Vcc=5V±10% IOH= -30uA IOH= -12uA 2.4 0.75Vcc 0.9Vcc Logical 0 Input Current (ports 1,3) IIL -50 uA VIN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA VIN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<VIN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=5V Comparator Input VCM Vcc V CIO 10 pF Test Freq.=1MHz, TA=25 C Icc Iccidle Icc Iccidle Ipd 20 12 30 15 100 mA mA mA mA uA Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V Vcc=5.0V, P1.0&P1.1=0 or Vcc Vcc=5.0V, P1.0&P1.1=0 or Vcc 0 Common Mode Voltage Pin Capacitance Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Active mode, 24Mhz Idle mode, 24Mhz Power Down mode 35 O HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller D.C. Characteristics (3V Version) Vcc = 2.7V to 3.6V, Vss= 0V, O O TA= 0 C to 70 C for the GMS97L2051/L1051 Parameter Symbol Limit Values Min Max Unit Test Condition Input Low Voltage VIL -0.5 0.2Vcc-0.1 V Input High Voltage (Except XTAL1, RST) VIH 0.5Vcc-0.1 Vcc+0.5 V Input High Voltage (XTAL1, RST) VIH1 0.7Vcc Vcc+0.5 V Output Low Voltage (ports 1,3) VOL 0.45 V IOL=6mA,Vcc=2.7V Output High Voltage (ports 1,3) VOH V IOH= -30uA IOH= -12uA 0.75Vcc 0.9Vcc Logical 0 Input Current (ports 1,3) IIL -50 uA VIN=0.45V Logical 1-to-0 Transition Current (ports 1,3) ITL -750 uA VIN=2V Input Leakage Current (Port P1.0, P1.1) ILI ±1uA uA 0<VIN<Vcc Comparator Input Offset Voltage VOS 200 mV Vcc=3V Comparator Input VCM Vcc V CIO 10 pF Test Freq.=1MHz, TA=25 C Icc Iccidle Ipd 10 5 50 mA mA uA Vcc=3V Vcc=3V, P1.0&P1.1=0 or Vcc Vcc=3V, P1.0&P1.1=0 or Vcc 0 Common Mode Voltage Pin Capacitance Power supply current: Active mode, 12Mhz Idle mode, 12Mhz Power Down mode HYUNDAI MicroElectronics 36 O 8-Bit CMOS Microcontorller GMS97C1051/L1051 External Clock drive waveforms tCHCX tCHCX tCHCL tCLCH VCC - 0.5 V 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL External Clock Drive GMS97L2015/L1051 Parameter Min Max Min Max 1/tCLCL Oscillator Frequency 0 12 0 24 tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time - 20 - 20 ns tCHCL Fall Time - 20 - 20 ns AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.2VCC + 0.9V VLOAD + 0.1V VLOAD - 0.1V Timing Reference VLOAD 0.2VCC - 0.1V Note: 1. AC Inputs during testing are driven at VCC 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. MHz Float Waveforms(1) TEST POINTS 0.45V GMS97C2051/C1051 Units Symbol Points VOL + 0.1V VOL + 0.1V Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when a 100mV change from the loaded VOH/VOL level occurs. 37 HYUNDAI MicroElectronics GMS97C1051/L1051 8-Bit CMOS Microcontroller Package Dimension 20 PDIP unit : mm ( inch ) 20 SOP HYUNDAI MicroElectronics 38 8-Bit CMOS Microcontorller GMS97C1051/L1051 Ordering Information Speed ( MHz) Power Supply 12 2.7V to3.6V 4.25V to 5.5V 24 4.25V to 5.5V Ordering Code Package GMS97L1051 20 PDIP GMS97L1051-D 20 SOP GMS97C1051 20 PDIP GMS97C1051-D 20 SOP GMS97C1051-24 20 PDIP GMS97C1051-24D 20 SOP Operation Range Commercial to 70) (0 Package Type Wide, Plastic Dual Inline Package (PDIP) Wide, Plastic Gull Wing Small Outline (SOP) 20 PDIP 20 Lead, 0.300 20 SOP 20 Lead, 0.300 39 HYUNDAI MicroElectronics