INTEL M87C51FB

M87C51FB
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH
16 KBYTES USER PROGRAMMABLE EPROM
Military
M87C51FB Ð 3.5 MHz to 12 MHz, VCC e 5V
g 20%
M87C51FB-16 Ð 3.5 MHz to 16 MHz, VCC e
5V g 20%
Y
High Performance CHMOS EPROM
Y
Three 16-Bit Timer/Counters
Y
Programmable Counter Array with:
Ð High Speed Output,
Ð Compare/Capture,
Ð Pulse Width Modulator,
Ð Watchdog Timer capabilities
Y
Gullwing and J-lead Packages Also
Available
Y
32 Programmable I/O Lines
Y
7 Interrupt Sources
Y
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
Y
TTL and CMOS Compatible Logic
Levels
Y
Up/Down Timer/Counter
Y
Three Level Program Lock System
Y
16K On-Chip EPROM
Y
64K External Program Memory Space
Y
256 Bytes of On-Chip Data RAM
Y
64K External Data Memory Space
Y
Improved Quick Pulse Programming
Algorithm
Y
MCSÉ 51 Microcontroller Fully
Compatible Instruction Set
Y
Boolean Processor
Y
Y
ONCE (On-Circuit Emulation) Mode
Power Saving Idle and Power Down
Modes
Available in 40-pin CERDIP and
44-pin Leadless Chip Carrier Packages
Y
Y
Military Temperature Range:
b 55§ C to a 125§ C (TC)
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 16 Kbytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel M87C51FB is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS III-E technology. Being a member of the MCS 51 family of microcontrollers, the M87C51FB uses the
same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing
MCS 51 microcontroller family of products. The M87C51FB is an enhanced version of the M87C51. Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation,
High Speed I/O, and up/down counting capabilities such as motor control. It also has a more versatile serial
channel that facilitates multi-processor communications.
November 1994
Order Number: 271093-007
M87C51FB
271093 – 1
Figure 1. M87C51FB Block Diagram
2
M87C51FB
TTL inputs. Port 0 pins that have 1’s written to them
float, and in that state can be used as high-impedance inputs.
DIP
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IIL, on the data sheet) because of the internal pullups.
271093 – 2
LCC/GULLWING/J-LEAD
In addition, Port 1 serves the functions of the following special features of the M87C51FB:
Port Pin
Alternate Function
P1.0
T2 (External Count Input to Timer/
Counter 2)
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
271093 – 20
Figure 2. M87C51FB Pin Connections
PIN DESCRIPTIONS
VCC: Supply voltage.
VSS: Circuit ground.
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
CEX0 (External I/O for Compare/
Capture Module 0)
CEX1 (External I/O for Compare/
Capture Module 1)
CEX2 (External I/O for Compare/
Capture Module 2)
CEX3 (External I/O for Compare/
Capture Module 3)
CEX4 (External I/O for Compare/
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IIL, on the data sheet) because of the internal pullups.
3
M87C51FB
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @ DPTR). In this application it
uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @ Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IIL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the M8051 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. An internal pulldown resistor permits a poweron reset with only a capacitor connected to VCC.
When the M87C51FB is executing code from external Program Memory, PSEN is activated twice each
machine cycle, except that two PSEN activations
are skipped during each access to external Data
Memory.
EA/VPP: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH. Note, however, that if either of
the Program Lock bits are programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program
executions.
This pin also receives the programming supply voltage (VPP) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, ‘‘Oscillators for Microcontrollers.’’
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the M87C51FB.
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
4
271093 – 3
C1, C2 e 30 pF g 10 pF for Crystals
e 10 pF for Ceramic Resonators
Figure 3. Oscillator Connections
M87C51FB
With an external interrupt, INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that
puts the device into Power Down.
DESIGN CONSIDERATION
271093 – 4
# Ambient light is known to affect the internal RAM
Figure 4. External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
contents during operation. If the M87C51FB application requires the part to be run under ambient lighting, an opaque label should be placed
over the window to exclude light.
# When the Idle Mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
POWER DOWN MODE
To save even more power, a Power Down Mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down Mode is terminated.
On the M87C51FB either a hardware reset or an
external interrupt can cause an exit from Power
Down. Reset redefines all the SFRs but does not
change the on-chip RAM. An external interrupt allows both the SFRs and on-chip RAM to retain their
values.
To properly terminate Power Down the reset or external interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
M87C51FB without the M87C51FB having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the M87C51FB is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a normal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Mode
PORT0
PORT1
PORT2
PORT3
NOTE:
For more detailed information on the reduced power modes refer to Application Note AP-255, ‘‘Designing with the
M80C51BH’’.
5
M87C51FB
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Case Temperature Under Bias
ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 55§ C to a 125§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Voltage on EA/VPP Pin to VSS ÀÀÀÀÀÀÀ0V to a 13.0V
Voltage on Any Other Pin to VSS ÀÀ b 0.5V to a 6.5V
Maximum IOL Per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
Operating Conditions
Symbol
Description
Min
Max
Unit
TC
Case Temperature (Instant On)
b 55
a 125
§C
VCC
Digital Supply Voltage
4.0
6.0
V
fOSC
Oscillator Frequency
3.5
16
MHz
DC CHARACTERISTICS:
Symbol
(Over Specified Operating Conditions)
Parameter
VIL
Input Low Voltage
VIH
Input High Voltage
(Except XTAL1, RST)
VIH1
Input High Voltage (XTAL1, RST)
VOL
Output Low Voltage(5)
(Ports 1, 2, and 3)
VOL1
Min
Max
Unit
b 0.5
0.2 VCC b 0.1
V
0.2 VCC a 0.9
VCC a 0.5
V
0.7 VCC
VCC a 0.5
V
0.3
V
IOL e 100 mA (Note 1)
0.45
V
IOL e 1.6 mA (Note 1)
1.0
V
IOL e 3.5 mA (Notes 1, 4)
Output Low Voltage(5)
(Port 0, ALE, PSEN)
VOH
6
Output High Voltage
(Ports 1, 2, and 3)
Test Conditions
0.3
V
IOL e 200 mA (Note 1)
0.45
V
IOL e 3.2 mA (Note 1)
1.0
V
IOL e 7.0 mA (Note 1, 4)
VCC b 0.3
V
IOH e b 10 mA
VCC b 0.7
V
IOH e b 30 mA
VCC b 1.5
V
IOH e b 60 mA
M87C51FB
DC CHARACTERISTICS:
Symbol
VOH1
(Over Specified Operating Conditions) (Continued)
Parameter
Min
Output High Voltage
(Port 0 in External Bus Mode,
ALE, PSEN)
Max
Unit
Test Conditions
VCC b 0.3
V
IOH e b 200 mA (Note 2)
VCC b 0.7
V
IOH e b 3.2 mA
VCC b 1.5
V
IOH e b 7.0 mA (Note 4)
IIL
Logical 0 Input Current
(Ports 1, 2, and 3)
b 75
mA
VIN e 0.45V
ILI
Input leakage Current (Port 0)
g 10
mA
0.45V k VIN k VCC
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)
b 750
mA
VIN e 2V
RRST
RST Pulldown Resistor
225
KX
CIO
Pin Capacitance
10
pF
ICC
Power Supply Current:
Active Mode @ 16 MHz
Idle Mode @ 16 MHz
Power Down Mode @ 16 MHz
45
15
130
mA
mA
mA
40
@1
MHz, 25§ C
(Note 3)
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to
0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC b 0.3 specification when
the address lines are stabilizing.
3. See Figures 5–8 for load circuits. Minimum VCC for Power Down is 2V.
4. Care must be taken not to exceed the maximum allowable power dissipation.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
10mA
Maximum IOL per port pin:
Maximum IOL per 8-bit portÐ
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
71 mA
Maximum total IOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
271093 – 5
All other pins disconnected
TCLCH e TCHCL e 5 ns
Figure 5. ICC Load Circuit Active Mode
271093 – 6
All other pins disconnected
TCLCH e TCHCL e 5 ns
Figure 6. ICC Load Circuit Idle Mode
7
M87C51FB
271093 – 7
All other pins disconnected
Figure 7. ICC Load Circuit Power Down Mode.
VCC e 2.0V to 5.5V.
271093 – 8
Figure 8. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH e TCHCL e 5 ns.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
8
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
M87C51FB
AC CHARACTERISTICS
(Over Specified Operating Conditions)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz
Oscillator
Min
1/TCLCL
Max
16 MHz
Oscillator
Min
Max
Oscillator Frequency
87C51FB
87C51FB-16
Variable
Oscillator
Unit
Min
Max
3.5
3.5
12
16
MHz
TLHLL
ALE Pulse Width
127
85
2TCLCL b 40
ns
TAVLL
Address Valid to ALE Low
43
23
TCLCL b 40
ns
TLLAX
Address Hold After ALE Low
53
33
TCLCL b 30
TLLIV
ALE Low to
Valid Instruction In
TLLPL
ALE Low to PSEN Low
53
33
TCLCL b 30
TPLPH
PSEN Pulse Width
205
143
3TCLCL b 45
TPLIV
PSEN Low to
Valid Instruction In
TPXIX
Input Instruction Hold
After PSEN
TPXIZ
Input Instruction Float
After PSEN
59
38
TCLCL b 25
ns
TAVIV
Address to
Valid Instruction In
312
208
5TCLCL b 105
ns
TPLAZ
PSEN Low to Address Float
10
10
10
ns
234
150
145
0
83
0
RD Pulse Width
400
275
TWLWH
WR Pulse Width
400
275
6TCLCL b 100
TRLDV
RD Low to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
0
147.5
0
107
ns
0
TRLRH
ns
ns
3TCLCL b 105
6TCLCL b 100
252
ns
4TCLCL b 100
ns
ns
ns
ns
5TCLCL b 165
0
ns
ns
65
2TCLCL b 60
ns
ns
TLLDV
ALE Low to Valid Data In
517
350
8TCLCL b 150
TAVDV
Address to Valid Data In
585
398
9TCLCL b 165
ns
TLLWL
ALE Low to RD or WR Low
3TCLCL a 50
ns
200
300
138
238
3TCLCL b 50
TAVWL
Address Valid to WR Low
203
120
4TCLCL b 130
TQVWX
Data Valid before WR
33
13
TCLCL b 50
ns
TWHQX
Data Hold after WR
33
13
TCLCL b 50
ns
288
7TCLCL b 150
TQVWH
Data Valid to WR High
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE High
433
0
43
123
0
23
103
TCLCL b 40
ns
ns
0
ns
TCLCL a 40
ns
NOTE:
7. Case temperatures are ‘‘instant on’’.
9
M87C51FB
EXTERNAL PROGRAM MEMORY READ CYCLE
271093 – 9
EXTERNAL DATA MEMORY READ CYCLE
271093 – 10
EXTERNAL DATA MEMORY WRITE CYCLE
271093 – 11
10
M87C51FB
SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions:
Symbol
(Over Specified Operating Conditions)
Parameter
12 MHz
Oscillator
16 MHz
Oscillator
Min Max
Min
Max
Variable
Oscillator
Min
Units
Max
TXLXL
Serial Port Clock Cycle Time
1
0.75
12TCLCL
ms
TQVXH
Output Data Setup to Clock
Rising Edge
700
492
10TCLCL b 133
ns
TXHQX
Output Data Hold after
Clock Rising Edge
50
8
2TCLCL b 117
ns
TXHDX
Input Data Hold After Clock
Rising Edge
0
0
0
ns
TXHDV
Clock Rising Edge to Input
Data Valid
700
492
10TCLCL b 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
271093 – 12
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
87C51FB
87C51FB-16
3.5
3.5
12
16
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
EXTERNAL CLOCK DRIVE WAVEFORM
271093 – 13
11
M87C51FB
AC TESTING INPUT, OUTPUT WAVEFORMS
FLOAT WAVEFORMS
271093 – 15
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH t g 20 mA.
271093 – 14
AC Inputs during testing are driven at VCC b 0.5V for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’.
EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
RST
PSEN
ALE/
PROG
EA/
VPP
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
ß
12.75V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption
Array Address 0–3FH
H
L
ß
12.75V
L
H
H
L
H
Program Lock
Bits
Bit 1
H
L
ß
12.75V
H
H
H
H
H
Bit 2
H
L
ß
12.75V
H
H
H
L
L
Bit 3
H
L
ß
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
Mode
Read Signature Byte
NOTES:
‘‘1’’ e Valid high for that pin
‘‘0’’ e Valid low for that pin
‘‘VPP’’ e a 12.75V g 0.25V
DEFINITION OF TERMS
PROGRAMMING THE EPROM
ADDRESS LINES: P1.0–P1.7, P2.0–P2.5, P3.4 –
P3.5 respectively for A0–A15.
The part must be running with a 4 MHz to 6 MHz
oscillator. The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is applied to data lines. Control and program signals must
be held at the levels indicated in Table 2. Normally
EA/VPP is held at logic high until just before ALE/
PROG is to be pulsed. The EA/VPP is raised to VPP,
ALE/PROG is pulsed low and then EA/VPP is returned to a high (also refer to timing diagrams).
DATA LINES: P0.0–P0.7 for D0–D7.
CONTROL SIGNALS: RST, PSEN, P2.6, P2.7, P3.3,
P3.6, P3.7.
PROGRAM SIGNALS: ALE/PROG, EA/VPP.
NOTE:
Exceeding the VPP maximum for any amount of
time could damage the device permanently. The
VPP source must be well regulated and free of
glitches.
12
M87C51FB
271093 – 16
*See Table 2 for proper input on these pins.
Figure 9. Programming the EPROM
PROGRAMMING ALGORITHM
Refer to Table 2 and Figures 9 and 10 for address,
data, and control signals set up. To program the
M87C51FB the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP from VCC to 12.75V g 0.25V.
5. Pulse ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAM VERIFY
Program verify may be done after each byte that is
programmed, or after a block of bytes that is programmed. In either case a complete verify of the
entire array that has been programmed will ensure a
reliable programming of the M87C51FB.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled. Refer to the EPROM Program
Lock section in this data sheet.
5 Pulses
271093 – 17
Figure 10. Programming Signal’s Waveforms
13
M87C51FB
EPROM Program Lock
Reading the Signature Bytes
The two-level Program Lock system consists of two
Program Lock bits and a 32 byte Encryption Array
which are used to protect the program memory
against software piracy.
The signature bytes are read by the same procedure
as a normal verification of locations 030H, 031H and
60H. To read these bytes, follow the procedure for
EPROM verify, but activate the control lines provided in Table 2 for Read Signature Byte.
Location: 30H e 89H
31H e 58H
Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1’s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1’s), will return the code in it’s
original, unmodified form.
Program Lock Bits
Also included in the EPROM Program Lock scheme
are two Program Lock Bits which are programmed
as shown in Table 2.
Table 3 outlines the features of programming the
Lock Bits.
Erasing the EPROM also erases the Encryption Array and the Program Lock Bits, returning the part to
full functionality.
60H e FBH
Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 mW/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1’s state.
Table 3. Program Lock Bits and their Features
Program Lock Bits
LB1
LB2
14
Logic Enabled
U
U
No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)
P
U
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled.
P
P
Same as above, but Verify is also disabled
U
P
Reserved for Future Definition
M87C51FB
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA e 21§ C to 27§ C; VCC e 5V g 0.25V; VSS e 0V)
ADVANCED INFORMATIONÐCONTACT INTEL FOR DESIGN-IN INFORMATION
Symbol
Parameter
Min
Max
Units
VPP
Programming Supply Voltage
12.5
13.0
V
IPP
1/TCLCL
Programming Supply Current
Oscillator Frequency
4
TAVGL
Address Setup to PROG Low
48TCLCL
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to VPP
48TCLCL
TSHGL
VPP Setup to PROG Low
TGHSL
VPP Hold after PROG
10
TGLGH
PROG Width
90
50
mA
6
MHz
10
ms
ms
110
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
ms
48TCLCL
ms
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
271093 – 19
15