GSI GS880F36T-11

Preliminary
GS880F18/36T-10/11/11.5/12/14
100 Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
Features
• Flow through mode operation.
• 3.3V +10%/-5% Core power supply.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• 100-lead TQFP package
-10
-11
-11.5
-12
-14
10ns 11ns 11.5ns 12ns 14ns
Flow Through tKQ
2-1-1-1
tCycle 10ns 15ns 15ns 15ns 15ns
IDD 225mA 180mA 180mA 180mA 175mA
Functional Description
10ns - 14ns
3.3V VDD
3.3V & 2.5V I/O
broadest access to multiple vendor sources. Boards designed with FT
pin pads tied low may be stuffed with GSI’s Pipeline/Flow through
configurable Burst RAMS or any vendor’s Flow through or
configurable Burst SRAM. Bumps designed with the FT pin location
tied High or floating must employ a non-configurable Flow through
Burst RAM, like this RAM, to achieve Flow through functionality.
88018/32/36TByte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36T operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(VDDQ) pins are used to de-couple output noise from the internal
circuit.
Applications
The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin option
(pin 14 on TQFP). Board sites for Flow through Burst RAMS should
be designed with V SS connected to the FT pin location to ensure the
Rev: 1.03 3/2000
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Rev: 1.03 3/2000
2/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A18
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
NC
VSS
VDDQ
NC
NC
NC
A16
LBO
A5
A4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
NC
VDD
NC
VSS
DQB5
DQB6
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K
x
18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A15
NC
NC
NC
VDDQ
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
A6
A7
E1
E2
NC
NC
BB
BA
E3
VDD
VSS
GS880F18 100 Pin TQFP Pinout
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Rev: 1.03 3/2000
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NC
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
A16
LBO
A5
A4
VSS
DQ C6
DQ C5
DQ C4
DQ C3
VSS
VDDQ
DQ C2
DQ C1
NC
VDD
NC
VSS
DQ D1
DQ D2
VDDQ
VSS
DQ D3
DQ D4
DQ D5
DQ D6
VSS
VDDQ
DQ D7
DQ D8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K
x
32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A15
NC
DQ C8
DQ C7
VDDQ
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
A6
A7
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
GS880F32 100 Pin TQFP Pinout
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Rev: 1.03 3/2000
4/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
A16
LBO
A5
A4
VSS
DQ C6
DQ C5
DQ C4
DQ C3
VSS
VDDQ
DQ C2
DQ C1
NC
VDD
NC
VSS
DQ D1
DQ D2
VDDQ
VSS
DQ D3
DQ D4
DQ D5
DQ D6
VSS
VDDQ
DQ D7
DQ D8
DQ D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K
x
36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
A17
A10
A11
A12
A13
A14
A15
DQ C9
DQ C8
DQ C7
VDDQ
CK
GW
BW
G
ADSC
ADSP
ADV
A8
A9
A6
A7
E1
E2
BD
BC
BB
BA
E3
VDD
VSS
GS880F36 100 Pin TQFP Pinout
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
A2-17
I
Address Inputs
80
A18
I
Address Inputs
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
DQ A1-DQA8
DQ B1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins. (x32, x36 Version)
51, 80, 1, 30
DQA9, DQB9,
DQC9, DQD9
I/O
Data Input and Output pins.
51, 80, 1, 30
NC
-
No Connect (x32 Version)
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQ A1-DQA9
DQB1- DQB9
I/O
Data Input and Output pins.
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
NC
-
No Connect
16
DP
I
Parity Input. 1 = Even, 0 = Odd.
66
QE
O
Parity Error Out. Open Drain Output.
87
BW
I
Byte Write. Writes all enabled bytes. Active Low.
93, 94
B A, B B
I
Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
95, 96
BC, BD
I
Byte Write Enable for DQC, DQD Data I/O’s. Active Low. (x32, x36
Version)
95, 96
NC
-
No Connect (x18 Version)
89
CK
I
Clock Input Signal. Active High.
88
GW
I
Global Write Enable. Writes all bytes. Active Low.
98, 92
E1, E3
I
Chip Enable. Active Low.
97
E2
I
Chip Enable. Active High.
86
G
I
Output Enable. Active Low.
83
ADV
I
Burst address counter advance enable. Active Low.
84, 85
ADSP, ADSC
I
Address Strobe (Processor, Cache Controller). Active Low.
64
ZZ
I
Sleep Mode control. Active High.
31
LBO
I
Linear Burst Order mode. Active Low.
15, 41, 65, 91
VDD
I
Core power supply.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
VSS
I
I/O and Core Ground.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
I
Output driver power supply.
14, 16, 38, 39, 42, 66
NC
-
No Connect.
Rev: 1.03 3/2000
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
GS880F18/32/36 Block Diagram
Register
A0-An
D
Q
A0
A0
D0
Q0
A1
A1
D1
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
Register
D
36
Q
BB
4
Register
D
Q
D
Q
Q
D
D
Register
Register
Q
Register
BC
BD
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
0
G
ZZ
1
Power Down
DQx0-DQx9
Control
Note: Only x36 version shown for simplicity.
Rev: 1.03 3/2000
6/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Mode Pin Functions
Mode Name
Pin Name State
Burst Order Control
LBO
Power Down Control
ZZ
Function
L
Linear Burst
H or NC
Interleaved Burst
L or NC
Active
H
Standby, IDD = ISB
Note:
There is a pull up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Interleaved Burst Sequence
Linear Burst Sequence
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
3rd address
10
11
4th address
11
00
A[1:0]
A[1:0]
A[1:0]
A[1:0]
1st address
00
01
10
11
00
2nd address
01
00
11
10
00
01
3rd address
10
11
00
01
01
10
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
GW
BW
BA
BB
BC
BD
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Rev: 1.03 3/2000
7/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key5
E1
Deselect Cycle, Power
Down
None
X
H
X
X
Deselect Cycle, Power Down
None
X
L
F
Deselect Cycle, Power
Down
None
X
L
Read Cycle, Begin Burst
External
R
Read Cycle, Begin Burst
External
Write Cycle, Begin Burst
E22
ADV
W3
DQ4
L
X
X
High-Z
L
X
X
X
High-Z
F
H
L
X
X
High-Z
L
T
L
X
X
X
Q
R
L
T
H
L
X
F
Q
External
W
L
T
H
L
X
T
D
Read Cycle, Continue Burst
Next
CR
X
X
H
H
L
F
Q
Read Cycle, Continue Burst
Next
CR
H
X
X
H
L
F
Q
Write Cycle, Continue Burst
Next
CW
X
X
H
H
L
T
D
Write Cycle, Continue Burst
Next
CW
H
X
X
H
L
T
D
Read Cycle, Suspend Burst
Current
X
X
H
H
H
F
Q
Read Cycle, Suspend Burst
Current
H
X
X
H
H
F
Q
Write Cycle, Suspend Burst
Current
X
X
H
H
H
T
D
Write Cycle, Suspend Burst
Current
H
X
X
H
H
T
D
(x36only)
ADSP ADSC
Note:
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above).
5.
6.
7.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to
accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items
above.
Rev: 1.03 3/2000
8/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Simplified State Diagram
X
Deselect
W
R
Simple Burst Synchronous Operation
Simple Synchronous Operation
W
X
R
R
First Write
CW
First Read
CR
W
X
CR
R
R
X
Burst Write
Burst Read
X
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1E2) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.03 3/2000
9/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Simplified State Diagram with G
X
Deselect
W
R
W
X
R
R
First Write
CR
CW
W
CW
W
X
First Read
X
CR
R
Burst Write
R
CR
CW
W
Burst Read
X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 3/2000
10/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
-0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
-0.5 to VDD
V
VCK
Voltage on Clock Input Pin
-0.5 to 6
V
VI/O
Voltage on I/O Pins
-0.5 to VDDQ+0.5 (≤ 4.6 V
max.)
V
VIN
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/- 20
mA
IOUT
Output Current on Any I/O Pin
+/- 20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
-55 to 125
oC
TBIAS
Temperature Under Bias
-55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
VDD
V
1
Input High Voltage
VIH
1.7
---
VDD+0.3
V
2
Input Low Voltage
VIL
-0.3
---
0.8
V
2
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
3
Ambient Temperature (Industrial Range Versions)
TA
-40
25
85
°C
3
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < V DD+2V with a pulse width not to exceed 20% tKC.
Rev: 1.03 3/2000
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
50%
VDD
VSS-2.0V
20% tKC
VIL
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
24
°C/W
1,2
RΘJC
9
°C/W
3
Junction to Case (TOP)
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
Parameter
Conditions
Input high level
2.3V
Input low level
0.2V
Input slew rate
1V/ns
Input reference level
1.25V
Output reference level
1.25V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Rev: 1.03 3/2000
12/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Output Load 2
Output Load 1
DQ
2.5V
225Ω
DQ
30pF*
50Ω
5pF*
VT=1.25V
225Ω
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symb
ol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
-1uA
1uA
ZZ Input Current
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
-1uA
-1uA
1uA
uA
Mode Pin Input Current
IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
-uA
-1uA
1uA
1uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDD
-1uA
1uA
Output High Voltage
VOH
IOH = - mA, VDDQ=2.375V
1.7V
Output High Voltage
VOH
IOH = - mA, VDDQ=3.135V
2.4V
Output Low Voltage
VOL
IOL = mA
Rev: 1.03 3/2000
0.4V
13/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
-0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
-0.5 to VDD
V
VCK
Voltage on Clock Input Pin
-0.5 to 6
V
VI/O
Voltage on I/O Pins
-0.5 to VDDQ+0.5 (≤ 4.6 V
max.)
V
VIN
Voltage on Other Input Pins
-0.5 to VDD+0.5 (≤ 4.6 V max.)
V
IIN
Input Current on Any Pin
+/- 20
mA
IOUT
Output Current on Any I/O Pin
+/- 20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
-55 to 125
oC
TBIAS
Temperature Under Bias
-55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
VDD
V
1
Input High Voltage
VIH
1.7
---
VDD+0.3
V
2
Input Low Voltage
VIL
-0.3
---
0.8
V
2
Ambient Temperature (Commercial Range Versions)
TA
0
25
70
°C
3
Ambient Temperature (Industrial Range Versions)
TA
-40
25
85
°C
3
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O)
and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < V DD+2V with a pulse width not to exceed 20% tKC.
Rev: 1.03 3/2000
14/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
VSS
50%
50%
VDD
VSS-2.0V
20% tKC
VIL
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
Max
Unit
Notes
Junction to Ambient (at 200 lfm)
single
RΘJA
40
°C/W
1,2
Junction to Ambient (at 200 lfm)
four
RΘJA
24
°C/W
1,2
RΘJC
9
°C/W
3
Junction to Case (TOP)
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
AC Test Conditions
Parameter
Conditions
Input high level
2.3V
Input low level
0.2V
Input slew rate
1V/ns
Input reference level
1.25V
Output reference level
1.25V
Output load
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.
4. Device is deselected as defined by the Truth Table.
Rev: 1.03 3/2000
15/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Output Load 2
Output Load 1
DQ
2.5V
225Ω
DQ
30pF*
50Ω
5pF*
VT=1.25V
225Ω
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symb
ol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
-1uA
1uA
ZZ Input Current
IINZZ
VDD ≥ VIN ≥ VIH
0V ≤ VIN ≤ VIH
-1uA
-1uA
1uA
uA
Mode Pin Input Current
IINM
VDD ≥ VIN ≥ VIL
0V ≤ VIN ≤ VIL
-uA
-1uA
1uA
1uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDD
-1uA
1uA
Output High Voltage
VOH
IOH = - mA, VDDQ=2.375V
1.7V
Output High Voltage
VOH
IOH = - mA, VDDQ=3.135V
2.4V
Output Low Voltage
VOL
IOL = mA
0.4V
Operating Currents
Parameter Test Conditions Symbol
-10
0 to
70°C
-11
-40 to
85°C
0 to
70°C
-40 to
85°C
-11.5
0 to
70°C
-40 to
85°C
-12
0 to
70°C
-40 to
85°C
-14
0 to
70°C
-40 to
85°C
Device Selected;
IDD
Operating All other inputs
225mA 235mA 180mA 190mA 180mA 190mA 180mA 190mA 175mA 185mA
≥V
or
≤
V
Flow-Thru
Current
IH
IL
Output open
Standby
Current
ZZ ≥ VDD - 0.2V
ISB
Flow-Thru
30mA
40mA
30mA
40mA
30mA
40mA
30mA
40mA
30mA
40mA
Deselect
Current
Device Deselected;
IDD
All other inputs
Flow-Thru
≥ VIH or ≤ VIL
80mA
90mA
65mA
75mA
65mA
75mA
65mA
75mA
55
65
Rev: 1.03 3/2000
16/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
AC Electrical Characteristics
FlowThru
Parameter
Symbol
Clock Cycle Time
-10
-11
-11.5
-12
-14
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKC
10.0
---
10.0
---
15.0
---
15.0
---
15.0
---
ns
Clock to Output Valid
tKQ
---
8.0
---
10.0
---
11.0
---
11.5
---
12.0
ns
Clock to Output Invalid
tKQX
3.0
---
3.0
---
3.0
---
3.0
---
3.0
---
ns
Clock to Output in Low-Z
1
tLZ
3.0
---
3.0
---
3.0
---
3.0
---
3.0
---
ns
Clock HIGH Time
tKH
1.3
---
1.5
---
1.7
---
1.7
---
2
---
ns
Clock LOW Time
tKL
1.5
---
1.7
---
2
---
2
---
2.2
---
ns
Clock to Output in High-Z
tHZ1
1.5
3.2
1.5
3.8
1.5
4.0
1.5
4.2
1.5
4.5
ns
G to Output Valid
tOE
---
3.2
---
3.8
---
4.0
---
4.2
---
4.5
ns
G to output in Low-Z
tOLZ1
0
---
0
---
0
---
0
---
0
---
ns
G to output in High-Z
tOHZ1
---
3.2
---
3.8
---
4.0
---
4.2
---
4.5
ns
Setup time
tS
1.5
---
1.5
---
1.5
---
2.0
---
2.0
---
ns
Hold time
tH
0.5
---
0.5
---
0.5
---
0.5
---
0.5
---
ns
ZZ setup time
tZZS2
5
---
5
---
5
---
5
---
5
---
ns
ZZ hold time
tZZH2
1
---
1
---
1
---
1
---
1
---
ns
ZZ recovery
tZZR
20
---
20
---
20
---
20
---
20
---
ns
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.03 3/2000
17/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated write
ADSC
tS tH
ADV
tS tH
A0-An
ADV must be inactive for ADSP Write
WR2
WR1
WR3
tS tH
GW
tS tH
BW
tS tH
BA - BD
WR1
WR1
WR2
tS tH
WR3
WR3
E1 masks ADSP
E1
tS tH
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS tH
DQA - DQD
Rev: 1.03 3/2000
Hi-Z
D1A
Write specified byte for 2A and all bytes for 2B, 2c& 2D
D2A
D2B
D2C
D2D
D3A
18/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Flow Through Read-Write Cycle Timing
Single Write
Single Read
Burst Read
CK
tS tH
tKC
tKH tKL
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
WR1
RD2
ADSC
tS tH
ADV
tS tH
A0-An
RD1
tS tH
GW
tS tH
tS
BW
tS
BA - BD
tH
WR1
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
tS tH
Deselected with E3
E3
tOE
tOHZ
G
tS
tKQ
DQA - DQD
Hi-Z
Q1A
tH
D1A
Q2A
Q2B
Q2c
Q2D
Q2A
Burst wrap around to it’s initial state
Rev: 1.03 3/2000
19/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS tH
tKC
ADSP is blocked by E inactive
ADSP
tS tH
ADSC initiated read
ADSC
tS tH
Suspend Burst
Suspend Burst
ADV
tS tH
A0-An
RD1
RD2
RD3
tS
tH
tS
tH
GW
BW
BA - BD
tS tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP or ADSC
Deselected with E 2
E2
tS tH
E3
tOE
tOHZ
G
tKQX
tOLZ
DQA-DQD
Q1A
Hi-Z
Q2A
tKQX
Q2B
Q2C
Q2D
Q3A
tLZ
tHZ
tKQ
Rev: 1.03 3/2000
20/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
CK
tS tH
tKC
tKH tKL
ADSP
ADSC
tZZS
ZZ
~
~ ~ ~
~ ~
~~
~ ~
Sleep Mode Timing Diagram
tZZH
tZZR
Snooze
Rev: 1.03 3/2000
21/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
20.0
VDDQ
I Out (mA)
I Out
0.0
VOut
-20.0
VSS
-40.0
-60.0
Pull Up Drivers
-80.0
-100.0
-120.0
-140.0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
Rev: 1.03 3/2000
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
22/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
3.6V PU HD
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
TQFP Package Drawing
Description
Min.
Nom.
Max
A1
Standoff
0.05
0.10
0.15
A2
Body Thickness
1.35
1.40
1.45
b
Lead Width
0.20
0.30
0.40
c
Lead Thickness
0.09
D
Terminal Dimension
21.9
22.0
22.1
D1
Package Body
19.9
20.0
20.1
E
Terminal Dimension
15.9
16.0
16.1
E1
Package Body
13.9
14.0
14.1
e
Lead Pitch
L
Foot Length
L1
Lead Length
Y
Coplanarity
θ
Lead Angle
c
0.20
e
D
0.60
D1
0.65
0.45
L1
θ
Pin 1
Symbol
L
b
0.75
1.00
0.10
0°
7°
A1
A2
Y
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
E1
E
BPR 1999.05.18
Rev: 1.03 3/2000
23/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Ordering Information for GSI Synchronous Burst RAMs
Org
Part Number1
Type
Package
Speed2
(Mhz/ns)
TA3
512K x 18
GS880F18T-10
Flow Through
TQFP
10
C
512K x 18
GS880F18T-11
Flow Through
TQFP
11
C
512K x 18
GS880F18T-11.5
Flow Through
TQFP
11.5
C
512K x 18
GS880F18T-12
Flow Through
TQFP
12
C
512K x 18
GS880F18T-14
Flow Through
TQFP
14
C
256K x 32
GS880F32T-10
Flow Through
TQFP
10
C
256K x 32
GS880F32T-11
Flow Through
TQFP
11
C
256K x 32
GS880F32T--11.5
Flow Through
TQFP
11.5
C
256K x 32
GS880F32T-12
Flow Through
TQFP
12
C
256K x 32
GS880F32T-14
Flow Through
TQFP
14
C
256K x 36
GS880F36T-10
Flow Through
TQFP
10
C
256K x 36
GS880F36T-11
Flow Through
TQFP
11
C
256K x 36
GS880F36T--11.5
Flow Through
TQFP
11.5
C
256K x 36
GS880F36T-12
Flow Through
TQFP
12
C
256K x 36
GS880F36T-14
Flow Through
TQFP
14
C
512K x 18
GS880F18T-10I
Flow Through
TQFP
10
I
512K x 18
GS880F18T-11I
Flow Through
TQFP
11
I
512K x 18
GS880F18T--11.5I
Flow Through
TQFP
11.5
I
512K x 18
GS880F18T-12I
Flow Through
TQFP
12
I
512K x 18
GS880F18T-14I
Flow Through
TQFP
14
I
256K x 32
GS880F32T-10
Flow Through
TQFP
10
I
256K x 32
GS880F32T-11
Flow Through
TQFP
11
I
256K x 32
GS880F32T--11.5
Flow Through
TQFP
11.5
I
256K x 32
GS880F32T-12
Flow Through
TQFP
12
I
256K x 32
GS880F32T-14
Flow Through
TQFP
14
I
256K x 36
GS880F36T-10I
Flow Through
TQFP
10
I
256K x 36
GS880F36T-11I
Flow Through
TQFP
11
I
256K x 36
GS880F36T--11.5I
Flow Through
TQFP
11.5
I
256K x 36
GS880F36T-12I
Flow Through
TQFP
12
I
256K x 36
GS880F36T-14I
Flow Through
TQFP
14
I
Status
Not Available
Not Available
Not Available
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880LF18TT.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.03 3/2000
24/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N
Preliminary
GS880F18/36T-10/11/11.5/12/14
Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
Content
• First Release of 880 F.
GS880F18/36T1.00
K880F18/36T1.02 1/2000L
Content
• Changed Flow Through Read-Write Cycle Timing Diagram for accuracy.
• Changed order of TQFP Address Inputs to match pinout.
• Changed order of TQFP DATA Input and Output pins to match pinout.
• New GSI Logo.
GS880F1836T Rev. 1.02 1/2000L;
GS880F1836T Rev. 1.03 3/2000N
Content
• Changed all speed bin information (headings, references, tables, ordering
info..) to reflect 14 -10Mhz
GS880F18/361.00 11/1999J
Rev: 1.03 3/2000
25/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
N