HD74AC138/HD74ACT138 1-of-8 Decoder/Demultiplexer Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a 1-of-32 decoder using four HD74AC138/HD74ACT138 devices and one inverter. Features • • • • • Demultiplexing Capability Multiple Input Enable for Easy Expansion Active LOW Mutually Exclusive Outputs Outputs Source/Sink 24 mA HD74ACT138 has TTL-Compatible Inputs HD74AC138/HD74ACT138 Pin Arrangement A0 1 16 VCC A1 2 15 O0 A2 3 14 O1 E1 4 13 O2 E2 5 12 O3 E3 6 11 O4 O7 7 10 O5 GND 8 9 O6 (Top view) Logic Symbol A0 A1 A2 E1 E2 E3 O0 O1 O2 O3 O4 O5 O6 O7 Pin Names A0 to A2 E1 to E 2 E3 O0 to O 7 2 Address Inputs Enable Inputs Enable Input Outputs HD74AC138/HD74ACT138 Functional Description The HD74AC138/HD74ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0 to O7). The HD74AC138/HD74ACT138 features three Enable inputs, two active-Low (E1, E2) and one active-High (E3). All outputs will be High unless E1 and E2 are Low and E 3 is High. This multiple enabled function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four HD74AC138/HD74ACT138 devices and one inverter (See Figure a). The HD74AC138/HD74ACT138 can be used as an 8-output demultiplexer by using one of the active Low Enable inputs as the data input and the other Enable inputs as strobes. The Enables inputs which are not used must be permanently tied to their appropriate active-High or active-Low state. Truth Table Inputs Outputs E1 E2 E3 A0 A1 A2 O0 O1 O2 O3 O4 O5 O6 O7 H X X X X X H H H H H H H H X H X X X X H H H H H H H H X X L X X X H H H H H H H H L L H L L L L H H H H H H H L L H H L L H L H H H H H H L L H L H L H H L H H H H H L L H H H L H H H L H H H H L L H L L H H H H H L H H H L L H H L H H H H H H L H H L L H L H H H H H H H H L H L L H H H H H H H H H H H L H : L : X : High Voltage Level Low Voltage Level Immaterial 3 HD74AC138/HD74ACT138 Logic Diagram A2 O7 A1 E1 E2 E3 A0 O6 O5 O4 O3 O2 O1 O0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure a: Expansion of 1-of-32 Decoding A0 A1 A2 ’04 A3 A4 H 123 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 O0 4 123 123 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 123 A0 A1 A2 E O0 O1 O2 O3 O4 O5 O6 O7 O31 HD74AC138/HD74ACT138 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum ICC/input (HD74ACT138) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V Ta = Worst case AC Characteristics: HD74AC138 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay t PLH 3.3 1.0 8.5 13.0 1.0 15.0 ns 5.0 1.0 6.5 9.5 1.0 10.5 3.3 1.0 8.0 12.5 1.0 14.0 5.0 1.0 6.0 9.0 1.0 10.5 3.3 1.0 11.0 15.0 1.0 16.0 5.0 1.0 8.0 11.0 1.0 12.0 3.3 1.0 9.5 13.5 1.0 15.0 5.0 1.0 7.0 9.5 1.0 10.5 3.3 1.0 11.0 15.5 1.0 16.5 5.0 1.0 8.0 11.0 1.0 12.5 3.3 1.0 8.5 13.0 1.0 14.0 5.0 1.0 6.0 8.0 1.0 9.5 An to On Propagation delay t PHL An to On Propagation delay t PLH E1 or E 2 to On Propagation delay t PHL E1 or E 2 to On Propagation delay t PLH E3 to On Propagation delay E3 to On Note: t PHL ns ns ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC138/HD74ACT138 AC Characteristics: HD74ACT138 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Propagation delay An to On t PLH 5.0 1.0 7.0 10.5 1.0 11.5 ns Propagation delay An to On t PHL 5.0 1.0 6.5 10.5 1.0 11.5 ns Propagation delay E1 or E 2 to On t PLH 5.0 1.0 8.0 11.5 1.0 12.5 ns Propagation delay E1 or E 2 to On t PHL 5.0 1.0 7.5 11.5 1.0 12.5 ns Propagation delay E3 to On t PLH 5.0 1.0 8.0 12.0 1.0 13.0 ns Propagation delay E3 to On t PHL 5.0 1.0 6.5 10.5 1.0 11.5 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 60.0 pF VCC = 5.0 V 6 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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