HITTITE HMCAD1040-80

HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Features
General Description
• 10-bit Resolution
The HMCAD1040-80 is a high performance low
power dual analog-to-digital converter (ADC). The
ADC employs internal reference circuitry, a CMOS
control interface, CMOS output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
• 65/80 MSPS Maximum Sampling Rate
• Ultra-Low Power Dissipation: 65/78 mW
• 61.6 dB SNR @ 8 MHz
• Internal Reference Circuitry
• 1.8 V Core Supply Voltage
• 1.7 – 3.6 V I/O Supply Voltage
• Parallel CMOS Output
A / D Converters - SMT
0
• 9 x 9 mm, 64-Pin QFN (LP9E) Package
• Dual Channel
Typical Applications
• Medical Imaging
• Portable Test Equipment
• Digital Oscilloscopes
• IF Communication
Several idle modes with fast startup times exist. Each
channel can be independently powered down and
the entire chip can either be put in Standby Mode or
Power Down mode. The different modes are optimized
to allow the user to select the mode resulting in
the lowest possible energy consumption during idle
mode and startup.
The HMCAD1040-80 has a highly linear THA optimized for frequencies up to Nyquist. The differential
clock interface is optimized for low jitter clock sources
and supports LVDS, LVPECL, sine wave and CMOS
clock inputs.
Pin compatible with HMCAD1040-40, HMCAD1050-40
and HMCAD1050-80.
Functional Diagram
Figure 1.Functional Block Diagram
0-1
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Electrical Specifications
DC Electrical Specifications
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, 65/80 MSPS clock, 50% clock duty cycle, -1 dBFS 8 MHz input signal, unless otherwise
noted
Parameter
Condition
Min.
Typ.
Max.
Units
±6
%FS
DC Accuracy
No missing codes
Offset error
Gain error
Guaranteed
Mid-scale offset
1
Full scale range deviation from typical
LSB
Gain matching between channels. ± 3 sigma value
at worst case conditions
± 0.5
DNL
Differential nonlinearity
± 0.15
LSB
INL
Integral nonlinearity
± 0.2
LSB
Common mode voltage output
VAVDD/2
V
Gain matching
VCM
%FS
0
Input common mode
Full scale range
Input capacitance
Bandwidth
Analog input common mode voltage
VCM -0.1
Differential input voltage range
VCM +0.2
2.0
Differential input capacitance
V
Vpp
2
pF
Input Bandwidth
500
MHz
Core Supply Voltage
Supply voltage to all 1.8V domain pins. See Pin
Configuration and Description
1.7
1.8
2.0
V
I/O Supply Voltage
Output driver supply voltage (OVDD). Should
be higher than or equal to Core Supply Voltage
(VOVDD ≥ VDVDD)
1.7
2.5
3.6
V
Power Supply
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
A / D Converters - SMT
Analog Input
0-2
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
AC Electrical Specifications - 65 MSPS
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, 65/80 MSPS clock, 50% clock duty cycle, -1 dBFS 8 MHz input signal, unless otherwise
noted
Parameter
Performance
SNR
SNDR
A / D Converters - SMT
0
SFDR
HD2
HD3
ENOB
Crosstalk
Power Supply
Analog supply current
Digital supply current
Output driver supply
Output driver supply
Condition
Signal to Noise Ratio
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Signal to Noise and Distortion Ratio
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Spurious Free Dynamic Range
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Second order Harmonic Distortion
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Third order Harmonic Distortion
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Effective number of Bits
FIN = 8 MHz
FIN = 20 MHz
FIN =~ FS/2
FIN = 40 MHz
Signal crosstalk between channels,
FIN1=8MHz, FIN0=9.9MHz
Min.
Typ.
60
61.6
61.6
61.5
61.3
dBFS
dBFS
dBFS
dBFS
60
61.6
61.6
60.4
61.1
dBFS
dBFS
dBFS
dBFS
70
77
77
70
75
dBc
dBc
dBc
dBc
-80
-90
-95
-85
-90
dBc
dBc
dBc
dBc
-70
-77
-77
-70
-75
dBc
dBc
dBc
dBc
9.7
9.9
9.9
9.7
9.9
bits
bits
bits
bits
-97
dB
22
5.2
mA
mA
7.9
mA
6.4
mA
39.6
mW
25.4
mW
65
mW
9.3
38.2
15.7
µW
mW
mW
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1 MHz, CK_EXT enabled
2.5V output driver supply, sine wave input,
FIN = 1 MHz, CK_EXT disabled
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode 1
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
0-3
OVDD = 2.5V, 5pF load on output bits,
FIN = 1 MHz, CK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1 MHz, CK_EXT disabled
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
Max.
65
3
Units
MSPS
MSPS
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
AC Electrical Specifications - 80 MSPS
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, 65/80 MSPS clock, 50% clock duty cycle, -1 dBFS 8 MHz input signal, unless otherwise
noted
SNDR
SFDR
HD2
HD3
ENOB
Crosstalk
Power Supply
Analog supply current
Digital supply current
Output driver supply
Output driver supply
Condition
Min.
Typ.
60
61.6
61.2
61.3
61.3
dBFS
dBFS
dBFS
dBFS
60
61.3
60.7
61
59
dBFS
dBFS
dBFS
dBFS
70
75
75
dBc
dBc
FIN = 30 MHz
75
dBc
FIN =~ FS/2
Second order Harmonic Distortion
FIN = 8 MHz
FIN = 20 MHz
FIN = 30 MHz
FIN =~ FS/2
Third order Harmonic Distortion
FIN = 8 MHz
FIN = 20 MHz
FIN = 30 MHz
FIN =~ FS/2
Effective number of Bits
FIN = 8 MHz
FIN = 20 MHz
FIN = 30 MHz
FIN =~ FS/2
Signal crosstalk between channels,
FIN1=8MHz, FIN0=9.9MHz
65
dBc
-80
-90
-95
-90
-80
dBc
dBc
dBc
dBc
-70
-75
-75
-75
-65
dBc
dBc
dBc
dBc
9.7
9.9
9.8
9.8
9.5
bits
bits
bits
bits
-95
dB
26.5
6.1
mA
mA
9.5
mA
7.6
mA
47.7
mW
30
mW
77.7
mW
9.1
46.1
18.3
µW
mW
mW
Signal to Noise Ratio
FIN = 8 MHz
FIN = 20 MHz
FIN = 30 MHz
FIN =~ FS/2
Signal to Noise and Distortion Ratio
FIN = 8 MHz
FIN = 20 MHz
FIN = 30 MHz
FIN =~ FS/2
Spurious Free Dynamic Range
FIN = 8 MHz
FIN = 20 MHz
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1 MHz, CK_EXT enabled
2.5V output driver supply, sine wave input,
FIN = 1 MHz, CK_EXT disabled
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode 1
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
OVDD = 2.5V, 5pF load on output bits,
FIN = 1 MHz, CK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1 MHz, CK_EXT disabled
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
Max.
80
3
Units
0
A / D Converters - SMT
Parameter
Performance
SNR
MSPS
MSPS
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0-4
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Digital & Timing Specifications
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, Conversion Rate: Max specified, 50% clock duty cycle, -1dBFS input signal,
5 pF capacitive load on data outputs, unless otherwise noted
Parameter
Condition
Min
Typ
Max
Unit
80
% high
Clock Inputs
Duty Cycle
20
Compliance
Input range
Differential input swing
0.4
Vpp
Input range
Differential input swing, sine wave clock input
1.6
Vpp
Keep voltages within ground and voltage of OVDD
0.3
Input common
mode voltage
A / D Converters - SMT
0
CMOS, LVDS, LVPECL, Sine Wave
Input capacitance
Differential
VOVDD -0.3
2
V
pF
Timing
TPD
Start up time from Power Down Mode to Active Mode
900
TSLP
Start up time from Sleep Mode to Active Mode
20
TOVR
Out of range recovery time
TAP
1
clock cycles
clock cycles
clock cycles
Aperture Delay
0.8
ns
Єrms
Aperture jitter
< 0.5
ps
TLAT
Pipeline Delay
12
clock cycles
TD
Output delay (see timing diagram). 5pF load on output bits
3
10
ns
TDC
Output delay relative to CK_EXT (see timing diagram)
1
6
ns
Logic Inputs
VHI
High Level Input Voltage. VOVDD ≥ 3.0V
2
V
VHI
High Level Input Voltage. VOVDD = 1.7V – 3.0V
0.8 ·VOVDD
V
VLI
Low Level Input Voltage. VOVDD ≥ 3.0V
0
0.8
VLI
Low Level Input Voltage. VOVDD = 1.7V – 3.0V
0
0.2 ·VOVDD
V
IHI
High Level Input leakage Current
±10
µA
ILI
Low Level Input leakage Current
±10
µA
CI
Input Capacitance
3
V
pF
Logic Outputs
VHO
High Level Output Voltage
VLO
Low Level Output Voltage
VOVDD -0.1
0.1
V
V
CL
Max capacitive load. Post-driver supply voltage equal to
pre-driver supply voltage VOVDD = VOCVDD
5
pF
CL
Max capacitive load. Post-driver supply voltage above 2.25V [1]
10
pF
[1] The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep
dynamic currents and resulting switching noise at a minimum
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Timing Diagram
Figure 2.Timing Diagram
Table 1. Absolute Maximum Ratings
Pin
Pin
Pin
AVDD
AVSS
-0.3V to +2.3V
DVDD
DVSS
-0.3V to +2.3V
AVSS, DVSSCK, DVSS, OVSS
DVSS
-0.3V to +0.3V
OVDD
OVSS
-0.3V to +3.9V
IPx, INx, analog inputs and outputs
AVSS
-0.3V to +2.3V
Digital outputs
OVSS
-0.3V to +3.9V
CKP, CKN
Digital Inputs
DVSSCK
-0.3V to +3.9V
OVSS
-0.3V to +3.9V
Operating temperature
-40 to +85 ºC
Storage temperature
-60 to +150 ºC
Soldering Profile Qualification
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
A / D Converters - SMT
0
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in
the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
J-STD-020
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0-6
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Pin Configuration and Description
A / D Converters - SMT
0
Figure 3.Package Drawing, QFN 64-Pin
0-7
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Table 2. Pin Descriptions
Function
Description
1, 18, 23
DVDD
Digital and I/O-ring pre driver supply voltage, 1.8V
2
CM_EXT
Common Mode voltage output
3, 9, 12
AVDD
Analog supply voltage, 1.8V
4, 5, 8
AVSS
Analog ground
6, 7
IP0, IN0
Analog input Channel 0 (non-inverting, inverting)
10, 11
IP1, IN1
Analog input Channel 1 (non-inverting, inverting)
13
DVSSCK
Clock circuitry ground
14
DVDDCK
Clock circuitry supply voltage, 1.8V
15
CKP
Clock input, non-inverting (Format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
16
CKN
Clock input, inverting. For CMOS input on CKP, connect CKN to ground.
17, 64
DVSS
Digital circuitry ground
19
CK_EXT_EN
CK_EXT signal enabled when low (zero). Tristate when high.
20
DFRMT
Data format selection. 0: Offset Binary, 1: Two's Complement
21
PD_N
Full chip Power Down mode when Low. All digital outputs reset to zero.
After chip power up always apply Power Down mode before using Active
Mode to reset chip.
22
OE_N_1
Output Enable Channel 0. Tristate when high
24, 41, 58
OVDD
I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
25, 40, 57
OVSS
Ground for I/O ring
26, 27, 28
NC
27
NC
28
NC
29
D1_0
Output Data Channel 1 (LSB)
30
D1_1
Output Data Channel 1
31
D1_2
Output Data Channel 1
32
D1_3
Output Data Channel 1
33
D1_4
Output Data Channel 1
34
D1_5
Output Data Channel 1
35
D1_6
Output Data Channel 1
36
D1_7
Output Data Channel 1
37
D1_8
Output Data Channel 1
38
D1_9
Output Data Channel 1 (MSB)
39
ORNG_1
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels
42
CK_EXT
43
NC
44
NC
45
NC
46
D0_0
Output Data Channel 0 (LSB)
47
D0_1
Output Data Channel 0
48
D0_2
Output Data Channel 0
49
D0_3
Output Data Channel 0
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0
A / D Converters - SMT
Pin Number
0-8
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Table 2. Pin Descriptions
Pin Number
Description
50
D0_4
Output Data Channel 0
51
D0_5
Output Data Channel 0
52
D0_6
Output Data Channel 0
53
D0_7
Output Data Channel 0
54
D0_8
Output Data Channel 0
55
D0_9
Output Data Channel 0 (MSB)
56
ORNG_0
Out of Range flag Channel 0. High when input signal is out of range
59
OE_N_0
Output Enable Channel 0. Tristate when high
60, 61
CM_EXTBC_1, CM_
EXTBC_0
Bias control bits for the buffer driving pin CM_EXT
00: OFF
01: 50uA
10: 500uA
11: 1mA
62, 63
SLP_N_1, SLP_N_0
Sleep Mode
00: Sleep Mode
01: Channel 0 active
10: Channel 1 active
11: Both channels active
A / D Converters - SMT
0
Function
0-9
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Analog Input
The analog input to the HMCAD1040-80 is a switched
capacitor track-and-hold amplifier optimized for
differential operation. Operation at common mode
voltages at mid supply is recommended even if
performance will be good for the ranges specified. The
CM_EXT pin provides a voltage suitable as common
mode voltage reference. The internal buffer for the
CM_EXT voltage can be switched off, and driving
capabilities can be changed by using the CM_EXTBC
control input.
Figure 4 shows a simplified drawing of the input
network. The signal source must have sufficiently low
output impedance to charge the sampling capacitors
within one clock cycle. A small external resistor (e.g.
22 Ohm) in series with each input is recommended as
it helps reduce transient currents and dampens ringing
behavior. A small differential shunt capacitor at the chip
side of the resistors may be used to provide dynamic
charging currents and may improve performance. The
resistors form a low pass filter with the capacitor, and
values must therefore be determined by requirements
for the application.
Figure 4. Input configuration
DC-Coupling
Preferably, the CM_EXT output should be used as
reference to set the common mode voltage.
The input amplifier could be inside a companion chip
or it could be a dedicated amplifier. Several suitable
single ended to differential driver amplifiers exist in the
market. The system designer should make sure the
specifications of the selected amplifier is adequate for
the total system, and that driving capabilities comply
with the HMCAD1040-80 input specifications.
Detailed configuration and usage instructions should
be found in the documentation of the selected driver,
and the values given in figure 5 must be varied
according to the recommendations for the driver.
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 6 shows
a recommended configuration using a transformer.
Make sure that a transformer with sufficient linearity
is selected, and that the bandwidth of the transformer
is appropriate. The bandwidth should exceed the
sampling rate of the ADC with at least a factor of
10. It is also important to minimize phase mismatch
between the differential ADC inputs for good HD2
performance. This type of transformer coupled input
is the preferred configuration for high frequency
signals as most differential amplifiers do not have
adequate performance at high frequencies. Magnetic
coupling between the transformers and PCB traces
may impact channel crosstalk, and must be taken
into account during PCB layout. If the input signal
is traveling a long physical distance from the signal
source to the transformer (for example a long cable),
kick-backs from the ADC will also travel along this
distance. If these kick-backs are not terminated
properly at the source side, they are reflected and will
add to the input signal at the ADC input. This could
reduce the ADC performance. To avoid this effect, the
source must effectively terminate the ADC kick-backs,
or the traveling distance should be very short. If this
problem could not be avoided, the circuit in figure 8
can be used.
0
A / D Converters - SMT
Recommended Usage
Figure 5. DC coupled input with buffer
Figure 5 shows a recommended configuration for DCcoupling. Note that the common mode input voltage
must be controlled according to specified values.
Figure 6. Transformer coupled input
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0 - 10
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Figure 7 shows AC-coupling using capacitors.
Resistors from the CM_EXT output, RCM, should be
used to bias the differential input signals to the correct
voltage. The series capacitor, CI, form the highpass pole with these resistors, and the values must
therefore be determined based on the requirement to
the high-pass cut-off frequency.
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to
SNR from clock jitter with a full scale signal at a given
frequency is shown in equation 1,
0
SNRjitter = 20 · log (2 · π · ƒIN · єt)
A / D Converters - SMT
Figure 7. AC coupled input
Figure 8. Alternative input network
Note that startup time from Sleep Mode and Power
Down Mode will be affected by this filter as the time
required to charge the series capacitors is dependent
on the filter cut-off frequency.
If the input signal has a long traveling distance, and
the kick-backs from the ADC not are effectively
terminated at the signal source, the input network of
figure 8 can be used. The configuration in figure 8 is
designed to attenuate the kickback from the ADC and
to provide an input impedance that looks as resistive
as possible for frequencies below Nyquist. Values
of the series inductor will however depend on board
design and conversion rate. In some instances a
shunt capacitor in parallel with the termination resistor
(e.g. 33 pF) may improve ADC performance further.
This capacitor attenuates the ADC kick-back even
more, and minimizes the kicks traveling towards the
source. However, the impedance match seen into the
transformer becomes worse.
Clock Input and Jitter considerations
Typically high-speed ADCs use both clock edges to
generate internal timing signals. In the HMCAD1040-80
only the rising edge of the clock is used. Hence,
input clock duty cycles between 20% and 80% are
acceptable.
0 - 11
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally. Hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine
wave can be connected directly to the input pins.
For CMOS inputs, the CKN pin should be connected
to ground, and the CMOS clock signal should be
connected to CKP. For differential sine wave clock, the
input amplitude must be at least ± 800 mVpp.
(1)
where fIN is the signal frequency, and εt is the total
rms jitter measured in seconds. The rms jitter is the
total of all jitter sources including the clock generation
circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution
is well controlled. It might be advantageous to use
analog power and ground planes to ensure low noise
on the supplies to all circuitry in the clock distribution.
It is of utmost importance to avoid crosstalk between
the ADC output bits and the clock and between the
analog input signal and the clock since such crosstalk
often results in harmonic distortion.
The jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LVDS or LVPECL clock
with fast edges. CMOS and sine wave clock inputs will
result in slightly degraded jitter performance.
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Digital Outputs
Digital output data are presented in parallel CMOS
form. The voltage on the OVDD pin sets the levels of the
CMOS outputs. The output drivers are dimensioned to
drive a wide range of loads for OVDD above 2.25V,
but it is recommended to minimize the load to ensure
as low transient switching currents and resulting noise
as possible. In applications with a large fanout or large
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT
always should be lower than the load on data outputs
to ensure sufficient timing margins.
The digital outputs can be set in tristate mode by
setting the OE_N signal high.
The HMCAD1040-80 employs digital offset correction. This means that the output code will be 4096
with shorted inputs. However, small mismatches in
parasitics at the input can cause this to alter slightly.
The offset correction also results in possible loss of
codes at the edges of the full scale range. With no
offset correction, the ADC would clip in one end
before the other, in practice resulting in code loss
at the opposite end. With the output being centered
digitally, the output will clip, and the out of range flags
will be set, before max code is reached. When out of
range flags are set, the code is forced to all ones for
overrange and all zeros for underrange.
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connected to OVSS). Setting
DFRMT high (connected to OVDD) results in 2’s
complement output format. Details are shown in
table 3.
Table 3: Data Format Description for 2Vpp full scale range
Differential Input Voltage (IPx - INx)
Output data: Dx_9 : Dx_0
(DFRMT = 0, offset binary)
Output Data: Dx_9 : Dx_0
(DFRMT = 1, 2's complement)
1.0 V
11 1111 1111
01 1111 1111
+0.24mV
10 0000 0000
00 0000 0000
-0.24mV
01 1111 1111
11 1111 1111
-1.0V
00 0000 0000
10 0000 0000
Reference Voltages
The reference voltages are internally generated and
buffered based on a bandgap voltage reference. No
external decoupling is necessary, and the reference
voltages are not available externally. This simplifies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
Operational Modes
The operational modes are controlled with the PD_N
and SLP_N pins. If PD_N is set low, all other control
pins are overridden and the chip is set in Power Down
mode. In this mode all circuitry is completely turned off
and the internal clock is disabled. Hence, only leakage
current contributes to the Power Down Dissipation.
The startup time from this mode is longer than for
other idle modes as all references need to settle to
their final values before normal operation can resume.
The input clock should be kept running in all idle
modes. However, even lower power dissipation is
possible in Power Down mode if the input clock is
stopped. In this case it is important to start the input
clock prior to enabling active mode.
Startup Initialization
The HMCAD1040-80 must be reset prior to normal
operation. This is required every time the power
supply voltage has been switched off. A reset is
performed by applying Power Down mode. Wait until a
stable supply voltage has been reached, and pull the
PD_N pin for the duration of at least one clock cycle.
The input clock must be running continuously during
this Power Down period and until active operation
is reached. Alternatively the PD pin can be kept low
during power-up, and then be set high when the power
supply voltage is stable.
0
A / D Converters - SMT
capacitive loads, it is recommended to add external
buffers located close to the ADC chip.
The SLP_N bus can be used to power down each
channel independently, or to set the full chip in Sleep
Mode. In this mode internal clocking is disabled, but
some low bandwidth circuitry is kept on to allow for a
short startup time. However, Sleep Mode represents
a significant reduction in supply current, and it can be
used to save power even for short idle periods.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0 - 12
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Outline Drawing
A / D Converters - SMT
0
Table 4. 9x9mm QFN (64 Pin LP9) Dimensions
Symbol
Millimeter
Min
Typ
A
A1
0.01
0.05
A2
0.65
0.7
A3
0.2 REF
b
Min
Typ
0.9
0
0.2
D
0.25
0
3.79
L
0.3
e
0.3
0.008
0°
F
1.9
G
0.24
0.002
0.026
0.028
0.01
0.012
0.354 bsc
0.344 bsc
3.99
4.19
0.149
0.4
0.5
0.012
0.50 bsc
Ѳ1
0.0004
0.008 REF
8.75 bsc
D2
Max
0.035
9.00 bsc
D1
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Inch
Max
0.157
0.165
0.016
0.02
0.020 bsc
12°
0°
12°
0.075
0.42
0.6
0.0096
0.0168
0.024
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1040-80
v01.0411
Dual 10-Bit 65/80 MSPS
A/D Converter
Package Information
Part Number
Package Body Material
Lead Finish
MSL [1]
Package Marking [2]
HMCAD1040-80
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
Level 2A
ASD0400
XXXX
XXXX
[1] MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature.
[2] Proprietary marking XXXX, 4-Digit lot number XXXX
A / D Converters - SMT
0
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
0 - 14