hmcad1513 - Hittite Microwave

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HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Features
• 8-bit High Speed Dual / Quad ADC
Dual Channel Mode: FSmax = 500 MSPS
Quad Channel Mode:FSmax = 250 MSPS
Typical Applications
• Microwave backhaul
• Satellite Receivers
• Integrated Cross Point Switches (Mux Array)
• 1X to 50X Digital Gain –
No Missing Codes up to 32X
• 2X Gain: 49.8 dB SNR. 10X Gain: 48 dB SNR
• Internal Low Jitter Programmable Clock Divider
• Ultra Low Power Dissipation
710 mW including I/O at 500 MSPS
Pin Compatible Parts
Device
Channels
HMCAD1062
4
HMCAD1068
HMCAD1052
Resolution Sample Rate
(bits)
(MSPS)
ECCN
14
80/105/125
2
14
80/105/125
3A991.c.3
4
12
160
3A001.a.5.a.3
3A991.c.3
HMCAD1054
2
12
320
3A001.a.5.a.3
HMCAD1056
1
12
640
3A001.a.5.a.3
• Internal Reference Circuitry with no
External Components Required
HMCAD1510
4/2/1
8
125/250/500
3A991.c.1
HMCAD1511
4/2/1
8
250/500/1000 3A001.a.5.a.1
• Coarse and Fine Gain Control
HMCAD1512
2/1
8
450 / 900
3A001.a.5.a.1
• Digital Fine Gain Adjustment for each ADC
HMCAD1513
4/2
8
250 / 500
3A991.c.1
• Internal Offset Correction
HMCAD1520
4
4/2/1
14
12
• 0.5 µs Start-up Time from Sleep,
15 µs from Power Down
80/105
3A001.a.5.a.4
160/320/640
• 1.8 V Supply Voltage
• 1.7 - 3.6 V CMOS Logic on Control Interface Pins
• Serial LVDS/RSDS Output
• 7x7 mm QFN 48 (LP7D) Package
Functional Diagram
1
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital and Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
5
5
6
7
Pins and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Digital Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Performance Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
0x00 – Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x31 – Modes of Operation and Clock Divide Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x3A, 0x3B – Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x55 – Full-Scale Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x50 – Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x30, 0x56 – Start-up and Clock Jitter Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x42, 0x46, 0x53 – LVDS Output Configuration and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x11 – LVDS Drive Strength Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0F, 0x52 – Power Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x33, 0x2A, 0x2B, 0x34-0x37 – Programmable Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x24 – Analog Input Invert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x25 to 0x27, 0x45 – LVDS Test Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
23
24
25
26
28
29
30
31
32
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
33
34
36
36
37
37
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
The HMCAD1513 is a versatile high performance low power analog-to-digital converter (ADC), utilizing time-interleaving
to increase sampling rate. Integrated Cross Point Switches activate the input selected by the user.
In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode, any
input can be assigned to any ADC channel.
An internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational
modes.
The HMCAD1513 is based on a proprietary structure, and employs internal reference circuitry, a serial control
interface and serial LVDS/RSDS output data. Data and frame synchronization clocks are supplied for data capture
at the receiver. Internal 1 to 50X digital coarse gain with ENOB > 7.5 up to 16X gain, allows digital implementation of
oscilloscope gain settings. Internal digital fine gain can be set separately for each ADC to calibrate for gain errors.
Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each
channel can be powered down independently and data format can be selected through this interface. A full chip idle
mode can be set by a single external pin. Register settings determine the exact function of this pin.
HMCAD1513 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from several vendors.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
A/D Converters - SMT
General Description
3
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Electrical Specifications
A/D Converters - SMT
Operating Conditions
Min
Typ
Max
Unit
VAVDD
Parameter
Analog supply voltage range
Description
1.7
1.8
2.0
V
VDVDD
Digital and output driver voltage range
1.7
1.8
2.0
V
VOVDD
Digital CMOS Inputs supply voltage range
1.7
1.8
TA
Ambient temperature
-40
3.6
V
+85
°C
Note: The conditions listed in this table must be observed for the device to be functional as specified in this document.
These conditions do not guarantee specific performance levels – which are listed in the DC Electrical Specifications,
AC Specifications, and Digital and Switching Specifications, and apply under the test conditions specified therein.
Absolute Maximum Ratings
Parameter
Description
Max
Unit
+110
°C
-65
+150
°C
Analog supply voltage in reference to AVSS
-0.3
+2.3
V
DVDD
Digital supply voltage in reference to DVSS
-0.3
+2.3
V
OVDD
Digital CMOS Inputs supply voltage in reference to AVSS
-0.3
+3.9
V
AVSS-DVSS
Supply difference – AVSS and DVSS are connected internally
0.0
V
Tj
Junction temperature
Tstorage
Storage temperature
AVDD
Min
Vanalog
Analog inputs and outputs in reference to AVSS
-0.3
Vclock
Clock input pins voltage in reference to AVSS
-0.3
VLVDS
LVDS output pins voltage in reference to DVSS
-0.3
Vdigital-in
Digital input pins voltage in reference to DVSS
-0.3
ESD Rating
–
Typ
AVDD+0.3
or +2.3
OVDD+0.3
or 3.9
DVDD+0.2
or +2.3
OVDD+0.3
or 3.9
V
V
V
V
Human body model
2000
V
Charged device model
1000
V
Soldering profile characteristics
J-STD-020
Note: Operating the device beyond the limits specified in this table may cause immediate damage to the device. Functional operation of the device is further limited by the Operating Conditions. Device functionality is not implied by the
Absolute Maximum Ratings.
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
4
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Parameter
Description
Min
Typ
Max
Unit
θJA
Thermal resistance – junction-to-ambient
21
°C/W
θJCb
Thermal resistance – junction-to-case bottom pad
3.2
°C/W
Note: The thermal pad at the bottom of the device package must be attached to the PCB ground plane. It is also recommended that the thermal pad should be connected to a metal pad on the underside of the PCB through multiple
vias for heat conduction purposes as this is the most optimal path for heat dissipation of this device.
DC Electrical Specifications
AVDD = 1.8 V, DVDD = 1.8 V, OVDD = 1.8 V, FS = 125 MSPS, Quad Channel Mode, 50% clock duty cycle, -1 dBFS 70 MHz input signal,
1x/0 dB digital gain (fine and coarse), unless otherwise noted.
Parameter
Description
Min
Typ
Max
Unit
±6
%FS
DC accuracy
No missing codes
Guaranteed
Offset
Offset error after internal digital offset correction
Gabs
Gain error
0.05
LSB
Grel
Gain matching between channels. ±3 σ value at worst case
conditions
±0.5
%FS
Gain flatness
DC to 300 MHz
DC to 425 MHz
±0.5
±1.0
dB
INL
Integral non linearity
±0.5
LSB
DNL
Differential non linearity
±0.5
LSB
VCM,out
Common mode voltage output
A/D Converters - SMT
Thermal Information
VAVDD /2
Analog Input
VCM,in
Analog input common mode voltage
FSR
Differential input voltage full scale range
FSR2X
Differential input voltage full scale range, gain = 2X
Cin
Differential Input capacitance Dual/Quad channel mode
Rin
Differential input resistance 250/500 MSPS
VCM – 0.1
VCM +0.2
V
2
Vpp-diff
1
Vpp-diff
7/5
pF
1.8/0.9
kΩ
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
5
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
AC Specifications
A/D Converters - SMT
AVDD = 1.8 V, DVDD = 1.8 V, OVDD = 1.8 V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels, unless
otherwise noted. Minimum/maximum specifications are valid for full condition range.
Parameter
Description
Min
Typ
Max
Unit
Performance
SNR
Signal to Noise Ratio
Dual Ch Mode, FS = 500 MSPS
Quad Ch Mode, FS = 250 MSPS
SNDR
Quad Ch Mode, FS = 250 MSPS
Quad Ch Mode, FS = 250 MSPS
dBFS
49.8
dBFS
49.9
dBFS
48.5
49.9
dBFS
48.5
dBFS
43
48.5
dBFS
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
49.5
dBFS
47
49.6
dBFS
56
dBc
43.5
56
dBc
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
59
dBc
49
59
dBc
72
dBc
60
69
dBc
82
dBc
55
75
dBc
7.8
bits
6.9
7.8
bits
7.9
bits
7.5
7.9
bits
Worst of HD2/HD3
Dual Ch Mode, FS = 500 MSPS
Quad Ch Mode, FS = 250 MSPS
ENOB
49.8
48.5
Spurious Free Dynamic Range
Dual Ch Mode, FS = 500 MSPS
HD2/3
Gain=1X (FSR = 2 Vpp-diff)
Signal to Noise and Distortion Ratio
Dual Ch Mode, FS = 500 MSPS
SFDR
Gain=2X (FSR = 1 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Effective number of Bits
Dual Ch Mode, FS = 500 MSPS
Quad Ch Mode, FS = 250 MSPS
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Gain=2X (FSR = 1 Vpp-diff)
Gain=1X (FSR = 2 Vpp-diff)
Xtlk,2
CrossTalk Dual Ch Mode. –1 dBFS 70 MHz signal applied to input 1 or 4,
–1 dBFS 71 MHz signal applied to alternate input. Valid for input 1 and 4.
–90
dBc
Xtlk,4
CrossTalk Quad Ch Mode. –1 dBFS 70 MHz signal applied to input 1, 2, 3
or 4, –1 dBFS 71 MHz signal applied to alternate input. Valid for all input
combinations.
–73
dBc
Power Supply
Dual Ch: FS = 500 MSPS, Quad Ch: FS = 250 MSPS.
IAVDD
Analog supply current
270
mA
IDVDD
Digital and output driver supply current
125
mA
PAVDD
Analog Power
486
mW
PDVDD
Digital Power
224
P TOT
Total Power Dissipation
710
PPD
Power Down Mode dissipation
15
µW
PSLP
Deep Sleep Mode power dissipation
72
mW
PSLPCH
Power dissipation with all channels in sleep channel mode (Light sleep)
153
mW
PSLPCH_SAV
Power dissipation savings per channel off
(Quad Channel mode)
139
mW
Full Power Bandwidth
650
MHz
mW
850
mW
Analog Input
FPBW
Clock Inputs
6
FSmax
Max. conversion rate in modes: Dual Ch / Quad Ch
FSmin
Min. conversion rate in modes: Dual Ch / Quad Ch
500 / 250
MSPS
60 / 30
MSPS
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Digital and Switching Specifications
Parameter
Description
Min
Typ
Max
Unit
55
% high
Clock Inputs
DC
Duty Cycle
Compliance
LVDS supported up to 700 MHz
45
VCK,diff
Differential input voltage swing, LVDS, LVPECL
450
mVpp
VCK,sine
Differential input voltage swing, sine wave clock input
1500
mVpp
VCK,CMOS
Voltage input range CMOS (CLKN connected to ground)
VCM,CK
Input common mode voltage. Keep voltages within ground and
voltage of OVDD
CCK
Differential Input capacitance
FCKmax
Maximum input frequency on CLK pins
LVPECL, Sine wave, CMOS, LVDS
VOVDD
VOVDD – 0.3
0.3
V
3
pF
1000
MHz
Logic inputs (CMOS)
VHI
High Level Input Voltage. VOVDD ≥ 3.0 V
2
V
VHI
High Level Input Voltage. VOVDD = 1.7 V – 3.0 V
VLI
Low Level Input Voltage. VOVDD ≥ 3.0 V
0.8 ·VOVDD
0
0.8
V
V
VLI
Low Level Input Voltage. VOVDD = 1.7 V – 3.0 V
0
0.2 · VOVDD
V
IHI
High Level Input leakage Current
±10
µA
ILI
Low Level Input leakage Current
±10
µA
CI
Input Capacitance
3
A/D Converters - SMT
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted.
pF
Data Outputs
Compliance
LVDS / RSDS
VOUT
Differential output voltage, LVDS
350
mV
VOUT
Differential output voltage, RSDS
150
mV
VCM
Output common mode voltage
1.2
V
Output coding
Default/optional
Offset Binary/ 2’s complement
Timing Characteristics
tA
Aperture delay
1.5
ns
tjrms
Aperture jitter, One bit set to ‘1’ in jitter_ctrl<7:0>
300
fsrms
Tskew
Timing skew between ADC channels
2.5
psrms
TSU
Start up time from Power Down Mode and Deep Sleep Mode to
Active Mode. See section “Clock Frequency” for details.
15
µs
TSLPCH
Start up time from Sleep Channel Mode to Active Mode
0.5
µs
TOVR
Out of range recovery time
1
clock cycles
TLATQ
Pipeline delay, Quad Channel Mode
32
clock cycles
TLATD
Pipeline delay, Dual Channel Mode
64
clock cycles
LVDS Output Timing Characteristics
tSK
TPROP
Data skew with respect to LCLK
Clock propagation delay
LVDS bit-clock duty-cycle
±100
±200
6∙TLVDS +2.2 7∙TLVDS +3.5 7∙TLVDS +5.0
45
55
Frame clock cycle-to-cycle jitter
2.5
ps
ns
% LCLK
cycle
% LCLK
cycle
TEDGE
Data rise- and fall time 20% to 80%
0.28
0.35
ns
TCLKEDGE
Clock rise- and fall time 20% to 80%
0.28
0.35
ns
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
7
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Pins and Interfaces
A/D Converters - SMT
Pin Configuration and Description
Figure 1. Package Diagram (Top View)
Table 1. Pin Descriptions
Pin Name
Description
Pin Number
# Of Pins
GND
Thermal pad and main ground connection
0
1
AVDD
Analog power supply, 1.8 V
AVDD2
Analog power supply domain 2, 1.8 V
2
32
1
DVDD
Digital and I/O power supply, 1.8V
7, 30
2
DVSS
Digital ground
8, 29
2
OVDD
Digital CMOS Inputs supply voltage
AVSS
Analog ground
AVSS2
33
1
39, 42, 45
3
Analog ground domain 2
31
1
Chip select enable. Active low
2
1
SDATA
Serial data input
3
1
SCLK
Serial clock input
4
1
Reset SPI interface. Active low
5
1
Power-down input. Activate after applying
power in order to initialize the ADC
correctly. Alternatively use the SPI power
down feature
6
1
CSN
RESETN
PD
8
1, 36
Interface Schematics
–
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Pin Number
# Of Pins
DP1A
LVDS channel 1A, positive output
Description
9
1
DN1A
LVDS channel 1A, negative output
10
1
DP1B
LVDS channel 1B, positive output
11
1
1
DN1B
LVDS channel 1B, negative output
12
DP2A
LVDS channel 2A, positive output
13
1
DN2A
LVDS channel 2A, negative output
14
1
DP2B
LVDS channel 2B, positive output
15
1
DN2B
LVDS channel 2B, negative output
16
1
LCLKP
LVDS bit clock, positive output
17
1
LCLKN
LVDS bit clock, negative output
18
1
FCLKP
LVDS frame clock (1X), positive output
19
1
FCLKN
LVDS frame clock (1X), negative output
20
1
DP3A
LVDS channel 3A, positive output
21
1
DN3A
LVDS channel 3A, negative output
22
1
DP3B
LVDS channel 3B, positive output
23
1
DN3B
LVDS channel 3B, negative output
24
1
DP4A
LVDS channel 4A, positive output
25
1
DN4A
LVDS channel 4A, negative output
26
1
DP4B
LVDS channel 4B, positive output
27
1
DN4B
LVDS channel 4B, negative output
28
1
CLKN
Negative differential input clock.
34
1
CLKP
Positive differential input clock
35
1
IN4
Negative differential input signal, channel 4
37
1
IP4
Positive differential input signal, channel 4
38
1
IN3
Negative differential input signal, channel 3
40
1
IP3
Positive differential input signal, channel 3
41
1
IN2
Negative differential input signal, channel 2
43
1
IP2
Positive differential input signal, channel 2
44
1
IN1
Negative differential input signal, channel 1
46
1
IP1
Positive differential input signal, channel 1
47
1
Common mode output pin, 0.5 ∙ AVDD
48
1
VCM
Interface Schematics
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
A/D Converters - SMT
Pin Name
9
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Serial Interface
The HMCAD1513 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial
interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set
low:
• Serial data are shifted into the chip
• At every rising edge of SCLK, the value present at SDATA is latched
• SDATA is loaded into the register every 24th rising edge of SCLK
Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into
SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is
divided into two parts:
• The first eight bits form the register address
• The remaining 16 bits form the register data
Acceptable SCLK frequencies are from 20 MHz down to a few Hertz. Duty-cycle does not have to be tightly controlled.
SPI Timing Diagram
Figure 2 shows the timing of the serial port interface. Table 2 explains the timing variables used in Figure 2.
thi
tlo
tcs
CSN
tck
ts
tchi
tch
th
SCLK
SDATA
A7
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3 D2
D1
D0
Figure 2. Serial Port Interface Timing
Table 2. Serial Port Interface Timing Definitions
10
Parameter
Description
Minimum value
tcs
Setup time between CSN and SCLK
8
Unit
ns
tch
Hold time between SCLK and CSN
8
ns
ns
thi
SCLK high time
20
tlo
SCLK low time
20
ns
tck
SCLK period
50
ns
ts
Data setup time
5
ns
th
Data hold time
5
ns
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BITLVDS
A-TO-D
CONVERTER (ADC)
output at 250MSPS. 500ps/, 120mV/
DUAL 500 MSPS / QUAD 250 MSPS
LVDS output
By default, the HMCAD1513 digital outputs conform to the ANSI-644 LVDS (Low-voltage differential signaling) standard, i.e. the ilvds* register fields in register 0x11 are set to ‘000’. In this mode the LVDS driver current is set to 3.5 mA.
A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a 350 mV swing at the receiver.
The LVDS driver current level is recommended in the cases where the LVDS receiver does not accept a reduced
signal swing
The generally recommended LVDS driving current is the RSDS (Reduced strength differential signaling) which is
used by setting the ilvds* registers to ‘010’. In this mode the LVDS driver
current
is500MSPS.
set to 1.5 mA.
A 100 Ω differential
LVDS
output at
200ps/, 110mV/
termination resistor placed at the LVDS receiver inputs results in a 150 mV swing at the receiver. The reduced driver
current gives a power consumption advantage over the LVDS driver current level, while preserving full robustness with
most LVDS receivers.
To achieve full robustness for the HMCAD1513 LVDS outputs it is highly recommended to utilize a single point-to-point
topology terminated with 100 Ω as close to the LVDS receiver as possible. The routing traces should be fully differential traces with impedance matched to the load and matched on length.
When these guidelines are followed, a PCB trace length up to 12 inches can be recommended. Figure 3 and Figure 4
show the LVDS Eye diagrams for LVDS and RSDS driving currents respectively, measured over the termination resistor, at a distance of 12 inches from the ADC.
The LVDS output signals are differential outputs with 1.2 V common mode voltage. When a ‘1’ is set the DPxx will be
350/150mV higher than DNxx for LVDS/RSDS respectively. When a ‘0’ is set the DPxx will be 350/150 mV lower than
DNxx for LVDS/RSDS respectively. This means that the total differential output signal is 700/300 mVp-p for LVDS/
LVDS output at 250MSPS. 500ps/, 120mV/
LVDS output
at 450MSPS.
110mV/
RSDS
output at 200ps/,
250MSPS.
500ps/, 54mV/
RSDS respectively.
Figure
EyeatDiagram
for LVDS
current level
LVDS3.
output
500MSPS. 200ps/,
110mV/
(ilvds = ‘1’), acquired 10” from ADC.
Dual Channel Mode at 500 MSPS.
Scale: 110 mV/ over 200 ps/
RSDS output at 250MSPS. 500ps/, 54mV/
A/D Converters - SMT
Digital Output Interface
RSDS output
Figure
4. Eye Diagram for RSDS current level
LVDS output at 500MSPS. 200ps/, 54mV/
(ilvds = ‘0’), acquired 10” from ADC.
Dual Channel Mode at 500 MSPS.
Scale: 54 mV/ over 200 ps/
RSDS output at 450MSPS. 200ps/, 54mV/
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
11
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Timing Diagrams
12
N+31
N+32
N+33
Analog input
N+35
N+34
Input clock
LCLKP
LCLKN
FCLKP
FCLKN
TLVDS
DxnA
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
N-4 N-4 N-4 N-4 N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N
D1
N
D2
N
D3
N
D4
N
D5
N
D6
N
DxnB
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-3 N-3 N-3 N-3 N-3 N-3 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+1 N+1 N+1 N+1 N+1 N+1 N+1
TPROP
Figure 5. Quad channel – LVDS timing 8-bit output
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
N+62
N+63
N+64
N+65
N+66
Analog input
N+67
N+70
N+68
N+69
Input clock
TLVDS
LCLKP
LCLKN
FCLKP
FCLKN
Dx1A / Dx3A
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
N-8 N-8 N-8 N-8 N-8 N-8 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N
D1
N
D2
N
D3
N
D4
N
D5
N
D6
N
Dx1B / Dx3B
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-7 N-7 N-7 N-7 N-7 N-7 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+1 N+1 N+1 N+1 N+1 N+1 N+1
Dx2A / Dx4A
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-6 N-6 N-6 N-6 N-6 N-6 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+2 N+2 N+2 N+2 N+2 N+2 N+2
Dx2B / Dx4B
D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
N-5 N-5 N-5 N-5 N-5 N-5 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+3 N+3 N+3 N+3 N+3 N+3 N+3
A/D Converters - SMT
Timing Diagrams, continued
TPROP
Figure 6. Dual channel – LVDS timing 8-bit output
TLVDS
LCLKP
LCLKN
TLVDS /2
Dxxx
tSK
Figure 7. LVDS data timing
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
13
HMCAD1513
v00.0414
Typical Performance Plots
Figure 1. Performance vs. Input Frequency
Figure 2. Performance vs. Input Frequency
Dual Mode, 500 MSPS, Ain = -1 dBFS, Gain 1x
Dual Mode, 500 MSPS, Ain = -1 dBFS, Gain 2x
80
65
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
70
HD2/3 (dBc)
60
SFDR (dBc)
55
SNR (dBFS)
50
SNDR (dBFS)
45
75
70
HD2/3 (dBc)
65
60
SFDR (dBc)
55
SNR (dBFS)
50
SNDR (dBFS)
45
40
0
100
200
300
400
40
500
0
200
300
400
500
FREQUENCY (MHz)
Figure 3. Performance vs. Input Frequency
Figure 4. Performance vs. Input Frequency
Quad Mode, 250 MSPS, Ain = -1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Ain = -1 dBFS, Gain 2x
85
80
80
PERFORMANCE (dBc/dBFS)
85
75
70
HD2/3
65
60
SFDR (dBc)
55
SNR (dBFS)
50
75
HD2/3
70
65
60
SFDR (dBc)
55
SNR (dBFS)
50
SNDR (dBFS)
45
SNDR (dBFS)
45
0
100
200
300
400
500
0
FREQUENCY (MHz)
100
200
300
400
500
FREQUENCY (MHz)
Figure 5. Performance vs. Temperature
Figure 6. Performance vs. Temperature
Dual Mode, 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
90
80
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
85
75
HD2/3 (dBc)
70
65
60
SFDR (dBc)
55
50
SNR (dBFS)
SNDR (dBFS)
45
-50
0
50
TEMPERATURE (°C)
14
100
FREQUENCY (MHz)
PERFORMANCE (dBc/dBFS)
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
100
80
HD2/3 (dBc)
70
60
SFDR (dBc)
SNR (dBFS)
50
SNDR (dBFS)
40
-50
0
50
100
TEMPERATURE (°C)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
Figure 7. Performance vs. Supply Voltage
Figure 8. Performance vs. Supply Voltage
Dual Mode, 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
90
HD2/3 (dBc)
70
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
75
65
SFDR (dBc)
60
55
SNR (dBFS)
50
80
HD2/3 (dBc)
70
SFDR (dBc)
60
SNR (dBFS)
50
SNDR (dBFS)
SNDR (dBFS)
45
1.7
1.8
1.9
40
2
1.7
1.8
SUPPLY VOLTAGE (V)
1.9
2
SUPPLY VOLTAGE (V)
Figure 9. Performance vs. Input Amplitude
Figure 10. Performance vs. Input Amplitude
Dual Mode, 500 MSPS, Fin = 70 MHz, Gain 1x
Quad Mode, 250 MSPS, Fin = 70 MHz, Gain 1x
60
50
70
SFDR (dBFS)
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
70
SNR (dBFS)
40
SFDR (dBc)
30
20
SFDR (dBFS)
60
50
SNR (dBFS)
40
SFDR (dBc)
30
20
SNR (dBc)
10
-35
-30
SNR (dBc)
-25
-20
-15
-10
-5
10
-35
0
-30
-25
INPUT AMPLITUDE (dBFS)
-20
-15
-10
-5
0
INPUT AMPLITUDE (dBFS)
Figure 11. Performance vs. Full Scale Range
Figure 12. Performance vs. Full Scale Range
Dual Mode, 500 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
80
90
70
HD2/3 (dBc)
60
SFDR (dBc)
SNR (dBFS)
50
SNDR (dBFS)
40
30
0
0.4
0.8
1.2
FULL SCALE RANGE (Vpp)
1.6
2
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
80
HD2/3 (dBc)
70
SFDR (dBc)
60
SNR (dBFS)
50
SNDR (dBFS)
40
30
0
0.4
0.8
1.2
1.6
2
FULL SCALE RANGE (Vpp)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
15
HMCAD1513
v00.0414
Figure 14. Differential Nonlinearity – DNL
Dual Mode, 500 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
DNL (LSB)
DNL (LSB)
Figure 13. Differential Nonlinearity – DNL
0
-0.05
0
-0.05
-0.1
-0.1
-0.15
-0.15
-0.2
-0.2
CODE
CODE
Figure 15. Integral Nonlinearity – INL
Figure 16. Integral Nonlinearity – INL
Dual Mode, 500 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
INL (LSB)
INL (LSB)
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0
-0.1
0
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
CODE
CODE
Figure 17. Fourier Transform – FFT
Figure 18. Fourier Transform – FFT
Dual Mode, 500 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
Quad Mode, 250 MSPS, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
0
FOURIER TRANSFORM (dBFS)
FOURIER TRANSFORM (dBFS)
0
-20
-40
-60
-80
-100
-40
-60
-80
-100
0
50
100
150
FREQUENCY (MHz)
16
-20
200
250
0
20
40
60
80
100
120
FREQUENCY (MHz)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
Figure 19. Performance vs. Sampling Rate
Figure 20. Performance vs. Sampling Rate
Dual Mode, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
Quad Mode, Fin = 71 MHz, Ain = –1 dBFS, Gain 1x
90
90
PERFORMANCE (dBc/dBFS)
PERFORMANCE (dBc/dBFS)
HD2/3 (dBc)
80
70
60
SFDR (dBc)
SNR (dBFS)
50
80
HD2/3 (dBc)
70
SFDR (dBc)
60
SNR (dBFS)
50
SNDR (dBFS)
SNDR (dBFS)
40
40
100
200
300
400
500
50
150
250
SAMPLING RATE (MSPS)
SAMPLING RATE (MSPS)
Figure 21. Power Dissipation vs.
Sampling Rate
Quad Mode, Fin = 70 MHz, Ain = -1 dBFS, Gain 1x
POWER DISSIPATION (mW)
800
700
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Total
600
500
Analog
400
300
200
Dig/Outp
100
0
0
50
100
150
200
250
300
SAMPLING RATE (MSPS)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
17
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Register Map Summary
A/D Converters - SMT
Table 3. Register Map
Name
rst *
Description
Self-clearing software reset*
‘0000’
Inactive
Channel-specific sleep mode for a
Dual Channel setup
‘00’
Inactive
sleep2_ch<1:0>
sleep
Go to sleep-mode
‘0’ – Inactive
pd
Go to power-down
‘0’ – Inactive
pd_pin_cfg
<1:0>
Configures the PD pin function
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
X
X
‘00’
PD pin invokes
power-down mode
X
‘000’
3.5 mA drive
ilvds_fclk<2:0>
LVDS current drive programmability
for FCLKP and FCLKN pins
‘000’
3.5 mA drive
ilvds_dat<2:0>
LVDS current drive programmability
for output data pins
‘000’
3.5 mA drive
en_lvds_term
Enables internal termination for
LVDS buffers
‘0’
Termination disabled
X
term_lclk<2:0>
Programmable termination for
LCLKN and LCLKP buffers
‘000’
Termination disabled
1
term_fclk<2:0>
Programmable termination for
FCLKN and FCLKP buffers
‘000’
Termination disabled
1
term_dat<2:0>
Programmable termination for
output data buffers
‘000’ –
Termination disabled
1
Channel specific swapping
invert4_ch<3:0> of the analog input signal
for a Quad Channel setup
‘0000’
IPx is positive input
Channel specific swapping
invert2_ch<1:0> of the analog input signal
for a Dual Channel setup
‘00’
IPx is positive input
X
X
D0
Hex
Address
X
0x00
X
X
0x0F
X
X
X
X
X
X
X
X
0x11
X
X
X
X
X
0x12
X
X
X
X
X
X
X
X
X
X
0x24
X
X
en_ramp
Enables a repeating full-scale ramp
pattern on the outputs
‘000’
Inactive
X
0
0
dual_custom_
pat
Enable the mode wherein the output
toggles between two defined codes
‘000’
Inactive
0
X
0
‘000’
Inactive
0
0
X
bits_custom2
<7:0>
D1
X
LVDS current drive programmability
for LCLKP and LCLKN pins
bits_custom1
<7:0>
D2
X
ilvds_lclk<2:0>
Bits for the single custom pattern
and for the first code of the dual
custom pattern
D3
‘0’ – Inactive
Channel-specific sleep mode for a
sleep4_ch<3:0>
Quad Channel setup
single_custom_ Enables the mode wherein the
pat
output is a constant specified code
0x25
0x00
X
X
X
X
X
X
X
X
0x26
Bits for the second code of the dual
custom pattern
0x00
X
X
X
X
X
X
X
X
0x27
cgain4_ch1
<3:0>
Programmable coarse gain
channel 1 in a Quad Channel setup
‘0000’
1x gain
cgain4_ch2
<3:0>
Programmable coarse gain
channel 2 in a Quad Channel setup
‘0000’
1x gain
cgain4_ch3
<3:0>
Programmable coarse gain
channel 3 in a Quad Channel setup
‘0000’
1x gain
cgain4_ch4
<3:0>
Programmable coarse gain
channel 4 in a Quad Channel setup
‘0000’
1x gain
cgain2_ch1
<3:0>
Programmable coarse gain
channel 1 in a Dual Channel setup
‘0000’
1x gain
cgain2_ch2
<3:0>
Programmable coarse gain
channel 2 in a Dual Channel setup
‘0000’
1x gain
X
X
X
X
0x01 (one bit set)
minimal power
X
X
X
X
jitter_ctrl<7:0>
Clock jitter adjustment
channel_num
<1:0>*
Set number of channels:
Dual or Quad Channel Mode*
clk_divide
<1:0>*
18
Default
Define clock divider factor:
1, 2, 4 or 8*
X
X
X
X
X
X
0x2A
X
X
X
X
X
X
X
X
X
X
X
X
0x2B
‘01’
Dual Channel Mode
‘00’
Divide by 1
X
X
X
X
X
X
X
X
0x30
0x31
X
X
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Name
cgain_cfg
Description
Configures the coarse gain setting
Default
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
‘1’ – x-gain selected
D0
Hex
Address
X
0x33
fine_gain_en
Enable use of fine gain
fgain_branch1
<6:0>
Programmable fine gain for branch 1
‘000 0000’
0dB gain
fgain_branch2
<6:0>
Programmable fine gain for branch 2
‘000 0000’
0dB gain
fgain_branch3
<6:0>
Programmable fine gain for branch 3
‘000 0000’
0dB gain
fgain_branch4
<6:0>
Programmable fine gain for branch 4
‘000 0000’
0dB gain
fgain_branch5
<6:0>
Programmable fine gain for branch 5
‘000 0000’
0dB gain
fgain_branch6
<6:0>
Programmable fine gain for branch 6
‘000 0000’
0dB gain
fgain_branch7
<6:0>
Programmable fine gain for branch 7
‘000 0000’
0dB gain
fgain_branch8
<6:0>
Programmable fine gain for branch 8
‘000 0000’
0dB gain
inp_sel_adc1
<4:0>
Input select for ADC 1
‘00010’
Signal input: IP1/IN1
inp_sel_adc2
<4:0>
Input select for ADC 2
‘00100’
Signal input: IP2/IN2
inp_sel_adc3
<4:0>
Input select for ADC 3
‘01000’
Signal input: IP3/IN3
Input select for ADC 4
‘10000’
Signal input: IP4/IN4
inp_sel_adc4
<4:0>
phase_ddr<1:0>
pat_deskew
Controls the phase of the LCLK
output relative to data
‘0’ – disabled
X
X
X
X
X
X
X
X
0x34
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x35
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x36
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x37
X
X
X
X
X
X
X
X
X
X
X
0
0x3A
X
X
X
X
0
X
X
X
X
A/D Converters - SMT
Table 3: Register Map, continued
0
0x3B
X
‘10’ – 90 degrees
X
X
X
0
X
X
0x42
Enable deskew pattern mode
‘00’ – Inactive
0
X
pat_sync
Enable sync pattern mode
‘00’ – Inactive
X
0
btc_mode
Binary two’s complement format for
ADC output data
‘0’ – Straight offset
binary
msb_first
Serialized ADC output data comes
out with MSB first
‘0’ – LSB first
0x45
adc_curr<2:0>
ADC current scaling
X
0x46
X
‘000’ – Nominal
X
X
0x50
ext_vcm_bc
<1:0>
VCM buffer driving strength control
‘01’ – ±20 μA
lvds_pd_mode
Controls LVDS power down mode
‘0’ – High z-mode
low_clk_freq *
Low clock frequency used*
‘0’ – Inactive
lvds_advance
Advance LVDS data bits and frame
clock by one clock cycle
‘00’ – Inactive
0
lvds_delay
Delay LVDS data bits and frame
clock by one clock cycle
‘00’ – Inactive
fs_cntrl<5:0>
Fine adjust ADC full scale range
‘10 0000’
0% change
startup_ctrl
<2:0> *
X
Controls start-up time *
X
X
X
X
0x52
0
0
0
X
0
0
0
X
0
0
0
0
X
X
X
X
X
0x55
X
X
X
0x56
‘000’
X
0x53
Undefined register addresses must not be written to; incorrect behaviour may be the result.
Unused register bits (blank table cells) must be set to ‘0’ when programming the registers.
All registers can be written to while the chip is in power down mode.
* These registers require a Power Down Mode Cycle when written to (See Start up Initialization on next page).
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
19
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Start Up Initialization
For proper operation and performance of the HMCAD1513, the following procedure must be followed:
Step #
1. Apply power
Address
Data
–
–
0x0001
Description
Ensure supply voltages are settled properly before proceeding.
A reset can be invoked by one of two ways:
a) By applying a low-going pulse (minimum 20 ns) on the RESETN pin
(asynchronous).
b) By using the SPI to set the rst bit high. When this bit is set, internal
registers are reset to default values, the rst bit is self-reset to zero. When
using this method, do not apply any low-going pulse on the RESETN pin.
2. Reset ADC
0x00
3. If desired:
Select clock divider and/or change
to Quad Channel Mode
0x31
4. If desired:
Adjust jitter_ctrl for high performance at high FCK (above
800 MHz)
0x30
0x00FF
See also “Clock Jitter Performance” on page 25
5. If desired:
Reduce LVDS driving current
0x11
0x0222
The recommended setting is 0x0222, giving RSDS (1.5 mA) driving currents.
The default (0x0000) LVDS driving currents (3.5 mA) should be used for LVDS
receivers not supporting RSDS.
6. If desired:
Increase driving current
on VCM pin
0x50
0x0030
The recommended setting is 0x0030 (max. driving current). When full
strength is not required, the driving strength can be decreased to save power
consumption. If the VCM pin is not in use, the buffer can be switched off,
0x0000.
See also “0x31 – Modes of Operation and Clock Divide Factor” on page 21
7. If desired:
Write additional register settings
Any changes to any other registers/bits marked with an asterisk (*) in Table 3
must be written now.
8. Set ADC in Power Down Mode
0x0F
0x0200
9. Wake ADC from
Power Down Mode
0x0F
0x0000
Power down can be set by one of two ways:
a) By setting the PD pin high (asynchronous).
b) By writing the pd bit in register 0x0F to ‘1’.
Depending on the method chosen in step 8:
a) Set PD pin low again
b) Set register bit pd in register 0x0F to ‘0’
10. Wait for Start-Up
–
–
See “Table 10. Start-Up Time Control Settings” on page 25
During normal operation, the register values marked with an asterisk (*) in Table 3 are set by first writing the desired
register value and then performing a Power Down Cycle, i.e. by executing steps 7 to 10.
20
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
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Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x00 – Software Reset
Name
rst*
Description
Default
D15
Self-clearing software reset
‘0’ – Inactive
D14
D13
D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Address
X
0x00
Setting the rst register bit to ‘1’ restores the default value of all the internal registers including the rst register bit itself.
0x31 – Modes of Operation and Clock Divide Factor
Name
Description
Default
channel_num<1:0>*
Set number of channels:
Dual or Quad Channel Mode
‘01’
2 channels
clk_divide<1:0>*
Define clock divider factor: 1, 2, 4 or 8
‘00’
Divide by 1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
Hex
Address
X
0x31
X
X
The HMCAD1513 has two main operating modes controlled by the register bits channel_num<1:0> as defined in
Table 4. Power down mode, as described in section ‘Startup Initialization’, must be activated after or during a change
of operating mode to ensure correct operation. All active operating modes utilize interleaving of eight internal ADC
branches (two per ADC channel) to achieve high sampling speed. Quad Channel Mode interleaves two ADC branches
per channel, while Dual Channel Mode interleaves four ADC branches per channel.
A/D Converters - SMT
Register Description
Table 4. Modes of Operation
channel_num <1:0> Mode of operation
Description
01 (default)
Dual Channel
Dual channel where channel 1 is made by interleaving ADC1 and ADC2,
channel 2 by interleaving ADC3 and ADC4
10
Quad Channel
Quad channel where channel 1 corresponds to
ADC1, channel 2 to ADC2, channel 3 to ADC3
and channel 4 to ADC4
Only one of the two bits should be activated at the same time.
clk_divide<1:0> allows the user to apply an input clock frequency FCK higher than the sampling rate FS. The clock
divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide<1:0> register. By setting the clk_divide<1:0> value relative to the channel_num<1:0> value, the same input clock frequency can be used
for all settings on number of channels. E.g: When increasing the number of channels from 2 to 4, the maximum sampling rate is reduced by a factor of two. By letting clk_divide<1:0> follow the channel_num<1:0> value, and change it
from 1 to 2, the internal clock divider will provide the reduction of the sampling rate without changing the input clock
frequency.
Table 5. Clock Divider Factor
clk_divide<1:0>
Clock Divider Factor
Sampling rate (FS)
00 (default)
1
Input clock frequency FCK / 1
01
2
Input clock frequency FCK / 2
10
4
Input clock frequency FCK / 4
11
8
Input clock frequency FCK / 8
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
21
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x3A, 0x3B – Input Select
A/D Converters - SMT
Name
Description
Default
Input select for ADC 1
‘00010’
Signal input: IP1/IN1
inp_sel_adc2 <4:0>
Input select for ADC 2
‘00100’
Signal input: IP2/IN2
inp_sel_adc3 <4:0>
Input select for ADC 3
‘01000’
Signal input: IP3/IN3
inp_sel_adc4 <4:0>
Input select for ADC 4
‘10000’
Signal input: IP4/IN4
inp_sel_adc1 <4:0>
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
0
Hex
Address
0x3A
X
X
X
X
0
X
X
X
X
0
0x3B
X
X
X
X
0
Each ADC is connected to the four input signals via a fully flexible cross point switch, set up by inp_sel_adcx.
In Dual Channel mode, a channel consists of two ADC cores which are interleaved according to Table 4 on page 21.
The two cores per channel require identical inputs. Any two of the four inputs can be selected to each ADC channel.
However, Input 1 and 4 should be used to for full CrossTalk performance. If input 2 or 3 is utilized in Dual Channel
Mode, please refer to Quad Channel CrossTalk.
In Quad Channel mode any input can be assigned to any ADC channel. The switching of inputs can be done during
normal operation, and no additional actions are needed. The switching will occur instantaneously at the end of each
SPI command.
Table 6. Input Select
inp_sel_adcx<4:0>
Selected Input
0 0010
IP1/IN1
0 0100
IP2/IN2
0 1000
IP3/IN3
1 0000
IP4/IN4
other
Do not use
inp_sel_adc1<4:1>
<4:1>
IP1 / IN1
inp_sel_adc2<4:1>
ADC 1
<4:1>
IP2 / IN2
inp_sel_adc3<4:1>
ADC 2
<4:1>
IP3 / IN3
inp_sel_adc4<4:1>
IP4 / IN4
ADC 3
<4:1>
Cross Point Switch
(Analog Mux)
ADC 4
Figure 8. ADC input signals through Cross Point Switch
22
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
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Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Name
Description
Default
fs_cntrl <5:0>
Fine adjust ADC full scale range
‘10 0000’
0% change
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hex
Address
X
X
X
X
X
X
0x55
The full-scale voltage range of HMCAD1513 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl
register. Changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. This
leads to a maximum range of ±10% adjustment. Table 9 shows how the register settings correspond to the full-scale
range. Note that the values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be
monotonous.
The full-scale control and the programmable gain features differ in two major ways:
1.The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable
gain is a digital feature.
2.The programmable gain feature has much coarser gain steps and larger range than the full-scale control.
Table 7. Register Values with Corresponding Change in Full-Scale Range
fs_cntrl<5:0>
Full-Scale Range Adjustment
111111
9.70%
111110
9.40%
…
…
100001
0.30%
100000
0%
011111
-0.3%
…
…
000001
-9.7%
000000
-10%
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
A/D Converters - SMT
0x55 – Full-Scale Control
23
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
0x50 – Current Control
Name
Description
Default
adc_curr<2:0>
ADC current scaling.
‘000’ – Nominal
ext_vcm_bc<1:0>
VCM buffer driving strength control
‘01’ – ±20 μA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
X
X
D3
D2
D1
D0
X
X
X
Hex
Address
0x50
There are two registers that impact performance and power dissipation.
The adc_curr register scales the current consumption in the ADC core. The performance is guaranteed at the nominal setting. Lower power consumption can be achieved by reducing the adc_curr value, see Table 8. The impact on
performance is low for settings down to minimum, but will depend on the ADC sampling rate.
Table 8. ADC Current Control Settings
adc_curr<2:0>
ADC Core Current
100
-40%
101
-30%
110
-20%
111
-10%
000 (default)
Nominal
001
Do not use
010
Do not use
011
Do not use
Table 9. External Common Mode Voltage
Buffer Driving Strength
ext_vcm_bc<1:0>
VCM buffer driving strength (µA)
Max current sinked/sourced from VCM pin
with < 20 mV voltage change.
00
Off (VCM floating)
01 (default)
±20
10
±400
11 (recommended)
±700
The ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the VCM pin. If this pin is
not in use, the buffer can be switched off (ext_vcm_bc = ‘00’). The VCM pin driving strength can be decreased to save
power consumption when full strength is not required.
The maximum driving strength (ext_vcm_bc = ‘11’) is recommended if power dissipation is not extremely important as
it results in the most accurate VCM output voltage.
24
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
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Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Name
Description
startup_ctrl<2:0>
Controls start-up time
'000'
Clock jitter adjustment
‘0000 0001’
one bit set
jitter_ctrl<7:0>
Default
D15
D14
D13
D12 D11 D10
D9
D8
D7
X
D6
D5
X
X
D4
X
D3
X
D2
D1
D0
Hex
Address
X
X
X
0x56
X
X
X
0x30
To optimize start up time, register startup_ctrl is provided where the start-up time in number of clock cycles can be set.
Some internal circuitry have start up times that are clock frequency independent. Default counter values are set to accommodate these start up times at the maximum clock frequency (sampling rate). This will lead to increased start up
times at low clock frequencies. Setting the value of this register to the nearest higher clock frequency will reduce the
count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced.
The start up times from power down and sleep modes are changed by this register setting. If the clock divider is used
(set to other than 1), the input clock frequency must be divided by the divider factor to find the correct clock frequency
range (see Table 5).
Table 10. Start-Up Time Control Settings
Quad Channel Mode
Dual Channel Mode
startup_ctrl
<2:0>
Sampling Rate
Range (MSPS)
Startup Delay
(clock cycles)
Startup Delay
(µs)
startup_ctrl
<2:0>
Sampling Rate
Range (MSPS)
Startup Delay
(clock cycles)
Startup Delay
(µs)
100
160 - 250
3072
12.3 - 19.2
100
320 - 500
6144
12.3 - 19.2
000
100 - 160
1984
12.4 - 19.8
000
200 - 320
3968
12.4 - 19.8
001
65 - 100
1280
12.8 - 19.7
001
130 – 200
2560
12.8 - 19.7
010
40 - 65
840
12.9 - 21
010
80 - 130
1680
12.9 - 21
011
30 - 40
520
13 - 17.3
011
60 – 80
1040
13 - 17.3
other
Do not use
-
-
other
Do not use
-
-
A/D Converters - SMT
0x30, 0x56 – Start-up and Clock Jitter Control
When the clock division factor is 2 or higher, Clock Input Frequencies FCK ≤ 1000 MHz are applicable. To maintain
high performance for high Clock Input Frequencies FCK ≥ 800 MHz it is recommended to set two or more bits in
jitter_ctrl.
jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register
are set low, the clock signal is stopped. The clock jitter depends on the number of bits set to ‘1’ in the jitter_ctrl<7:0>
register. Which bits are set high does not affect the result.
Table 11. Clock Jitter Performance
Number of bits to ‘1’ in
jitter_ctrl<7:0>
Clock jitter
performance [fsrms]
Module
current consumption
[mA]
0
Clock stopped
1 (default)
lowest power
1
2 (recommended for
FCK > 800 MHz)
:
2
3
:
3
4
:
4
5
:
5
6
:
6
7
:
7
8
lowest jitter
8
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
25
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
0x42, 0x46, 0x53 – LVDS Output Configuration and Control
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
low_clk_freq
Low clock frequency used
‘0’ – Inactive
lvds_advance
Advance LVDS data bits and
frame clock by one clock cycle
‘00’ – Inactive
0
X
lvds_delay
Delay LVDS data bits and
frame clock by one clock cycle
‘00’ – Inactive
X
0
phase_ddr<1:0>
Controls the phase of the LCLK
output relative to data
‘10’ – 90 degrees
btc_mode
Binary two's complement
format for ADC output data
‘0’
Straight offset binary
msb_first
Serialized ADC output data
comes out with MSB first
‘0’ – LSB first
D3
D2
D1
D0
Hex
Address
X
X
0x53
X
0x42
X
0x46
X
The HMCAD1513 uses an 8-bit serial LVDS output interface as shown in the Timing Diagrams section. The different
selection of number of channels (channel_num<1:0> in register 0x31) uses the LVDS outputs as defined by Table
12.
Table 12. Use of LVDS Outputs
channel_num<1:0>
in register 0x31
Channel Number
LVDS Outputs Used
Channel 1
D1A, D1B, D2A, D2B
Channel 2
D3A, D3B, D4A, D4B
Channel 1
D1A, D1B
Channel 2
D2A, D2B
Channel 3
D3A, D3B
Channel 4
D4A, D4B
‘01’ - Dual channel mode
‘10’ - Quad channel mode
Maximum data output bit-rate for HMCAD1513 is 1 Gb/s. The maximum sampling rate for the different configurations is given by Table 13. The sampling rate FS is set by the frequency of the input clock FCK and the clock divider,
FS = FCK / clk_div. The frame-rate, i.e. the frequency of the FCLK signal on the LVDS outputs, depends on the selected
mode and the sampling frequency (FS) as defined in Table 13.
If the HMCAD1513 device is used at a low sampling rate the register bit low_clk_freq has to be set to ‘1’. See Table 13
for when to use this register bit for the different modes of operation.
Table 13. Sampling and Frame Rate Properties in Dual and Quad Channel Mode
Frame Rate (FCLK Frequency)
Limit When low_clk_freq
Should Be Activated
500
FS / 4
FS < 120 MHz
250
FS / 2
FS < 60 MHz
Mode of Operation
Maximum Sampling Rate FSmax
(MSPS)
Dual Channel
Quad Channel
To ease timing in the receiver when using multiple HMCAD1513, the device has the option to adjust the timing of the
output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS
clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. See Figure 9 for details. Note
that LCLK is not affected by lvds_delay or lvds_advance settings.
26
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
LCLKP
LCLKN
TLVDS
TPROP
FCLKN
FCLKP
default:
Dxxx
D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N
TPROP
Dxxx
D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2
TPROP
D2
N
D3
N
D4
N
D5
N
D6
N
TLVDS
FCLKP
FCLKN
lvds_delay = '1':
D1
N
D0
N
D1
N
D2
N
D3
N
D4
N
D5
N
D2
N
D3
N
D4
N
D5
N
D6
N
D7
N
TLVDS
FCLKP
FCLKN
lvds_advance = '1':
Dxxx
D0 D1 D2 D3 D4 D5 D6 D7 D0
N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N
D1
N
A/D Converters - SMT
Input clock
Figure 9.LVDS output timing adjustment
The LVDS output interface of HMCAD1513 is a DDR interface. The default setting is with the LCLK rising and falling
edge transitions in the middle of alternate data windows. The phase for LCLK can be programmed relative to the
output frame clock and data bits using phase_ddr<1:0>. The LCLK phase modes are shown in Figure 10. The default
timing is identical to setting phase_ddr<1:0>=’10’.
PHASE_DDR<1:0>='00' (270 deg)
FCLKN
FCLKP
LCLKP
LCLKN
Dxx<1:0>
PHASE_DDR<1:0>='10' (90 deg)
FCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
PHASE_DDR<1:0>='01' (180 deg)
FCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
PHASE_DDR<1:0>='11' (0 deg)
FCLKN
FCLKP
LCLKP
LCLKN
Dxx<1:0>
Figure 10. Phase programmability modes for LCLK
The default data output format is offset binary. Two’s complement mode can be selected by setting the btc_mode bit
to ‘1’ which inverts the MSB.
The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Programming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP
rising edge.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
27
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x11 – LVDS Drive Strength Programmability
A/D Converters - SMT
Name
Description
Default
ilvds_lclk <2:0>
LVDS current drive programmability for
LCLKP and LCLKN pins.
‘000’
3.5 mA drive
ilvds_fclk <2:0>
LVDS current drive programmability for
FCLKP and FCLKN pins.
‘000’
3.5 mA drive
ilvds_dat <2:0>
LVDS current drive programmability for
output data pins.
‘000’
3.5 mA drive
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
X
X
X
D5
X
D4
D3
D2
D1
D0
X
X
X
Hex
Address
0x11
X
X
The current delivered by the LVDS output drivers can be configured as shown in Table 14. The default current is
3.5 mA, according to the LVDS standard.
To reduce power consumption in the HMCAD1513, Reduced Swing Data Signaling (RSDS), is recommended. The
output current drive setting should then be 1.5 mA.
Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and
LCLKN pins.
Setting the ilvds_fclk<2:0> register controls the current drive strength of the frame clock output on the FCLKP and
FCLKN pins.
Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]N pins.
Table 14. LVDS Output Drive Strength
for LCLK, FCLK & Data
Table 15. LVDS Output Internal
Termination for LCLK, FCLK and Data
ilvds_*<2:0>
LVDS Drive Strength
term_*<2:0>
LVDS Internal Termination
000
3.5 mA (default)
000
Termination disabled
001
2.5 mA
001
260Ω
010
1.5 mA (RSDS)
010
150Ω
011
0.5 mA
011
94Ω
100
7.5 mA
100
125Ω
101
6.5 mA
101
80Ω
110
5.5 mA
110
66Ω
111
4.5 mA
111
55Ω
0x12 – LVDS Internal Termination Programmability
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9
en_lvds_term
Enables internal termination for
LVDS buffers
‘0’
Termination disabled
X
term_lclk <2:0>
Programmable termination for
LCLKN and LCLKP buffers
‘000’
Termination disabled
1
term_fclk<2:0>
Programmable termination for
FCLKN and FCLKP buffers
‘000’
Termination disabled
1
term_dat <2:0>
Programmable termination for
output data buffers
‘000’
Termination disabled
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
Hex
Address
0x12
X
X
X
X
X
X
The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with
the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be
mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal
termination mode can be selected by setting the en_lvds_term bit to ‘1’. Once this bit is set, the internal termination
values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table
15 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can
vary by up to ±20% from device to device and across temperature.
28
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x0F, 0x52 – Power Mode Control
Description
Default
sleep4_ch<4:1>
Channel-specific sleep mode for
a Quad Channel setup
‘0000’
Inactive
sleep2_ch<2:1>
Channel-specific sleep mode for
a Dual Channel setup
‘00’
Inactive
sleep
Go to sleep-mode
‘0’ – Inactive
pd
Go to power-down
‘0’ – Inactive
pd_pin_cfg
<1:0>
lvds_pd_mode
Configures the PD pin function
‘00’ – PD pin invokes
power-down mode
Controls LVDS power down
mode
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
X
D4
D3
D2
D1
D0
X
X
X
X
Hex
Address
X
0x0F
X
X
X
X
‘0’ – High z-mode
X
0x52
The HMCAD1513 device has several modes for power management, from sleep modes with short start up time to
full power down with extremely low power dissipation. There are two sleep modes, both with the LVDS clocks (FCLK,
LCLK) running, such that the synchronization with the receiver is maintained. The first is a light sleep mode (sleep*_
ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down.
Setting sleep4_ch<n> = ‘1’ sets channel <n> in a Quad Channel setup in sleep mode. Setting sleep2_ch<n> = ‘1’ sets
channel <n> in a Dual Channel setup in sleep mode. This is a light sleep mode with short start up time.
Setting sleep = ‘1’, puts all channels to sleep, but keeps FCLK and LCLK running to maintain LVDS synchronization.
The start up time is the same as for complete power down. Power consumption is significantly lower than for setting
all channels to sleep by using the sleep*_ch register.
A/D Converters - SMT
Name
Setting pd = ‘1’ completely powers down the chip, including the band-gap reference circuit. Start-up time from this
mode is significantly longer than from the sleep*_ch mode. The synchronization with the LVDS receiver is lost since
LCLK and FCLK outputs are put in high-Z mode.
Setting pdn_pin_cfg<1:0> = ‘x1’ configures the circuit to enter sleep channel mode (all channels off) when the PD pin
is set high. This is equal to setting all channels to sleep by using sleep*_ch. The channels can not be powered down
separately using the PD pin. Setting pdn_pin_cfg<1:0> = ‘10’ configures the circuit to enter (deep) sleep mode when
the PD pin is set high (equal to setting sleep = ’1’). When pdn_pin_cfg <1:0> = ‘00’, which is the default, the circuit
enters the power down mode when the PD pin is set high.
Table 16. PD Pin Function
pdn_pin_cfg<1:0>
00 (default)
01 or 11
10
Effect when setting PD pin high
invoke power down
invoke light sleep mode, like sleepx_ch = ‘1111’
invoke sleep mode, like sleep = ‘1’
The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or kept alive in sleep
and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and
sleep channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z mode, and the driver is
completely powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on
during sleep and sleep channel modes.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
29
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x33, 0x2A, 0x2B, 0x34-0x37 – Programmable Gain
A/D Converters - SMT
Name
cgain_cfg
fine_gain_en
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
‘1’ – x-gain
enabled
Configures the coarse gain setting
Enable use of fine gain
X
‘0’ – Disabled
cgain4_ch1 <3:0>
Programmable coarse gain channel 1
in a Quad Channel setup
‘0000’
1x gain
cgain4_ch2 <3:0>
Programmable coarse gain channel 2
in a Quad Channel setup
‘0000’
1x gain
cgain4_ch3 <3:0>
Programmable coarse gain channel 3
in a Quad Channel setup
‘0000’
1x gain
cgain4_ch4 <3:0>
Programmable coarse gain channel 4
in a Quad Channel setup
‘0000’
1x gain
cgain2_ch1 <3:0>
Programmable coarse gain channel 1
in a Dual Channel setup
‘0000’
1x gain
cgain2_ch2 <3:0>
Programmable coarse gain channel 2
in a Dual Channel setup.
‘0000’
1x gain
fgain_branch1<6:0>
Programmable fine gain for branch1
fgain_branch2<6:0>
Programmable fine gain for branch 2
fgain_branch3<6:0>
Programmable fine gain for branch 3
fgain_branch4<6:0>
Programmable fine gain for branch 4
fgain_branch5<6:0>
Programmable fine gain for branch 5
fgain_branch6<6:0>
Programmable fine gain for branch 6
fgain_branch7<6:0>
Programmable fine gain for branch 7
fgain_branch8<6:0>
Programmable fine gain for branch 8
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
‘000 0000’
0dB gain
Hex
Address
0x33
X
X
X
X
X
X
X
X
X
0x2A
X
X
X
X
X
X
X
X
X
X
X
X
0x2B
X
X
X
X
X
X
X
X
X
X
X
0x34
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x35
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0x36
X
X
X
X
X
X
X
0x37
X
X
X
X
X
X
X
The device includes a digital programmable gain in addition to the Full-scale control. The programmable gain of each
channel can be individually set using a four bit code, indicated as cgain*<3:0>. The gain is configured by the register
cgain_cfg: when cgain_cfg equals ‘0’ a gain in dB steps is enabled as defined in Table 17, otherwise if cgain_cfg
equals ‘1’ the gain is defined by Table 18. There will be no missing codes for gain settings of 32x (30dB) or lower, due
to higher than 8 bit resolution internally.
Table 17. Gain setting – dB Step
30
cgain_cfg
cgain*<3:0>
Implemented Gain (dB)
0
0000
0
0
0001
Table 18. Gain Setting – x Step
Implemented Gain Factor
(x)
cgain_cfg
cgain*<3:0>
1
1
0000
1
0001
1.25
0
0010
2
1
0
0011
3
1
0010
2
0011
2.5
4
0
0100
4
1
0
0101
5
1
0100
0
0110
6
1
0101
5
0
0111
7
1
0110
8
0
1000
8
1
0111
10
0
1001
9
1
1000
12.5
0
1010
10
1
1001
16
1
1010
20
0
1011
11
0
1100
12
0
1101
Not used
0
1110
Not used
0
1111
Not used
1
1011
25
1
1100
32
1
1101
50
1
1110
Not used
1
1111
Not used
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
To enable the fine gain function the register bit fine_gain_en has to be activated, set to ‘1’.
See also section “Interleaving Effects and Sampling Order” on page 33.
Table 19. Fine Gain Setting
fgain_branchx<6:0>
Arithmetic Function
Implemented Gain (x)
Gain (dB)
0
1
1
1
1
1
1
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12 + 2-13) * IN
1.0077
0.0665
0
1
1
1
1
1
0
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12) * IN
1.0076
0.0655
0
1
1
1
1
0
1
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-13) * IN
1.0074
0.0644
0
1
1
1
1
0
0
OUT = (1 + 2-8 + 2-9 + 2-10 + 2-11) * IN
1.0073
0.0634
0
0
0
0
0
1
1
OUT = (1 + 2-12 + 2-13) * IN
1.0004
0.0031
0
0
0
0
0
1
0
OUT = (1 + 2-12) * IN
1.0002
0.0021
0
0
0
0
0
0
1
OUT = (1 + 2-13) * IN
1.0001
0.001
0
0
0
0
0
0
0
OUT = IN
1.0000
0.0000
1
1
1
1
1
1
1
OUT = IN
1.0000
0.0000
1
1
1
1
1
1
0
OUT = (1 - 2-13) * IN
0.9999
-0.0011
1
1
1
1
1
0
1
OUT = (1 - 2-12) * IN
0.9998
-0.0021
1
1
1
1
1
0
0
OUT = (1 - 2-12 - 2-13) * IN
0.9996
-0.0032
1
0
0
0
0
1
1
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11) * IN
0.9927
-0.0639
1
0
0
0
0
1
0
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-13) * IN
0.9926
-0.0649
1
0
0
0
0
0
1
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12) * IN
0.9924
-0.0660
1
0
0
0
0
0
0
OUT = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12 - 2-13) * IN
0.9923
-0.0670
A/D Converters - SMT
There is a digital fine gain implemented for each ADC to adjust the fine gain errors between the ADCs. The gain is
controlled by fgain_branch* as defined in Table 19. There will be no missing codes when using digital fine gain, due
to higher resolution internally.
0x24 – Analog Input Invert
Name
Description
Default
invert4_ch
<3:0>
Channel specific swapping of the analog
input signal for a Quad Channel setup
‘0000’ – IPx is
positive input
invert2_ch
<1:0>
Channel specific swapping of the analog
input signal for a Dual Channel setup
‘00’ – IPx is
positive input
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
Hex
Address
X
0x24
X
X
The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting
the bits marked invertx_ch<n> (individual control for each channel) causes the inputs to be swapped. INx would then
represent the positive input, and IPx the negative input.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
31
HMCAD1513
v00.0414
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
0x25 to 0x27, 0x45 – LVDS Test Patterns
Name
Description
Default
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hex
Address
en_ramp
Enables a repeating full-scale ramp
pattern on the outputs
‘000’
Inactive
X
0
0
dual_custom_pat
Enable the mode wherein the output
toggles between two defined codes
‘000’
Inactive
0
X
0
single_custom_pat
Enables the mode wherein the output
is a constant specified code
‘000’
Inactive
0
0
X
bits_custom1
<7:0>
Bits for the single custom pattern and
for the first code of the dual custom
pattern. <0> is the LSB
0x00
X
X
X
X
X
X
X
X
0x26
bits_custom2
<7:0>
Bits for the second code of the dual
custom pattern
0x00
X
X
X
X
X
X
X
X
0x27
pat_deskew
pat_sync
0x25
Enable deskew pattern mode
‘00’ – Inactive
0
X
Enable sync pattern mode
‘00’ – Inactive
X
0
0x45
To ease the LVDS synchronization setup of HMCAD1513, several test patterns can be set up on the outputs. Normal
ADC data are replaced by the test pattern in these modes:
Setting en_ramp to ‘1’ sets up a repeating full-scale ramp pattern on all data outputs. The ramp starts at code zero
and is increased 1 LSB every clock cycle, see Figure 12. It returns to zero code and starts the ramp again after reaching the full-scale code.
A constant value can be set up on the outputs by setting single_custom_pat to ‘1’, and programming the desired
value in bits_custom1<7:0>. In this mode, bits_custom1<7:0> replaces the ADC data at the output, and is controlled
by LSB-first and MSB-first modes (msb_first in register 0x46) in the same way as normal ADC data are.
The device may also be set up to alternate between two codes by programming dual_custom_pat to ‘1’. The two
codes are the contents of bits_custom1<7:0> and bits_custom2<7:0>, see Figure 13.
Two preset patterns can also be selected:
en_ramp = 1
Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with a pattern consisting of alternating
FCLKP
zeros and ones - MSB will be a zero.
FCLKN
N+1
Sync pattern: Set using pat_sync, the normal ADC word is in this mode
pattern
Dx1A replaced Nby a fixed synchronization
N+1
where the output word is split in two and the upper part of the word is Dx1B
ones and theN lower part is zeros.
Dx2A
Dx2B
Note: Only one of the above patterns should be selected at the same time.
Dx4B
N
N+1
en_ramp = 1
dual_custom_pat = 1
FCLKP
FCLKN
N
Dx1A
Dx1B
N
Figure 11.
N+1
N+1
Dx2A
Dx2B
Dx4B
N
N+1
Figure 12. LVDS test pattern en_ramp
(two subsequent FCLK frames)
dual_custom_pat = 1
FCLKP
FCLKN
DxnA
bits_custom1
bits_custom2
DxnB
bits_custom2
bits_custom1
Figure 13. LVDS test pattern dual_custom_pat
(two subsequent FCLK frames)
FCLKP
FCLKN
32
DxnA
bits_custom1
bits_custom2
DxnB
bits_custom2
bits_custom1
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Theory of Operation
HMCAD1513 utilizes a LVDS output, described in
‘Register Description – LVDS Output Configuration
and Control’. The clocks needed (FCLK, LCLK) for the
LVDS interface are generated by an internal PLL.
The HMCAD1513 operates from one clock input,
which can be differential or single ended. The sampling clocks for each of the four channels are generated from the clock input using a carefully matched
clock buffer tree. Internal clock dividers are utilized
to con­trol the clock for each ADC during interleaving.
The clock tree is controlled by the Mode of operations.
HMCAD1513 uses internally generated references.
The differential reference value is 1.0 V. This results in
a differential input of −1.0 V to correspond to the zero
code of the ADC, and a differential input of +1.0 V to
cor­respond to the full-scale code (code 255).
The ADC employs a Pipeline converter architecture.
Each Pipeline Stage feeds its output data into the digi­
tal error correction logic, ensuring excellent differential
linearity and no missing codes.
HMCAD1513 operates from two sets of supplies and
grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by DVDD and DVSS. AVSS and DVSS are electrically connected on-chip. AVSS and DVSS are internally connected.
Interleaving Effects and Sampling Order
Interleaving ADCs will generate interleaving artifacts
caused by gain, offset and timing mismatch between
the ADC branches. The design of HMCAD1513 has
been optimized to minimize these effects. It is not
possible, though, to eliminate mismatch completely,
such that additional compensation may be needed,
especially when using high digital gain settings. The
internal digital fine gain control may be used to compensate for gain errors between the ADC branches.
Due to the optimization of HMCAD1513 there is not
a one-to-one correspondence between the sampling
order, LVDS output order and the branch number. Table 20 and 24 give an overview of the corresponding
branches, LVDS outputs and sampling order for the
different high speed modes.
Table 20. Quad Channel Mode
Channel #
1
2
3
4
Sampling
Order
LVDS Output
Fine Gain
Branch
1
D1A
1
2
D1B
2
1
D2A
3
2
D2B
4
1
D3A
5
2
D3B
6
1
D4A
7
2
D4B
8
A/D Converters - SMT
HMCAD1513 is a multi Mode high-speed, CMOS ADC,
consisting of eight ADC branches, configured in different channel modes, using interleaving to achieve high
speed sampling. For all practical purposes, the device
can be considered to contain four ADCs. Fine gain is
adjusted for each of the eight branches separately.
Table 21. Dual Channel Mode
Channel #
1
2
Sampling
Order
LVDS Output
Fine Gain
Branch
1
D1A
1
2
D1B
3
3
D2A
2
4
D2B
4
1
D3A
5
2
D3B
7
3
D4A
6
4
D4B
8
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
33
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
Recommended Usage
Preferably, the VCM output should be used as reference to set the common mode voltage.
A/D Converters - SMT
Analog Input
The analog input to HMCAD1513 ADC is a switched
capacitor sample-and-hold amplifier optimized for differential operation.
Operation at common mode voltages at mid supply is
recommended even if performance will be good for
the ranges specified. The VCM pin provides a voltage
suitable as common mode voltage reference. The internal buffer for the VCM voltage can be switched off,
and driving capabilities can be changed programming
the ext_vcm_bc<1:0> register.
S
H
IP
CS
S
S
CS
S
H
IN
Figure 14. Input configuration
C1
IN
Figure 14 shows a simplified drawing of the input network. The signal
source must have sufficiently low
C2
output impedance to charge
the sampling capacitors
R2
R1
within one clock cycle.
C3
Cin
VCM
Rin
ADC
R1
C2
In Dual channel
mode, Input 1 and 4 should be used
R2
for full CrossTalk performance. If input 2 or 3 is utilized
in Dual channel mode, please refer to Quad Channel
CrossTalk.
Figure 15. DC coupled input
An RC shunt to ground (R3 and C3) is inserted to optimize the direct sampling input of the ADC. For wide
band applications the recommended values are 20 Ω
for R3 and 10 pF for C3. For applications optimized for
frequencies lower than 150 MHz, C3 can be increased
to reduce the ADC driver noise bandwidth.
A series resistor, R2 is inserted to ensure the pass
band flatness for the ADC input. The recommended
value for R2 is 10 Ω. The value for R2 depends on the
distance between ADC driver and ADC. For wide band
applications it is highly recommended to minimize the
distance between the ADC driver and the ADC input
pins, and to keep the value of R2 low.
The ADC VCM output voltage is decoupled to ground
through C4. The recommended value for C4 is 10 nF
per channel.
AC-Coupling
DC-Coupling
For DC coupling the common mode input voltage from
the ADC driver must match the VCM,IN specification given in the Electrical Specifications on page 4. Preferably, the ADC common mode output voltage (VCM pin)
should be used as reference to set the common mode
input voltage. The input amplifier (e.g. HMC1023LP5E)
could be inside a companion chip or it could be a dedicated amplifier.
34
Figure 16. Transformer coupled input
For ADC drivers not optimized to drive the 0.9 V VCM in
the ADC from a common ground, VCM alignment with
ADC can be achieved by using a negative voltage for
VSS in the ADC driver.
A balun configuration is recommended for high performance AC-coupled input networks. Figure 16 shows a
recommended configuration utilizing this configuration.
The balun termination resistors (R1) define the impedance of the input network. The recommendations for
R2, R3, C3 and C4 are as for DC coupling.
Figure 15 shows a recommended configuration for
DC-coupling. Note that the common mode input voltage must be controlled according to specified values.
Make sure that a transformer with sufficient linearity is
selected, and that the bandwidth of the transformer is
appropriate. It is important to minimize second order
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
distortion. This type of transformer coupled input is the
preferred configuration to optimize Signal to Noise Ratio. A differential amplifier or differential Variable Gain
Amplifier may result in higher linearity since they most
often are less dependent on a pure resistive load. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be
taken into account during PCB layout.
close to the ADC clock pins as possible. For CMOS
inputs, the CLKN pin should be connected to ground,
and the CMOS clock signal should be connected to
CLKP. CMOS input clock is not recommended above
200 MHz clock frequency. For differential sine wave
clock input the amplitude must be at least ±0.8 Vpp.
No additional configuration is needed to set up the
clock source format.
Due to the switched nature of the ADC input stage,
there will be some kick-back going from the ADC input
and back into the driver. If these kick-backs are not terminated properly at the source side, they are reflected
and will add to the input signal at the ADC input. This
could reduce the ADC performance. To avoid this effect, the source must effectively terminate the ADC
kick-backs, or the traveling distance should be very
short.
The quality of the input clock is important for highspeed ADCs. The contribution to SNR from clock jitter
with a full scale signal at a given frequency is shown
in equation 1.
Differential amplifiers are often suited to terminate the
kick-back efficiently. It is of utmost importance that the
amplifier is placed close to the ADC input to minimize
any transmission line effects on the trace from the amplifier to the ADC input. The bandwidth in this node
should also be maximized to allow the kick-back to
settle within the available time.
In Figure 16 the ADC common mode setup for ACCoupling is shown. By connecting the termination resistors (R1) to the ADC VCM output, the ADC Common mode voltage will be set up correctly given an
AC-coupling capacitor (C1) to control the lower passband frequency.
The value of C1 must be defined based on the requirement to the high-pass cut-off frequency.
Note that Start Up Time from Sleep Mode and Power
Down Mode will be affected by this filter as the time
required to charge the series capacitors is dependent
on the filter cut-off frequency.
Clock Input and Jitter Considerations
Typically high-speed ADCs use both clock edges to
generate internal timing signals. In HMCAD1513 only
the rising edge of the clock is used.
The input clock can be supplied in a variety of formats. The clock pins are AC-coupled internally, hence
a wide common mode voltage range is accepted.
Differential clock sources such as LVDS, LVPECL or
differential sine wave can be utilized. LVDS/LVPECL
clock signals must be appropriately terminated as
SNRjitter = –20 · log (2 · π · fIN · Tjrms)(1)
where fIN is the signal frequency, and Tjrms is the rootmean-square (rms) ADC aperture jitter measured in
seconds. The rms jitter is the total of all jitter sources
including the clock generation circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the
clock jitter. This can be obtained by using precise and
stable clock references (e.g. Hittite PLL/VCO solutions, such as HMC1035LP6GE) and make sure the
clock distribution is well controlled. It might be advantageous to use analog power and ground planes
to ensure low noise on the supplies to all circuitry in
the clock distribution. It is of utmost importance to
avoid crosstalk between the ADC output bits and the
clock and between the analog input signal and the
clock since such crosstalk often results in harmonic
distortion.
A/D Converters - SMT
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
The jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LVDS or LVPECL clock
with fast edges. CMOS and sine wave clock inputs will
result in slightly degraded jitter performance.
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Using PLL/VCO as Clock Source
When the direct ADC clock generation is not available,
a high performance PLL/VCO should be utilized to generate a low jitter master clock. This should be applied to
the ADC either directly or through a fan out buffer.
The recommended PLL/VCO for HMCAD1513 is
HMC1035LP6GE. The recommended fan out buffer is
HMC987LP5E.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
35
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Definition of Terms
Aperture delay (t AD) The delay difference between
Analog and Clock inputs to sampling.
tAD = Tsd – Tid, where
Tsd delay from Clock input to sampling, and
Tid delay from Analog input to sampling.
Aperture jitter (tjrms) The sample-to-sample variation
in Aperture delay.
Cross Talk (Xtlk) Crosstalk is the signal coupling between the ADC channels, and is measured by applying full scale signals to both an adjacent channel and
to the channel of interest. The crosstalk is the ratio of
power in between the signal applied to the adjacent
channel and the signal power at the channel of interest
that origin from the adjacent channel.
Decibel – carrier (dBc) A unit where the parameter
is measured by comparing to the applied fundamental
(or carrier) power in the given test.
Full Scale Range (FSR) The voltage difference at the
analog input of the ADC between the voltage that will
generate the maximum digital output code, and the
voltage that will generate the minimum digital output
code.
When referring to deviation in Full Scale Range this
means that the analog voltages giving max/min output
code are different from the theoretical values. A Full
Scale Range fundamental is a sine wave where the
lowest value gives minimum output code and the highest value gives maximum output code.
Noise Power Bandwidth (NoiseBW) The analog input frequency where the power of the fundamental is
reduced by 3 dB compared to the low-frequency value.
Gain error (G abs) The deviation from ideal Full Scale
Range. This parameter is independent from Grel.
Gain flatness The input frequency range where the
Gain variation is within the specified number of dB.
Decibel – Full Scale (dBFS) A unit where the parameter is measured by comparing to the theoretical maximum fundamental power based on Full Scale Range.
Gain matching (Grel) The mismatch in Full Scale
Range between the ADC channels. This parameter is
independent from Gabs.
Differential Non-Linearity (DNL) The DNL is the deviation from the ideal voltage that causes a change of
one single code (1 LSB). The DNL plot is a diagram
showing this deviation for all the codes in the ADC.
The DNL parameter is the worst case value on this
diagram.
Integral Non-Linearity (INL) The INL is the deviation
of the ADC transfer function from an ideal straight line.
The INL plot is this deviation generated with the best
fit method for the ADC Full Scale range. The INL parameter is the worst case value on this line.
Effective Number of Bits (ENOB) Measures the converter performance in terms of number of bit resolution, based on a perfect ADC with quantization noise.
ENOB = (SNDR – 1.76)/6.02.
Full Power Bandwidth (FPBW) The analog input
frequency where the power of the fundamental is reduced by 3 dB compared to the low-frequency value.
Signal to Noise Ratio (SNR) The ratio of the power of
the fundamental to the power of the noise measured
in dB. SNR excludes DC, harmonics and interleaving
spurs.
Signal to Noise and Distortion Ratio (SNDR) The
ratio of the power of the fundamental to the power of
the noise and distortion measured in dB. SNDR excludes DC.
Spurious Free Dynamic Range (SFDR) The ratio of
the power of the fundamental to the power of the highest harmonic or spurious component.
Document Changes
Version
v00.0414
36
Comment
Initial release
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
HMCAD1513
v00.0414
8-BIT A-TO-D CONVERTER (ADC)
DUAL 500 MSPS / QUAD 250 MSPS
A/D Converters - SMT
Outline Drawing
NOTES:
1. LEADFRAME MATERIAL: COPPER ALLOY
2. DIMENSIONS ARE IN INCHES [MILLIMETERS].
3. LEAD SPACING TOLERANCE IS NON-CUMULATIVE
4. PAD BURR LENGTH SHALL BE 0.15mm MAXIMUM. PAD BURR HEIGHT SHALL BE 0.05mm MAXIMUM.
5. PACKAGE WARP SHALL NOT EXCEED 0.05mm.
6. ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND.
7. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN.
Table 22. 7x7 mm QFN 48 Pin (LP7) Dimensions
Symbol
Millimeter
Inch
Min
Typ
Max
Min
Typ
Max
A
0.8
0.9
1
0.031
0.035
0.039
A1
0
0.02
0.05
0
0.001
0.002
A2
b
0.2
0.19
0.25
0.008
0.31
0.007
0.01
0.012
D, D1
6.9
7
7.1
0.272
0.276
0.280
D2
5.15
5.3
5.41
0.203
0.209
0.213
L
0.4
e
0.44
F
0.20
0.50
0.016
0.46
0.017
0.020
0.022
0.008
Package Information
Part Number
Package Body Material
Lead Finish
MSL [1]
Package Marking [2]
HMCAD1513
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
Level 2A
HAD1513
XXXXX
[1] MSL, Peak Temp: The moisture sensitivity level rating classified according to the JEDEC industry standard and to peak solder temperature.
[2] Lot number XXXXX
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: +1 978-250-3343
Fax: +1 978-250-3373
Order On-line at www.hittite.com
Application Support: [email protected]
37