HANBit HSD64M72D18RP Synchronous DRAM Module 512Mbyte (64Mx72bit), DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Part No. HSD64M72D18RP GENERAL DESCRIPTION The HSD64M72D18RP is a 64M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 64M x 4 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD64M72D18RP is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES • Part Identification HSD64M72D18RP-10L : 100MHz (CL=3) HSD64M72D18RP-10 : 100MHz (CL=2) HSD64M72D18RP-13 : 133MHz (CL=3) • Burst mode operation • Auto & self refresh capability (8192 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system cloc • serial presence detect with EEPROM • The used device is 16M x 4bit x 4Banks SDRAM URL:www.hbe.co.kr REV.1.0 (August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP PIN ASSIGNMENT PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 Vss 29 2 DQ0 30 DQM1 57 DQ18 /CS0 58 DQ19 85 Vss 113 DQM5 141 DQ50 86 DQ32 114 */CS1 142 DQ51 3 DQ1 31 NC 59 VDD 87 DQ33 115 /RAS 143 VCC 4 5 DQ2 32 Vss 60 DQ20 88 DQ3 33 A0 61 NC 89 DQ34 116 Vss 144 DQ52 DQ35 117 A1 145 NC 6 VCC 34 A2 62 NC(*VREF) 90 VCC 118 A3 146 NC(*VREF) 7 DQ4 35 A4 63 *CKE1 8 DQ5 36 A6 64 Vss 91 DQ36 119 A5 147 REGE 92 DQ37 120 A7 148 Vss 9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53 10 DQ7 38 A10 11 DQ8 39 BA1 66 DQ22 94 DQ39 122 BA0 150 DQ54 67 DQ23 95 DQ40 123 A11 151 DQ55 12 Vss 40 VCC 13 DQ9 41 VCC 68 Vss 96 Vss 124 VCC 152 Vss 69 DQ24 97 DQ41 125 *CLK1 153 DQ56 14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 A12 154 DQ57 15 DQ11 16 DQ12 43 Vss 71 DQ26 99 DQ43 127 Vss 155 DQ58 44 NC 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 /CS2 73 VCC 101 DQ45 129 */CS3 157 VCC 18 VCC 46 DQM2 74 DQ28 102 VCC 130 DQM6 158 DQ60 19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61 20 DQ15 48 NC 76 DQ30 104 DQ47 132 *A13 160 DQ62 21 CB0 49 VCC 77 DQ31 105 CB4 133 VCC 161 DQ63 22 CB1 50 NC 78 Vss 106 CB5 134 NC 162 Vss 23 VCC 51 NC 79 *CLK2 107 Vss 135 NC 163 *CLK3 24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC 25 NC 53 CB3 81 WP 109 NC 137 CB7 165 **SA0 26 VCC 54 Vss 82 **SDA 110 VCC 138 Vss 166 **SA1 27 /WE 55 DQ16 83 **SCL 111 /CAS 139 DQ48 167 **SA2 28 DQM0 56 DQ17 84 VCC 112 DQM4 140 DQ49 168 VCC * These pins are not used in this module ** These pins should be NC in the system which does not support SPD *Pin Names A0~A12: Address input (Multiplexed) DQ0~DQ63: Data input/output CLK0~CLK3: Clock input /CS0~/CS3: Chip select input /CAS: Coulmn address strobe DQM0~7: DQM VSS: Ground BA0~BA1: Select bank CB0~7: Check bit (Data-in/data-out) CKE0~ CKE1: Clock enable input /RAS: Row address strobe /WE: Write enable VCC: Power supply(3.3V) *VREF:Power supply for reference REGE: Register enable SDA: Serial data I/O SCL: Serial clock SA0~2: Address in EEPROM WP: Write protection NC: No connection URL:www.hbe.co.kr REV.1.0 (August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP FUNCTIONAL BLOCK DIAGRAM URL:www.hbe.co.kr REV.1.0 (August.2002) 3 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9,CA11 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. /CAS Column address strobe /WE Write Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. enable Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. DQM0 ~ 7 REGE Data input/output Makes data output Hi-Z, tsHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) Register enable The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. The inputs are strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to VDD through 10K ohm register on PCB. So if REGE of module is floating, this module will be operated as registerd mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0~7 Check bit Check bits for ECC. WP Write Protection WP pin is connected to Vcc. When WP is “high”, EEPROM Programming will be inhibited and the entire memory will be write-protected. Vcc /VSS Power Power and ground for the input buffers and the core logic. supply/ground URL:www.hbe.co.kr REV.1.0 (August.2002) 4 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 18W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCC. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 3 CAPACITANCE (Vcc = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Input capacitance(A0~A12) CIN1 15 pF Input capacitance(/RAS, /CAS,/WE) CIN2 15 pF Input capacitance(CKE0) CIN3 20 pF Input capacitance(CLK0) CIN4 15 pF Input capacitance(/CS0~/CS3) CIN5 15 pF Input capacitance(DQM0~DQM7) CIN3 15 pF Input capacitance(BA0~BA1) CIN3 15 pF Data input/output capacitance (DQ0 ~ DQ63) COUT 16 pF Data input/output capacitance (CB0 ~ CB7) COUT1 16 pF URL:www.hbe.co.kr REV.1.0 (August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70°C) TEST PARAMETER VERSION NOT SYMBOL UNIT CONDITION -13 -10 -10L 2,660 2,480 2,480 E Burst length = 1 Operating current (One bank active) ICC1 tRC ≥ tRC(min) mA 1,3 368 mA 3 38 mA 3 mA 3 mA 3 mA 3 IO = 0mA Precharge standby current ICC2P in power-down mode ICC2PS CKE ≤ VIL(max), tCC=10ns CKE & CLK ≤ VIL(max), tCC=∞ CKE ≥ VIH(min) Precharge standby current ICC2N /CS ≥ VIH(min), tcc=10ns 638 Input signals are changed in one time during 20ns non power-down mode CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tcc=∞ 254 Input signals are stable Active standby current in power-down mode ICC3P ICC3PS CKE ≤ VIL(max), tcc=10ns 458 CKE&CLK ≤ VIL(max) 110 tcc=∞ CKE≥VIH(min), Active standby current in ICC3N /CS≥VIH(min), tcc=10ns 890 Input signals are changed non power-down mode one time during 20ns (One bank active) CKE≥VIH(min) ICC3NS CLK ≤VIL(max), tcc=∞ 452 Input signals are stable IO = 0 mA Operating current (Burst mode) Page burst ICC4 3,020 2,570 2,570 mA 1,3 4,460 4,280 4,280 mA 2,3 mA 3 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ 0.2V Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1PLL & 2 Drive Ics. 4. Unless otherwise noticed, input swing level is CMOS(V IH/VIL= VCCQ/VSSQ). URL:www.hbe.co.kr REV.1.0 (August.2002) 6 404 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 +3.3V 1200Ω DOUT 870Ω Vtt=1.4V 50pF* 50Ω VOH (DC) = 2.4V, IOH = -2mA DOUT VOL (DC) = 0.4V, IOL = 2mA Z0=50Ω 50pF (Fig. 1) DC output load vss (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 20 20 ns 1 /RAS to /CAS delay tRCD(min) 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 ns 1 tRAS(min) 45 50 50 ns 1 Row active time tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to Active delay 100 65 ns ns 1 2 CLK 2,5 tDAL(min) 2CLK + 20ns - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 CAS latency=3 70 70 2 Number of valid output data URL:www.hbe.co.kr REV.1.0 (August.2002) - 7 1 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 PARAMETER MIN CLK cycle CAS latency=3 CAS latency=2 CLK to valid CAS latency=3 -10L MIN MAX 10 1000 MIN CAS latency=2 Output data CAS latency=3 10 3 1000 ns 1 ns 1,2 ns 1,2 12 6 6 6 7 3 3 3 3 tOH CAS latency=2 NOTE 10 1000 5.4 UNIT MAX tSAC output delay hold time MAX 7.5 tCC time -10 SYMBOL CLK high pulse width tCH 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 ns 3 Input setup time tSS 1.5 2 2 ns 3 Input hold time tSH 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 5.4 6 6 ns 1 6 7 ns 1 tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered i.e., [(tr + tf)/2-1]ns should be added to the parameter. URL:www.hbe.co.kr REV.1.0 (August.2002) 8 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP SIMPLIFIED TRUTH TABLE CK E n-1 COMMAND Register Mode register set Auto refresh Self Refresh refres h Entry Exit Bank active & row addr. Read & Auto column disable addres s H H CKE n /C S /R A S /C A S /W E D Q M X L L L L X OP code L L L H X X L H H H H X X X X X L L H H H L L H H X X BA 0,1 V precharge Auto column disable addres Auto s enable H X L H L H X Burst Stop Bank selection e All banks Clock suspend or active power down Precharge power down mode X H X Entry H L Exit L H Entry Exit H L L X H L DQM H No operation command H L H L H H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H X 3 3 4 (A0 ~ 4,5 Column 4 Address V X X 3 A9),A11 (A0 H H Precharg L 3 Column L X 1,2 Address H H NOTE Row address V precharge precharge A11 A9~A0 L Auto precharge eable Write & A10/ AP ~ A9),A11 X V L X H 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) URL:www.hbe.co.kr REV.1.0 (August.2002) 9 4,5 HANBit Electronics Co.,Ltd. 7 HANBit HSD64M72D18RP TIMING DIAGRAMS td, tr = Delay of register (74LVC162835) Notes : 1.In case of module timing, command cycles 1CLK with respect to external input timing at the address and input signal because of the buffering in register (74LVC162835). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1 clock after write command in external timing because D IN is issued directly to module. URL:www.hbe.co.kr REV.1.0 (August.2002) 10 HANBit Electronics Co.,Ltd. HANBit HSD64M72D18RP PACKAGING INFORMATION Unit : inch [mm] Front – Side TOLERANCE : ±0.008 [ ±0.20 ] ORDERING INFORMATION Part Number Density Org. HSD64M72D18RP-10 512MByte 64M x 72 HSD64M72D18RP-10L 512MByte 64M x 72 HSD64M72D18RP-13 URL:www.hbe.co.kr REV.1.0 (August.2002) 512MByte 64M x 72 Package 168 Pin-DIMM /Low Profile 168 Pin-DIMM /Low Profile 168 Pin-DIMM /Low Profile 11 Ref. Vcc 8K 3.3V 8K 3.3V 8K 3.3V MODE MAX.frq Registered 100MHz /ECC CL=2 Registered 100MHz /ECC CL=3 Registered 133MHz /ECC CL=3 HANBit Electronics Co.,Ltd.