Aerospace Electronics FIFO—SOI HX6409 HX6218 HX6136 FEATURES • 1K x 36, 2K x 18, 4K x 9 Organizations OTHER • Fabricated with RICMOS™ IV Silicon on Insulator (SOI) 0.8 µm Process (Leff = 0.65µm) • Read/Write Cycle Times <35 ns (-55° to 125°C) • Expandable in Width RADIATION • Supports Free-Running 50% Duty Cycle Clock • Total Dose Hardness through 1x106 rad(SiO2) • Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags • Neutron Hardness through 1x1014 cm-2 • Parity Generation/Checking • Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s • Fully Asynchronous with Simultaneous Read and Write Operation • Dose Rate Survivability through 1x1011 rad(Si)/s • Output Enable (OE) • Soft Error Rate of <1x10-10 upsets/bit-day • CMOS or TTL Compatible I/O • No Latchup • Single 5 V ± 10% Power Supply • Various Flat Pack Options GENERAL DESCRIPTION The HX6409, HX6218, and HX6136 are high speed, lowpower, first-in first-out memories with clocked read and write interfaces. The HX6409 is a 4096 word by 9 bit memory array, the HX6218 is a 2048 word by 18 bit memory array, and the HX6136 is a 1024 word by 36 bit memory array. The FIFOs support width expansion while depth expansion requires external logic control using state machine techniques. Features include programmable parity control, an empty/full flag, a quarter/three quarter full flag, a half full flag and an error flag. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have separate input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a free running clock (CKW) and a write enable pin ENW . When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a freerunning read clock (CKR) and a read enable pin (ENR ). In addition, the three FIFOs have an output enable pin (OE ) and a master reset pin (MR ). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 30 MHz are achievable in the three configurations. Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. The FIFO is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environments. The SOI RICMOS™ IV process is a 5-volt, SIMOX CMOS technology with a 150 Å gate oxide and a minimum drawn feature size of 0.8 µm, (0.65 µm effective gate array—Leff). Additional features include tungsten via plugs, Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability. Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com HX6409/HX6218/HX6136 LOGIC BLOCK DIAGRAM D: 0 - 8 D: 0 - 17 D: 0 - 35 Input Register CKW ENW Parity Program Register Parity Write Control HF E/F QF/TQF EF_Fault Flag Logic Write Pointer Memory Array 4096 x 9 2048 x 18 1024 x 36 Read Pointer Reset Logic MR Tri-State Output Register Read Control OE CKR ENR Q: 0 - 8 Q: 0 - 17 Q: 0 - 35 FLAG DECODE TABLE Word Count EF_Fault E/ F QF/TQF HF State 4K x 9 2K x 18 1K x 36 0 0 0 1 Empty Fault (Enabled Read when Empty) 0 0 0 1 0 0 1 Empty 0 0 0 1 1 0 1 Less than or Equal to 1/4 Full 1 to 1024 1 to 512 1 to 256 1 1 1 1 Less than or Equal to 1/2 Full 1025 to 2048 513 to 1024 257 to 512 1 1 1 0 Greater that 1/2 Full 2049 to 3071 1025 to1535 513 to 767 1 1 0 0 Greater than or Equal to 3/4 Full 3072 to 4095 1536 to 2047 768 to 1023 1 0 0 0 Full 4096 2048 1024 0 0 0 0 Full Fault (Enabled Write when Full) 4096 2048 1024 2 HX6409/HX6218/HX6136 SIGNAL DEFINITIONS Signal Name I/O Description D: 0 - 35 I Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when ENW is active and the FIFO is not full. Q: 0 - 35 O Data Outputs: Data Outputs are read out of the FIFO memory and updated on the rising edge of CKR when ENR is active and the FIFO is not Empty. The Data Outputs are in a high impedance state if OE is not active. ENW I Enable Write: An active low signal that enables the write of the Data Inputs on the CKW rising edge (if FIFO is not full). ENR I Enable Read: An active low signal that enables the read and update of the Data Outputs on the CKR rising edge (if FIFO is not empty). CKW I Write Clock: The rising edge clocks data into the FIFO when ENW is low (active). On the rising edge, this signal also updates the Half Full, 3/4 Full, Full, and Full Fault Flags. CKR I Read Clock: The rising edge clocks data out of the FIFO when ENR is low (active). On the rising edge, this signal also updates the 1/4 Full, Empty, and Empty Fault Flags. HF O Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is greater than half full. E/ F O Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated on the rising edge of CKW. QF/TQF O 1/4 Full or 3/4 Full Flag: 1/4 Full is updated on the rising edge of CKR, and 3/4 Full is updated on the rising edge of CKW. 1/4 Full signifies 256 or less words in the 1K x 36 FIFO and 3/4 Full signifies 256 words or less until a full condition. EF_Fault O Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault condition is detected, the Fault Flag remains latched until the empty or full condition is removed. MR I Master Reset: Active low signal which, when active, resets device to empty condition. OE I Output Enable: Active low signal which, when active, enables low impedance Data Outputs, Q: 0 - 35. PROGRAMMABLE PARITY OPTIONS D2 D1 D0 Conditions O X X Parity Disabled I O O Generate Even Parity, Q8, Q17, Q26, Q35 I O I Generate Odd Parity, Q8, Q17, Q26, Q35 I I O Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal I I I Check for Odd Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal 3 HX6409/HX6218/HX6136 RADIATION CHARACTERISTICS Total Ionizing Radiation Dose All FIFO configurations will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T = 125°C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and product using 10 KeV X-ray and radiation sources. Transistor gate threshold shift correlations have been made between 10 KeV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Each FIFO will meet any functional or electrical specification after exposure to a radiation pulse of ≤50 ns duration up to 1x1011 rad(Si)/s, when applied under recommended operating conditions. Note the current conducted during the pulse by the inputs, outputs and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation Each FIFO configuration will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Transient Pulse Ionizing Radiation Soft Error Rate Each FIFO configuration is capable of writing, reading and retaining stored data during and after exposure to a transient ionizing radiation pulse of <50 ns duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is ≤10%), it is suggested that stiffening capacitance be placed near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitor of 0.7 nH per part. If there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. This FIFO configuration has a soft error rate (SER) performance of <1x10-10 upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment. Latchup This FIFO configuration will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX substrate with its oxide isolation ensure latchup immunity. RADIATION-HARDNESS RATINGS (1) Parameter Units Limits (2) Test Conditions Total Dose ≥1x106 rad(SiO2) TA=25°C Transient Dose Rate Upset ≥1x109 rad(Si)/s Pulse width ≤50 ns Transient Dose Rate Survivability ≥1x1011 rad(Si)/s Soft Error Rate <1x10-10 upsets/bit-day Neutron Fluence ≥1x10 14 N/cm2 (1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C. 4 Pulse width ≤50 ns, X-ray, VDD=6.0 V, TA=25°C TA=125°C, Adams 90% worst case environment 1 MeV equivalent energy, Unbiased, TA=25°C HX6409/HX6218/HX6136 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter Min Max Units VDD Supply Voltage Range (2) -0.5 7.0 V VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V TSTORE Storage Temperature (Zero Bias) -65 150 °C TSOLDER Soldering Temperature (5 Seconds) 270 °C PD Maximum Power Dissipation (3) 2.5 W IOUT DC or Average Output Current 25 mA VPROT ESD Input Protection Voltage (4) ΘJC Thermal Resistance (Jct-to-Case) TJ Junction Temperature 2000 V 5 °C/W 175 °C (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) FIFO power dissipation (IDDSB + IDDOP) plus FIFO output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab. RECOMMENDED OPERATING CONDITIONS Description Parameter Symbol Min Typ Max Units VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V TA Ambient Temperature -55 25 125 °C VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V CAPACITANCE (1) Symbol Parameter Typical (1) Worst Case Min Units Test Conditions Max CI Input Capacitance 7 pF VI=VDD or VSS, f=1 MHz CO Output Capacitance 9 pF VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only. DATA RETENTION CHARACTERISTICS Symbol Parameter VDR Data Retention Voltage IDR Data Retention Current Typical (1) Worst Case (2) Min 2.5 V 500 (1) Typical operating conditions: TA= 25°C, pre-radiation. (2) Worst case operating conditions: TC= -55°C to +125°C, post total dose at 25°C. 5 Units Test Conditions Max µA NCS=VDR VI=VDR or VSS NCS=VDD=VDR VI=VDR or VSS HX6409/HX6218/HX6136 DC ELECTRICAL CHARACTERISTICS Symbol VIH Test Parameters Input High Voltage VIL Input Low Voltage VOH1 High Output Voltage Worst Case (1) Min Max 0.7xVDD — 2.2 — 0.3xVDD 0.8 3.5 — VOH2 High Output Voltage VDD-0.4 — V VOL Low Output Voltage — 0.4 V II Input Leakage Current -1.0 +1.0 µA IOZL IOZH Output OFF, High Z Current -10.0 +10.0 µA IDDSB Standby Power Supply Current (2) — 1 mA IDDOP Operating Power Supply Current (2) — 7 mA IDDSB Standby Power Supply Current (2) — 40 mA IDDOP Operating Power Supply Current (2) — 280 mA CMOS TTL CMOS TTL Units V Conditions VDD=5.5V V VDD=4.5V V VDD=4.5V IOH=-4.0ma VDD=4.5V IOH=-100µa VDD=4.5V IOL=4.0ma VDD=5.5V VIN=0V or VDD TC=-55°C TO +125°C OE>VIH, VSS<VO<VDD VIN=0V or VDD CLK(s)=1 MHz VIN=0V or VDD CLK(s)=1 MHz VIN=0V or VDD CLK(s)=40MHz VIN=0V or VDD CLK(s)=40MHz (1) Worst case operating conditions: VDD =4.5 V to 5.5 V, TC=-55°C to +125°C, post total dose at 25°C. (2) Standby current for the device includes the Read Clock (CKR) and Write Clock (CKW) only. Both the Read Enable (ENR ) and Write Enable (ENW ) are disabled (ENR , ENW =Vdd). For operating currents, ENR and ENW are enabled (=0.0 V) and data inputs are switching at one half the clock speed between 0.0 V and VDD. 2.9 V Vref1 + - Valid high output 249Ω DUT output Vref2 + - Tester Equivalent Load Circuit 6 Valid low output HX6409/HX6218/HX6136 AC TIMING CHARACTERISTICS (1) Worst Cast (2) —55•C to 125°C Symbol Test Parameter Min Max Units TCKW Write Clock Cycle 24 — ns TCKR Read Clock Cycle 34 — ns TCKH Clock High Read 24 — ns TCKH Clock High Write 14 — ns TCKL Clock Low 10 — ns TA Data Access Time — 30 ns TOH Previous Output Data Hold After Rd High 2 — ns TFH Previous Flag Hold After Rd/Wr High 2 — ns TSD Data Set-UP 9 — ns THD Data Hold 4 — ns TSEN Enable Set-UP 8 — ns THEN Enable Hold 2 — ns TOE OE Low to Output Data Valid — 10 ns TOLZ OE Low to Output Data in Low Z 1 — ns TOHZ OE High to Output Data in High Z — 10 ns TFD Flag Delay — 17 ns TSKEW1 Opposite Clock after Clock (3) 0 — ns TSKEW2 Opposite Clock before Clock (4) 25 — ns TPMR Master Reset Pulse Width (Low) 25 — ns TSCMR Last Valid Clock Low Set-up to Master Reset Low 0 — ns TOHMR Data Hold from Master Reset Low 2 — ns TMRR Master Reset Recovery 8 — ns TMRF Master Reset High to Flags Valid — 17 ns TAMR Master Reset High to Data Outputs Low — 17 ns TSMRP Parity Program Mode—MR Low Set-up 34 — ns THMRP Parity Program Mode—MR Low Hold 24 — ns TFTP Parity Program Mode—Write HIGH to Read HIGH 34 — ns TAP Parity Program Mode—Data Access Time — 30 ns TOHP Parity Program Mode—Data Hold Time from MR HIGH 4 — ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing characteristics Table, capacitive output loading CL=50 pF. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Worst case operating conditions: VDD=4.5V to 5.5V, TC= -55°C to +125°C, post total dose at 25°C. (3) For flag updates, tskew1 is the minimum time an opposite clock can occur after a clock and still not be included in the current clock cycle. At less that tskew1, inclusion of the opposite clock is arbitrary. (4) For flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in the current clock cycle. At less than tskew2, inclusion of the opposite clock is arbitrary. (5) Timing parameters are defined in Figures 1 through 6. 7 HX6409/HX6218/HX6136 AC TIMING WAVEFORMS Tckw Tckh CKW Tckl Enabled WR Tsd Disabled WR Thd Data Tsen Tsen Then Then ENW Flags Tfh Tfh Tfd Tfd Figure 1. Write Timing Tckw Tckh CKR Tckl Enabled RD Toh Disabled RD Ta Data Tsen Then Tsen Then ENR Flags Tfh Tfh Tfd Tfd Figure 2. Read Timing 8 HX6409/HX6218/HX6136 Tpmr MR Tscmr Tmrr First Write CKW ENW Tscmr Tmrr CKR ENR Tphmr Data Tamr All Data Outputs Low Valid Data Tmrf HF Tmrf Other Flags Figure 3. Master Reset Timing NOTE: If ENW is held high during Master Reset, the parity is disabled. Latent Cycle Enable Read CKR ENR Tskew1 Flag Update Tskew2 Enable Read Tskew2 Enable Write CKW ENW HF high Tfd Tfd Flags Tfd Figure 4. Read Flag Update Timing NOTE: When an empty condition occors, the empty flag is set. The performance of another read requires at least one write, on read clock to reset the empty flag and then an enabled read clock. 9 HX6409/HX6218/HX6136 Latent Cycle Enable Write CKW ENW Flag Update Tskew2 Tskew1 Enable Write Tskew2 Enable Read CKR ENR Tfd Tfd Tfd Flags Figure 5. Write Flag Update Timing NOTE: When a full condition occurs, the full flag is set. The performance of another write requires at least one read, one write clock to reset the full flag and then one enabled write clock. Read M+1 CKR Low ENR OE Toe Tohz Data Valid Data Word M Valid Data Word M+1 Tolz Figure 6. Output Enable Timing Tsmrp MR Thmrp Tckh Tscmr Parity Write CKW Tmrr First Write Tftp ENW Tnd Tsd Parity Word Data In Last Word Tscmr Word Thmrp Tsmrp Parity Read CKR Tckh ENR Tohmr Data Out Tap Tohp Parity Word Valid Data Figure 7. Parity Programming Mode 10 Tamr HX6409/HX6218/HX6136 TESTER AC TIMING CHARACTERISTICS TTL I/O Configuration CMOS I/O Configuration AAAA AAAA AA AAA AAAAA AAAA AAAAA AAAA AAAA AAAA AA AA 3V Input Levels* VDD-0.5 V 1.5 V 0V VDD/2 0.5 V 1.5 V Output Sense Levels VDD-0.4V 0.4 V VDD/2 VDD-0.4V High Z 0.4 V 3.4 V High Z High Z 3.4 V High Z 2.4 V High Z = 2.9V 2.4 V High Z = 2.9V * Input rise and fall times <1 ns/V QUALITY AND RADIATION HARDNESS ASSURANCE and are available per the applicable Standard Microcircuits Drawing (SMD). QML devices offer ease of procurement by eliminating the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a complete “Total Quality Assurance System,” a computer data base process performance tracking system and a radiation hardness assurance strategy. RELIABILITY Honeywell understands the stringent reliability requirements for space and defense systems and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOSTM process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. In addition, the reliability of the RICMOS™ process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Group B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer’s requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. SCREENING LEVELS Honeywell offers several levels of device screening to meet your system needs. “Engineering Devices” are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MIL-STD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 11 HX6409/HX6218/HX6136 Pin List for HX6409 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 VSS 7 Q5 13 QT/TQF 19 ENR 25 D6 31 D0 2 Q0 8 Q6 14 HF 20 CKW 26 D5 32 VDD 3 Q1 9 Q7 15 EF 21 ENW 27 D4 4 Q2 10 Q8 16 VSS 22 MR 28 D3 5 Q3 11 OE 17 VDD 23 D8 29 D2 6 Q4 12 EF_FAULT 18 CKR 24 D7 30 D1 Pin List for HX6218 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 CKR 13 D17 25 VSS 37 Q1 49 Q11 61 VSS 2 ENR 14 D16 26 D8 38 Q2 50 Q12 62 VDD 3 CKW 15 D15 27 D7 39 Q3 51 Q13 63 OE 4 ENW 16 D14 28 D6 40 Q4 52 VDD 64 EF_FAULT 5 MR 17 VDD 29 D5 41 Q5 53 VSS 65 QF/TQF 6 VDD 18 VSS 30 D4 42 Q6 54 Q14 66 HF 7 VSS 19 D13 31 D3 43 Q7 55 Q15 67 E?F 8 VSS 20 D12 32 D2 44 Q8 56 Q16 68 VDD 9 VSS 21 D11 33 D1 45 VSS 57 Q17 10 VDD 22 D10 34 D0 46 VDD 58 VDD 11 VDD 23 D9 35 VDD 47 Q9 59 VDD 12 VDD 24 VDD 36 Q0 48 Q10 60 VDD 12 HX6409/HX6218/HX6136 Pin List for HX6236 Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal 1 VSS 23 CKW 45 NC 67 VSS 89 Q2 111 Q19 2 NC 24 NC 46 D25 68 NC 90 NC 112 Q20 3 NC 25 ENW 47 NC 69 D8 91 Q3 113 NC 4 NC 26 NC 48 D24 70 D7 92 NC 114 Q21 5 OE 27 MR 49 VSS 71 D6 93 Q4 115 VDD 6 NC 28 NNC 50 VDD 72 NC 94 Q5 116 VSS 7 EF_FAULT 29 NC 51 D23 73 D5 95 Q6 117 Q22 8 QF/TQF 30 NC 52 D22 74 D4 96 Q7 118 Q23 9 HF 31 NC 53 D21 75 D3 97 Q8 119 Q24 10 NC 32 NC 54 D20 76 NC 98 NC 120 Q25 11 EF 33 VSS 55 D19 77 D2 99 VSS 121 Q26 12 NC 34 VDD 56 D18 78 NC 100 VDD 122 Q27 13 NC 35 D35 57 D17 79 D1 101 Q9 123 Q28 14 NC 36 D34 58 D16 80 NC 102 Q10 124 NC 15 NC 37 D33 59 D15 81 D0 103 Q11 125 Q29 16 VSS 38 D32 60 D14 82 VSS 104 Q12 126 Q30 17 VDD 39 D31 61 D13 83 VDD 105 Q13 127 Q31 18 NC 40 D30 62 D12 84 NC 106 Q14 128 Q32 19 CKR 41 D29 63 D11 85 Q0 107 Q15 129 Q33 20 NC 42 D28 64 D10 86 NC 108 Q16 130 Q34 21 ENR 43 D27 65 D9 87 Q1 109 Q17 131 Q35 22 NC 44 D26 66 VDD 88 NC 110 Q18 132 VDD 13 HX6409/HX6218/HX6136 PACKAGING feature non-conductive ceramic tie bars. The tie bars allows electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. The FIFO is offered in a 32-lead, 68-lead and a 132-lead flat pack, depending on the configuration. These packages are constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. The flat packs also PACKAGE DRAWING FOR 6409 (22018533-001) Optional capacitors in cutout E 1 22018533-001 Z b (width) TOP VIEW F e S L A Kovar Lid [4] Cutout Area V E2 Ceramic Body C VDD 1 BOTTOM VIEW D (pitch) Q All dimensions in inches A A AA A AAA AA A A AA A AAA AA VDD VSS U Y X W Lead Alloy 42 [1] [2] [3] [4] E3 14 A b C D e E E2 E3 F L Q S U V W X Y Z 0.135 ± 0.015 0.017 ± 0.002 0.004 to 0.009 0.820 ± 0.008 0.050 ± 0.005 [1] 0.600 ± 0.008 0.500 ± 0.008 0.040 ref 0.750 ± 0.005 [2] 0.295 min [3] 0.026 to 0.045 0.035 ± 0.010 0.080 ref 0.380 ref 0.050 ref 0.075 ref 0.010 ref 0.135 ref BSC - Basic lead spacing between centers Where lead is brazed to package Parts delivered with leads unformed Lid connected to VSS HX6409/HX6218/HX6136 PACKAGE DRAWING FOR 6218 (22019075-001) D/E F (4 Places) A1 A 60 61 Terminal 1 ID Area All dimensions in inches A 0.092 ± 0.010 A1 0.080 ± 0.008 b 0.018 ± 0.002 c 0.010 ± 0.002 D/E 0.950 ± 0.015 e 0.050 ± 0.005 (1) F 0.800 ± 0.008 (1) N 68 ref. 44 43 68 1 (1) BSC – Basic lead spacing between centers e 9 27 10 26 b (N Places) c PACKAGE DRAWING FOR 6136 (22018696-001) HD/HE D/E A e1 4 Places A1 99 67 Dimensions in inches 100 min 66 A A1 A2 b c D/E e e1 HD/HE L N L 4 Places e 132 Non-Conductive Tie Bar: 4 Places Index Corner & Terminal No. 1 ID Area 34 1 33 b N Places c A2 15 max 0.091 0.109 0.057 0.063 0.036 0.047 0.005 0.009 0.004 0.008 0.942 0.958 0.025 BSC .800 BSC 2.485 0.575 2.505 Ref. 132 HX6409/HX6218/HX6136 ORDERING INFORMATION (1) H 6409 X PROCESS X=SOI SOURCE H=HONEYWELL PART NUMBER 6409 = 4K x 9 6218 = 2K x 18 6136 = 1K x 36 D S H SCREEN LEVEL S=Level S B=Level B E=Engr Device (2) PACKAGE DESIGNATION D=68-Lead CQFP F=132-Lead CQFP T=32-Lead CQFP C INPUT BUFFER TYPE C=CMOS Level T=TTL Level TOTAL DOSE HARDNESS R=1x105 rad(SiO2) F=3x105 rad(SiO2) H=1x106 rad(SiO2) N=No Level Guaranteed (1) Orders may be faxed to 612-954-2051. Please contact our Customer Service Department at 612-954-2888 for further information. (2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed. Contact Factory with other needs. To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. 900157, Rev. D 2/99