128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4 Document Title 128Mx64 bits Unbuffered DDR SO-DIMM Revision History No. History Draft Date 0.1 Initial Draft Dec. 2003 0.2 1) Reflected a “notational” change in module thickness on page 14 - Not Real ! 2) Corrected some typos Apr. 2004 Remark This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 1 128Mx64 bits Unbuffered DDR SO-DIMM HYMD512M646A(L)FS8-D43/D4 DESCRIPTION Hynix HYMD512M646A(L)FS8-D43/D4 series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512M646A(L)FS8-D43/D4 series consists of eight 128Mx8 DDR MCP SDRAM in FBGA packages on a 200pin glass-epoxy substrate. Hynix HYMD512M646A(L)FS8-D43/D4 series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD512M646A(L)FS8-D43/D4 series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD512M646A(L)FS8-D43/D4 series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 1GB (128M x 64) Unbuffered DDR SO-DIMM based on 128Mx8 DDR MCP SDRAM • Data inputs on DQS centers when write (centered DQ) • 200-pin small outline dual in-line memory module (SO-DIMM) • Data strobes synchronized with output data for read and input data for write • 2.6V +/- 0.1V VDD and VDDQ Power supply • Programmable CAS Latency 3 supported • All inputs and outputs are compatible with SSTL_2 interface • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Fully differential clock operations (CK & /CK) with 200MHz • tRAS Lock-out function supported • Internal four bank operations with single pulsed RAS • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock ORDERING INFORMATION Part No. HYMD512M646A(L)FS8-D43 HYMD512M646A(L)FS8-D4 Power Supply VDD=2.6V VDDQ=2.6V Clock Frequency 200MHz (DDR400 3-3-3) 200MHz (DDR400 3-4-4) Interface Form Factor SSTL_2 200pin Unbuffered SO-DIMM 67.6mm x 31.75mm x 1mm * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 2 HYMD512M646A(L)FS8-D43/D4 PIN DESCRIPTION Pin Pin Description Pin Pin Description CK0, /CK0, CK1, /CK1 Differential Clock Inputs VDDQ DQs Power Supply CS0, CS1 Chip Select Input VSS Ground CKE0, CKE1 Clock Enable Input VREF Reference Power Supply /RAS, /CAS, /WE Commend Sets Inputs VDDSPD Power Supply for SPD A0 ~ A12 Address SA0~SA2 E2PROM Address Inputs BA0, BA1 Bank Address SCL E2PROM Clock DQ0~DQ63 Data Inputs/Outputs SDA E2PROM Data I/O DQS0~DQS7 Data Strobe Inputs/Outputs VDDID VDD Identification Flag DM0~DM7 Data-in Mask DU Do not Use VDD Power Supply NC No Connection PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 /CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 CK1 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 /RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 /WE 120 /CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 /CS0 122 /CS1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 NC 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 NC 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 /CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 NC 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 NC 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 NC 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 A12 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Rev. 0.2 / Apr. 2004 3 HYMD512M646A(L)FS8-D43/D4 FUNCTIONAL BLOCK DIAGRAM CKE1 CKE0 /CS1 /CS0 DQS0 DM0 DQS4 DM4 DQ0 DQ1 DQ2 DM I/O0 I/O1 I/O2 DQ3 DQ4 I/O3 I/O4 DQ5 DQ6 I/O5 I/O6 DQ7 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1 D0 DQS1 DM1 DQ32 DQ33 DQ34 DM I/O0 I/O1 I/O2 DQ35 DQ36 I/O3 I/O4 DQ37 DQ38 I/O5 I/O6 DQ39 I/O7 DQ40 DQ41 DQ42 DM I/O0 I/O1 I/O2 DQS /CS0 /CS1 /CKE0 /CKE1 D4 DQS5 DM5 DQ10 DM I/O0 I/O1 I/O2 DQ11 DQ12 I/O3 I/O4 DQ13 DQ14 I/O5 I/O6 DQ15 I/O7 DQ8 DQ9 DQS /CS0 /CS1 /CKE0 /CKE1 D1 I/O3 I/O4 DQ43 DQ44 DQ45 DQ46 DQS2 DM2 DQS /CS0 /CS1 /CKE0 /CKE1 D5 I/O5 I/O6 DQ47 I/O7 DQ48 DQ49 DQ50 DM I/O0 I/O1 I/O2 DQS6 DM6 DQ16 DQ17 DQ18 DM DQS /CS0 /CS1 /CKE0 /CKE1 I/O0 I/O1 I/O2 DQ19 DQ20 I/O3 I/O4 DQ21 DQ22 I/O5 I/O6 DQ23 I/O7 DQ51 DQ52 DQ53 D2 DQS3 DM3 DQS /CS0 /CS1 /CKE0 /CKE1 I/O3 I/O4 DQ54 I/O5 I/O6 DQ55 I/O7 D6 DQS7 DM7 DQ24 DQ25 DQ26 DM I/O0 I/O1 I/O2 DQ27 DQ28 I/O3 I/O4 DQ29 DQ30 I/O5 I/O6 DQ31 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1 D3 DQ56 DQ57 DQ58 DM I/O0 I/O1 I/O2 DQ59 DQ60 I/O3 I/O4 DQ61 DQ62 I/O5 I/O6 DQ63 I/O7 DQS /CS0 /CS1 /CKE0 /CKE1 D7 Serial PD VDD SPD SPD VDD /VDDQ DO-D15 VREF DO-D15 WP DO-D15 VSS VDDID SDA SCL A0 A1 A2 SA0 SA1 SA2 Strap:see Note 4 Note : BA0BA1 A0A12 BA0-BA1 : SDRAMs D0-D7 A0-A12 : SDRAMs D0-D7 /RAS /RAS : SDRAMs D0-D7 /CAS /CAS : SDRAMs D0-D7 /WE Rev. 0.2 / Apr. 2004 /WE : SDRAMs D0-D7 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors : 22 Ohms ? 5%. 4. VDDID strap connections (for memory device VDD, VDDQ) : STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ? VDDQ 4 HYMD512M646A(L)FS8-D43/D4 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Operating Temperature (Ambient) TA 0 ~ 70 o Storage Temperature TSTG -55 ~ 125 oC Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 1.0 x # of Components W Soldering Temperature Þ Time TSOLDER 260 / 10 oC C / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 2.5 2.6 2.7 V Power Supply Voltage VDDQ 2.5 2.6 2.7 V Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V Reference Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V Note 1 2 3 Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed +/- 2% of the DC value. AC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V) Parameter Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) Input Differential Voltage, CK and /CK inputs VID(AC) Input Crossing Point Voltage, CK and /CK inputs VIX(AC) Max Unit Note V VREF - 0.31 V 0.7 VDDQ + 0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev. 0.2 / Apr. 2004 5 HYMD512M646A(L)FS8-D43/D4 AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 Ω Series Resistor (RS) 25 Ω Output Load Capacitance for Access Time Measurement (CL) 30 pF Input Timing Measurement Reference Level Voltage Rev. 0.2 / Apr. 2004 6 HYMD512M646A(L)FS8-D43/D4 CAPACITANCE (TA=25oC, f=100MHz ) Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A13, BA0, BA1 CIN1 TBD TBD pF Input Capacitance /RAS, /CAS, /WE CIN2 TBD TBD pF Input Capacitance CKE0, CKE1 CIN3 TBD TBD pF Input Capacitance /CS0, /CS1 CIN4 TBD TBD pF Input Capacitance CK0, /CK0, CK1, /CK1 CIN5 TBD TBD pF Input Capacitance DM0 ~ DM7 CIN6 TBD TBD pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 TBD TBD pF Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT RT=50Ω Output Zo=50Ω VREF CL=30pF Rev. 0.2 / Apr. 2004 7 HYMD512M646A(L)FS8-D43/D4 DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Input Leakage Current Symbol Add, CMD, /CS, CKE Min. Max -32 32 -16 16 ILI CK0, /CK0, CK1, /CK1 Unit Note uA 1 Output Leakage Current ILO -5 5 uA 2 Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA Output Low Voltage VOL - VTT - 0.76 V IOL = +15.2mA Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.2 / Apr. 2004 8 HYMD512M646A(L)FS8-D43/D4 DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Speed Symbol Test Condition Operating Current IDD0 One bank; Active - Precharge ; tRC=tRC(min); tCK=tCK(min) ; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1480 mA Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle 1880 mA Precharge Power Down Standby Current IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min) 160 mA Idle Standby Current IDD2F /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM 560 mA Idle Quiet Standby Current IDD2Q /CS>=Vih(min); All banks idle; CKE>=Vih(min); Addresses and other control inputs stable, Vin=Vref for DQ, DQS and DM 520 mA Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 192 mA Active Standby Current IDD3N /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 680 mA Operating Current IDD4R Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA 2520 IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle 2520 2680 Operating Current -D43 Auto Refresh Current IDD5 tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz Self Refresh Current IDD6 CKE =< 0.2V; External clock on; tCK=tCK(min) Operating Current Four Bank Operation IDD7 Four bank interleaving with BL=4, Refer to the following page for detailed test condition Rev. 0.2 / Apr. 2004 -D4 Unit Note mA Normal 80 mA Low Power 40 mA 4600 mA 9 HYMD512M646A(L)FS8-D43/D4 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter DDR400 (D43) DDR400 (D4) Min Max Min Max Symbol Unit Note Row Cycle Time tRC 55 - 60 - ns Auto Refresh Row Cycle Time tRFC 70 - 70 - ns Row Active Time tRAS 40 70K 40 70K ns Active to Read with Auto Precharge Delay tRAP tRCD or tRASmin - tRCD or tRASmin - ns Row Address to Column Address Delay tRCD 15 - 18 - ns Row Active to Row Active Delay tRRD 10 - 10 - ns Column Address to Column Address Delay tCCD 1 - 1 - CK Row Precharge Time tRP 15 - 18 - ns Write Recovery Time tWR 15 - 15 - ns Internal Write to Read Command Delay tWTR 2 - 2 - CK Auto Precharge Write Recovery + Precharge Time tDAL (tWR/tCK) + (tRP/tCK) - (tWR/tCK) + (tRP/tCK) - CK tCK 5 10 5 10 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.7 0.7 -0.7 0.7 ns DQS-Out edge to Clock edge Skew tDQSCK -0.55 0.55 -0.55 0.55 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.4 - 0.4 ns Data-Out hold time from DQS tQH tHP -tQHS - tHP -tQHS - ns 1,10 Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - ns 1,9 tQHS - 0.5 - 0.5 ns 10 tAC(Max) ns System Clock Cycle Time CL = 3 Data Hold Skew Factor Data-out high-impedance window from CK,/CK tHZ tAC(Max) Data-out low-impedance window from CK, /CK tLZ -0.7 0.7 -0.7 0.7 ns Input Setup Time (fast slew rate) tIS 0.6 - 0.6 - ns Input Hold Time (fast slew rate) tIH 0.6 - 0.6 - ns Input Setup Time (slow slew rate) tIS 0.7 - 0.7 - ns Input Hold Time (slow slew rate) tIH 0.7 - 0.7 - ns 16 15 17 2,3,5,6 2,4,5,6 Rev. 0.2 / Apr. 2004 10 HYMD512M646A(L)FS8-D43/D4 AC CHARACTERISTICS (AC operating conditions unless otherwise noted) - continued - DDR400 (D43) DDR400 (D4) Min Max Min Max tIPW 2.2 - 2.2 Write DQS High Level Width tDQSH 0.35 - Write DQS Low Level Width tDQSL 0.35 Clock to First Rising edge of DQS-In tDQSS 0.72 DQS falling edge to CK setup time tDSS 0.2 0.2 CK DQS falling edge hold time from CK tDSH 0.2 0.2 CK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.4 - 0.4 - ns Data-in Hold Time to DQS-In (DQ & DM) tDH 0.4 - 0.4 - ns 6,7,11 , 12,13 DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - ns 6 Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 CK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 CK Write DQS Preamble Setup Time tWPRES 0 - 0 - CK Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - CK Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 CK Mode Register Set Delay tMRD 2 - 2 - CK Exit Self Refresh to Any Execute Command tXSC 200 - 200 - CK Average Periodic Refresh Interval tREFI - 7.8 - 7.8 us Parameter Symbol Input Pulse Width Unit Note - ns 6 0.35 - CK - 0.35 - CK 1.28 0.72 1.28 CK 8 Note : 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold 5. Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tIS Delta tIH V/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 6. CK, /CK slew rates are >=1.0V/ns 7. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. Rev. 0.2 / Apr. 2004 11 HYMD512M646A(L)FS8-D43/D4 8. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 9. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 11. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 12. 13. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tDS Delta tDH V/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level 14. 15. 16. Delta tDS Delta tDH mV ps ps +280 +50 +50 I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V. (1/SlewRate1)-(1/SlewRate2) Delta tDS Delta tDH ns/V ps ps 0 0 0 +/-0.25 +50 +50 +/- 0.5 +100 +100 DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock 17. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x tCK. 18. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). Rev. 0.2 / Apr. 2004 12 HYMD512M646A(L)FS8-D43/D4 SIMPLIFIED COMMAND TRUTH TABLE A10/ AP Command CKEn-1 CKEn /CS /RAS /CAS /WE Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 H X X X H X X 1 L H H H Device Deselect No Operation Bank Active H X L L H H H X L H L H ADDR RA Read BA V L CA Read with Autoprecharge 1 1,3 L H X L H L L CA Write with Autoprecharge 1 V H Precharge All Banks H X L L H L Precharge selected Bank 1 V H Write Note 1,4 H X 1,5 L V 1 X Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L L L L H H X X X Exit L H L H H H H X X X L H H H Self Refresh Precharge Power Down Mode Active Power Down Mode (Clock Suspend) Entry H 1 X 1 1 L 1 X Exit Entry Exit L H L H X X X 1 L H H H 1 H X X X 1 L V V V H L H X X 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.2 / Apr. 2004 13 HYMD512M646A(L)FS8-D43/D4 PACKAGE DIMENSIONS 2.00 mm Front 2.00 mm Component Keepout Area 31.75 mm 20.00 mm 1 39 41 199 Side Back 67.60 mm 1.1mm Max z 3.8mm Max Rev. 0.2 / Apr. 2004 14 SERIAL PRESENCE DETECT SPD SPECIFICATION (128Mx64 Unbuffered DDR SO-DIMM) Rev. 0.2 / Apr. 2004 15 HYMD512M646A(L)FS8-D43/D4 SERIAL PRESENCE DETECT Byte# 0 Function Description Number of Bytes written into serial memory at module manufacturer 1 Total number of Bytes in SPD device 2 Fundamental memory type 3 4 5 Number of physical banks on DIMM 6 Module data width 7 Module data width (continued) 8 Module voltage Interface levels(VDDQ) Bin Sort :D43(DDR400 3-3-3) / D4(DDR400 3-4-4) Function Supported Hexa Value D43 D4 D43 D4 128 Bytes 128 Bytes 80h 80h Note 256 Bytes 256 Bytes 08h 08h DDR SDRAM DDR SDRAM 07h 07h Number of row address on this assembly 13 13 0Dh 0Dh 1 Number of column address on this assembly 11 11 0Bh 0Bh 1 2Bank 2Bank 02h 02h 64 Bits 64 Bits 40h 40h - - 00h 00h SSTL 2.5V SSTL 2.5V 04h 04h 9 DDR SDRAM cycle time at CAS Latency=X (tCK) 10 DDR SDRAM access time from clock at CL=X (tAC) 11 Module configuration type 12 Refresh rate and type 13 5.0ns 5.0ns 50h 50h 2 +/-0.7ns +/-0.7ns 70h 70h 2 00h None None 00h 7.8us & Self refresh 7.8us & Self refresh 82h 82h Primary DDR SDRAM width x8 x8 08h 08h 14 Error checking DDR SDRAM data width N/A N/A 00h 00h 15 Minimum clock delay for back-to-back random column address(tCCD) 1 CLK 1 CLK 01h 01h 0Eh 16 Burst lengths supported 2,4,8 2,4,8 0Eh 17 Number of banks on each DDR SDRAM 4 Banks 4 Banks 04h 04h 18 CAS latency supported 2, 2.5, 3 2, 2.5, 3 1Ch 1Ch 19 CS latency 0 0 01h 01h 20 WE latency 1 1 02h 02h 21 DDR SDRAM module attributes 22 DDR SDRAM device attributes : General 23 DDR SDRAM cycle time at CL=X-0.5(tCK) 24 DDR SDRAM access time from clock at CL=X-0.5(tAC) 25 DDR SDRAM cycle time at CL=X-1(tCK) 26 DDR SDRAM access time from clock at CL=X-1(tAC) 27 Differential Clock Input Differential Clock Input +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out 20h 20h +/-0.2Voltage tolerance, Concurrent Auto Precharge tRAS Lock Out C0h C0h 6.0ns 6.0ns 60h 60h 2 +/-0.7ns +/-0.7ns 70h 70h 2 7.5ns 7.5ns 75h 75h 2 +/-0.75ns +/-0.75ns 75h 75h 2 Minimum row precharge time(tRP) 15ns 18ns 3Ch 48h 28 Minimum row activate to row active delay(tRRD) 10ns 10ns 28h 28h 29 Minimum RAS to CAS delay(tRCD) 15ns 18ns 3Ch 48h 30 Minimum active to precharge time(tRAS) 40ns 40ns 28h 28h 31 Module row density 512MB 512MB 80h 80h 32 Command and address signal input setup time(tIS) 0.60ns 0.60ns 60h 60h 33 Command and address signal input hold time(tIH) 0.60ns 0.60ns 60h 60h 34 Data signal input setup time(tDS) 0.40ns 0.40ns 40h 40h 35 Data signal input hold time(tDH) 0.40ns 0.40ns 40h 40h 36~40 Reserved for VCSDRAM Undefined Undefined 00h 00h 41 Minimum active / auto-refresh time ( tRC) 55ns 58ns 37h 3Ah 42 Minimum auto-refresh to active/auto-refresh command period(tRFC) 70ns 70ns 46h 46h 43 Maximum cycle time (tCK max) 10ns 10ns 28h 28h 44 Maximim DQS-DQ skew time(tDQSQ) 0.4ns 0.4ns 28h 28h 45 Maximum read data hold skew factor(tQHS) 0.5ns 0.5ns 50h 50h 00h 46~61 Superset information(may be used in future) 62 SPD Revision code 63 Checksum for Bytes 0~62 Rev. 0.2 / Apr. 2004 Undefined Undefined 00h Initial release Initial release 00h 00h - - A8h C3h 16 HYMD512M646A(L)FS8-D43/D4 SERIAL PRESENCE DETECT Byte# 64 65~71 72 Function Description Manufacturer JEDEC ID Code --------- Manufacturer JEDEC ID Code Manufacturing location - continued Function Supported Hexa Value D43 D4 D43 D4 Hynix JEDEC ID Hynix JEDEC ID ADh ADh - - 00h 00h 0*h 1*h 2*h 3*h 4*h 5*h 0*h 1*h 2*h 3*h 4*h 5*h Hynix(Korea Area) Hynix(Korea Area) HSA(United States Area) HSA(United States Area) HSE(Europe Area) HSE(Europe Area) HSJ(Japan Area) HSJ(Japan Area) Singapore Singapore Asia Area Asia Area 73 Manufacture part number(Hynix Memory Module) H H 48h 48h 74 -------- Manufacture part number(Hynix Memory Module) Y Y 59h 59h 75 -------- Manufacture part number(Hynix Memory Module) M M 4Dh 4Dh 76 Manufacture part number (DDR SDRAM) D D 44h 44h 77 Manufacture part number(Memory density) 5 5 35h 35h 78 Manufacture part number(Module Depth) 1 1 31h 31h 79 ------- Manufacture part number(Module Depth) 2 2 32h 32h 80 Manufacture part number(Module type) M M 4Dh 4Dh 81 Manufacture part number(Data width) 6 6 36h 36h 82 -------Manufacture part number(Data width) 4 4 34h 34h 83 Manufacture part number(Refresh, # of Bank.) 6(8K refresh,4Bank) 6(8K refresh,4Bank) 36h 36h 84 Manufacture part number(Component Generation) A A 41h 41h 85 Manufacture part number(Component configuration) F F 46h 46h 86 Manufacture part number(Module type) 8 8 38h 38h 87 Manufacture part number(Hyphen) ‘-’ ‘-’ 2Dh 2Dh 88 Manufacture part number(Minimum cycle time) D D 44h 44h 89 Manufacture part number(Minimum cycle time) 4 4 34h 34h 90 Manufacture revision code(Minimum cycle time) 3 - 33h - 91 Manufacture revision code(for Component) Note 6 92 Manufacture revision code (for PCB) 93 Manufacturing date(Year) 3 94 Manufacturing date(Week) 3 95~98 Module serial number 4 99~127 Manufacturer specific data (may be used in future) Undefined Undefined 00h 00h 5 128~255 Open for customer use Undefined Undefined 00h 00h 5 Note : 1. The bank address is excluded 2. These value is based on the component specification 3. These bytes are programmed by code of date week & date year 4. These bytes apply to Hynix’s own Module Serial Number system 5. These bytes undefined and coded as ‘00h’ 6. Refer to Hynix web site Rev. 0.2 / Apr. 2004 17