Direct Rambus™ RIMM™ Module 128 MBytes (64M x 16/18) based on 8Mx16/18 Overview Key Timing Parameters/Part Numbers The Direct Rambus™ RIMM™ module is a general purpose high-performance memory subsystem suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and low latency are required. The following table lists the frequency and latency bins available from RIMM modules. An optional -LP designator is used to indicate low power modules. Organization The 128MB Direct Rambus RIMM module consists of eight 128M Direct Rambus DRAM (Direct RDRAM™ ) devices. These are extremely high-speed CMOS DRAMs organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz or 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAM allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions. I/O Freq. trac (Row Access MHz Time) ns Part Number 64M x 16 600 53 HYMR11664-653 64M x 16 800 45 HYMR11664-845 64M x 16 800 40 HYMR11664-840 64M x 18 600 53 HYMR11864-653 64M x 18 800 45 HYMR11864-845 64M x 18 800 40 HYMR11864-840 Form Factor The Direct Rambus RIMM modules are offered in a 184-pin 1mm pin pitch form factor suitable for desktop and other system applications. Features 184-pin 1mm pin spacing Card Size: 133.35mm x 31.75mm x 1.27mm (5.25” x 1.25” x 0.050”) 128MB Direct RDRAM storage Each RDRAM has 32banks, for 256banks total on module Gold plated contacts RDRAMs use Chip Scale Package (CSP) Serial Presence Detect support Operates from a 2.5 volt supply (±5%) Low power and powerdown self refresh modes Separate Row and Column buses for higher efficiency Rev. 0.0 /Feb. 99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 HYMR11664/11864 Series Preliminary Pinouts and Pin Names Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 Pin Name Gnd LDQA8 Gnd LDQA6 Gnd LDQA4 Gnd LDQA2 Gnd LDQA0 Gnd LCTMN Gnd LCTM Gnd NC Gnd LROW1 Gnd LCOL4 Gnd LCOL2 Gnd LCOL0 Gnd LDQB1 Gnd LDQB3 Gnd LDQB5 Gnd LDQB7 Gnd LSCK Vcmos SOUT Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 Pin Name Gnd LDQA7 Gnd LDQA5 Gnd LDQA3 Gnd LDQA1 Gnd LCFM Gnd LCFMN Gnd NC Gnd LROW2 Gnd LROW0 Gnd LCOL3 Gnd LCOL1 Gnd LDQB0 Gnd LDQB2 Gnd LDQB4 Gnd LDQB6 Gnd LDQB8 Gnd LCMD Vcmos SIN Vcmos NC Gnd NC Vdd Vdd NC NC NC NC Page 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Pin A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 Pin Name NC NC NC NC Vref Gnd SCL Vdd SDA SVdd SWP Vdd RSCK Gnd RDQB7 Gnd RDQB5 Gnd RDQB3 Gnd RDQB1 Gnd RCOL0 Gnd RCOL2 Gnd RCOL4 Gnd RROW1 Gnd NC Gnd RCTM Gnd RCTMN Gnd RDQA0 Gnd RDQA2 Gnd RDQA4 Gnd RDQA6 Gnd RDQA8 Gnd Pin B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 Pin Name NC NC NC NC Vref Gnd SA0 Vdd SA1 SVdd SA2 Vdd RCMD Gnd RDQB8 Gnd RDQB6 Gnd RDQB4 Gnd RDQB2 Gnd RDQB0 Gnd RCOL1 Gnd RCOL3 Gnd RROW0 Gnd RROW2 Gnd NC Gnd RCFMN Gnd RCFM Gnd RDQA1 Gnd RDQA3 Gnd RDQA5 Gnd RDQA7 Gnd Rev. 0.0/ Feb. 99 HYMR11664/11864 Series Preliminary Pin Definition Signal Pins Gnd A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, A31, A33, A39, A52, A60, A62, A64, A66, A68, A70, A72, A74, A76, A78, A80, A82, A84, A86, A88, A90, A92, B1, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, B39, B52, B60, B62, B64, B66, B68, B70, B72, B74, B76, B78, B80, B82, B84, B86, B88, B90, B92 LCFM B10 LCFMN B12 LCMD B34 LCOL4.. LCOL0 A20, B20, A22, B22, A24 LCTM A14 LCTMN A12 LDQA8.. LDQA0 A2, B2, A4, B4, A6, B6, A8, B8, A10 LDQB8.. LDQB0 B32, A32, B30, A30, B28, A28, B26, A26, B24 LROW2.. LROW0 B16, A18, B18 LSCK A34 NC A16, B14, A38, B38, A40, B40, A43, B43, A44, B44, A45, B45, A46, B46, A47, B47, A48, B48, A49, B49, A50, B50, A77, B79 RCFM B83 RCFMN B81 I/O Type Description Ground reference for RDRAM core and interface. 72 pins. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. I VCMOS I RSL Column bus. 5-pin bus containing control and address information for column accesses. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. I/O RSL Data bus A. A 9-pin bus carrying a byte of read or write data between the Channel and the RDRAM. LDQA8 is non-functional on x16 devices I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. LDQB8 is non-functional on x16 devices. I RSL Row bus. 3-pin bus containing control and address information for row accesses. I VCMOS Clock input. Pin used to read from and write to the control registers. Serial Command Pin. Pin used to read from and write to the control registers. Also used for power management. These pins are not connected. These 24 pins are all reserved for future use. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. I RSL Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity. Rev. 0.0/ Feb. 99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 3 HYMR11664/11864 Series Preliminary Signal Pins RCMD B59 I/O Type Description I VCMOS I RSL Column bus. 5-pin bus containing control and address information for column accesses. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. I RSL Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Serial Command Input. Pin used to read from and write to the control registers. Also used for power management. RCOL4.. RCOL0 A73, B73, A71, B71, A69 RCTM A79 RCTMN A81 RDQA8.. RDQA0 A91, B91, A89, B89, A87, B87, A85, B85, A83 I/O RSL Data bus A. A 9-pin bus carrying a byte of read or write data between the Channel and the RDRAM. RDQA8 is non-functional on x16 devices. RDQB8.. RDQB0 B61, A61, B63, A63, B65, A65, B67, A67, B69 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel and the RDRAM. RDQB8 is non-functional on x16 devices. RROW2.. RROW0 B77, A75, B75 I RSL Row bus. 3-pin bus containing control and address information for row accesses. RSCK A59 I VCMOS Clock input. Pin used to read from and write to the control registers. SA0 B53 I SVDD Serial Presence Detect Address 0. SA1 B55 I SVDD Serial Presence Detect Address 1. SA2 B57 I SVDD Serial Presence Detect Address 2. SCL A53 I SVDD Serial Presence Detect Clock. SDA A55 I/O SVDD Serial Presence Detect Data (Open Collector I/O). SIN B36 I/O VCMOS Serial I/O. Pin for reading from and writing to the control registers. Attaches to SIO0 of the first RDRAM on the module. I/O VCMOS Serial I/O. Pin for reading from and writing to the control registers. Attaches to SIO1 of the last RDRAM on the module. SOUT A36 SVDD A56, B56 SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and SA2. SWP A57 VCMOS A35, B35, A37, B37 CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. Vdd A41, A42, A54, A58, B41, B42, B54, B58 Supply voltage for the RDRAM core and interface logic. Vref A51, B51 Logic threshold reference voltage for RSL signals. I SVDD Page 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. Rev. 0.0/ Feb. 99 LDQA8 LDQA7 LDQA6 LDQA5 LDQA4 LDQA3 LDQA2 LDQA1 LDQA0 LCFM LCFMN LCTM LCTMN LROW2 LROW1 LROW0 LCOL4 LCOL3 LCOL2 LCOL1 LCOL0 LDQB0 LDQB1 LDQB2 LDQB3 LDQB4 LDQB5 LDQB6 LDQB7 LDQB8 SIN LSCK LCMD VREF DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 U8 Direct RDRAM (128/144Mb) SIO0 SIO1 SCK CMD Vref . . . . . . U3 RDQA8 RDQA7 RDQA6 RDQA5 RDQA4 RDQA3 RDQA2 RDQA1 RDQA0 RCFM RCFMN RCTM RCTMN RROW2 RROW1 RROW0 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 RDQB0 RDQB1 RDQB2 RDQB3 RDQB4 RDQB5 RDQB6 RDQB7 RDQB8 SOUT RSCK RCMD Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 5 Rev. 0.0/ Feb. 99 Gnd SA0 SA1 SA2 SVDD Vcc 0.1 µF U0 47K Ohm SDA SCL SDA WP A0 A1 A2 SCL SWP Serial Presence Detect SVDD Note 1: Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain. Gnd Direct RDRAM (128/144Mb) 1 per 2 RDRAMs 0.1 µF SIO0 SIO1 SCK CMD Vref Gnd Direct RDRAM (128/144Mb) 1 per 2 RDRAMs Plus one Near Connector 0.1µF U2 VCMOS SIO0 SIO1 SCK CMD Vref Gnd Direct RDRAM (128/144Mb) 2 per RDRAM 0.1µF U1 SIO0 SIO1 SCK CMD Vref Preliminary HYMR11664/11864 Series Functional Diagram Vdd VREF HYMR11664/11864 Series Preliminary Absolute Maximum Ratings Symbol Parameter Min Max Unit VI,ABS Voltage applied to any RSL or CMOS pin with respect to Gnd - 0.3 VDD + 0.3 V VDD,ABS Voltage on VDD with respect to Gnd - 0.5 VDD + 1.0 V TSTORE Storage temperature - 50 100 °C Min Max Unit DC Recommended Electrical Conditions Symbol Parameter and Conditions VDD Supply voltage 2.50 - 0.13 2.50 + 0.13 V VCMOS CMOS I/O pin power supply - 2.5V controllers: - for 1.8V controllers: 2.5 - 0.13 1.8 - 0.1 2.5 + 0.25 1.8 + 0.2 V V VREF Reference voltage 1.4 - 0.2 1.4 + 0.2 V VIL RSL input low voltage VREF - 0.5 VREF - 0.2 V VIH RSL input high voltage VREF + 0.2 VREF + 0.5 V VIL,CMOS CMOS input low voltage - 0.3 0.5VCMOS - 0.25 V VIH,CMOS CMOS input high voltage 0.5VCMOS + 0.25 VCMOS + 0.3 V VOL,CMOS CMOS output low voltage @ IOL,CMOS = 1mA 0.3 V VOH,CMOS CMOS output high voltage @ IOH,CMOS = -0.25mA IREF VREF current @ V REF,MAX -40 40 µA ISCK,CMD CMOS input leakage current @ (0 ≤ VCMOS ≤ VDD) -40 40 µA ISIN,SOUT CMOS input leakage current @ (0 ≤ VCMOS ≤ VDD) -10.0 10.0 µA VCMOS - 0.3 V AC Electrical Specifications Symbol Parameter and Conditions Min Max Unit Z Module Impedance 25.2 30.8 Ohms TPD Propagation Delay, all RSL signals - 1.2 ns ∆TPD Propagation delay variation of RSL signals with respect to an average clock delay a -0.01 0.01 ns ∆TPD-CMOS Propagation delay variation of SCK and CMD signals with respect to an average clock delay a -0.1 0.1 ns Vα/VIN Attenuation Limit 4.0 % VXF/VIN Forward crosstalk coefficient (300ps input risetime 20%-80%) 0.8 % VXB/VIN Backward crosstalk coefficient (300ps input risetime 20%-80%) 1 % a. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). Page 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Rev. 0.0/ Feb. 99 HYMR11664/11864 Series Preliminary IDD - VDD Supply Current Profile -600 Max -800 Max IDD RIMM module power test conditions Unit IDD1 All RDRAMs in powerdown, self-refresh mode IDD2 All RDRAMs in NAP mode IDD3 All RDRAMs in Standby mode, no commands TBD TBD mA IDD4 All RDRAMs in Active mode, no commands TBD TBD mA IDD5 All RDRAMs running refresh cycles, with tRC = tRC,MIN TBD TBD mA IDD6 All RDRAMs running refresh cycles, with tRC = tREF/# of rows TBD TBD mA IDD7 One RDRAM cycling tRC = min, 1 bank, no COL packets, remainder of RDRAMs in Standby TBD TBD mA IDD8 One RDRAM cycling tRC = min, 1 bank, two dualocts per activate (32-byte transfers), remainder of RDRAMs in Standby TBD TBD mA IDD9 One RDRAM burst read/write, 1 bank open, full bandwidth, COL address changing every dualoct, remainder of RDRAMs in Standby TBD TBD mA TBD/TBDa mA TBD mA a. For modules with a -LP designator. ICMOS - VCMOS Supply Current Profile ICMOS RIMM module power test conditions Max Unit ICMOS1 Current when RDRAMs are in powerdown, self-refresh state TBD mA ICMOS2 Current when CMOS pins are used for register read/write operations (f=1MHz) TBD mA ICMOS3 Current when CMOS pins are used for power management operations (f=100MHz) TBD mA Rev. 0.0/ Feb. 99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 7 HYMR11664/11864 Series Preliminary Timing Parameters The following timing parameters are from the RDRAMs pins, not the RIMM. Please refer to the RDRAM datasheet for detailed timing diagrams. Parameter Description Min -40 -800 Min -45 -800 Min -53 -600 Max Units tRC Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT commands to the same bank. 28 28 28 - tCYCLE tRAS RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRERa command to the same bank. 20 20 20 60µsb tCYCLE tRP Row Precharge time of RDRAM banks - the interval between ROWR packet with PRERa command and next ROWA packet with ACT command to the same bank. 8 8 8 - tCYCLE tPP Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRERa commands to any banks of the same device. 8 8 8 - tCYCLE tRR RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. 8 8 8 - tCYCLE tRCD RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command). Note - the RAS-toCAS delay seen by the RDRAM core (t RCD,CORE) is equal to tRCD,CORE = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. 7 9 7 - tCYCLE tCAC CAS Access delay - the minimum interval from RD command to Q read data. 8 8 8 12 tCYCLE tCWD CAS Write Delay (interval from WR command to D write data. 6 6 6 6 tCYCLE tCC CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). 4 4 4 - tCYCLE tPACKET Length of ROWA, ROWR, COLC, COLM or COLX packet. 4 4 4 4 tCYCLE tRTR Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. 8 8 8 - tCYCLE tOFFP The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLX packet with PREX command to the equivalent ROWR packet with PRER. 4 4 4 4 tCYCLE tRDP Interval from last COLC packet with RD command to ROWR packet with PRER. 4 4 4 - tCYCLE tRTP Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 4 4 4 - tCYCLE a. Or equivalent PREC or PREX command. b. This is a constraint imposed by the core, and is therefore in units of µs rather than t CYCLE. Page 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Rev. 0.0/ Feb. 99 HYMR11664/11864 Series Preliminary Serial Presence Detect Contents To be determined Layout Drawing The following defines the RIMM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate. The maximum height of the module is 31.75mm(1.25”). Rev. 0.0/ Feb. 99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Page 9 Preliminary Page 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYMR11664/11864 Series Rev. 0.0/ Feb. 99