IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 IA70C20 8-Bit Microcontroller Data Sheet IA211030117-05 Page 1 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Copyright 2008 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 fido®, fido1100®, and SPIDER are trademarks of Innovasic Semiconductor, Inc. I2C™ Bus is a trademark of Philips Electronics N.V. Motorola is a registered trademark of Motorola, Inc. IA211030117-05 Page 2 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. 7. 8. Features ..................................................................................................................................... 4 Description ................................................................................................................................ 5 2.1 CPU ............................................................................................................................... 6 2.2 Port A ............................................................................................................................ 6 2.3 Port B ............................................................................................................................ 6 2.4 Port C ............................................................................................................................ 7 2.5 Port D ............................................................................................................................ 7 2.6 Interrupt Controller ....................................................................................................... 7 2.7 Clock Controller ............................................................................................................ 7 2.8 Perf File ......................................................................................................................... 7 2.9 Timer ............................................................................................................................. 7 2.10 ROM .............................................................................................................................. 7 Addressing Modes .................................................................................................................. 10 3.1 Single-Register Addressing Mode .............................................................................. 11 3.2 Dual-Register Addressing Mode ................................................................................. 12 3.3 Peripheral-File Addressing Mode ............................................................................... 13 3.4 Immediate Addressing Mode ...................................................................................... 13 3.5 Program Counter Relative Addressing Mode ............................................................. 14 3.6 Direct Memory Addressing Mode .............................................................................. 15 3.7 Register-File Indirect Addressing Mode ..................................................................... 15 3.8 Indexed Addressing Mode .......................................................................................... 16 Instruction Overview .............................................................................................................. 16 DC Characteristics .................................................................................................................. 24 AC Characteristics .................................................................................................................. 25 70cX0 Errata ........................................................................................................................... 27 Revision History ..................................................................................................................... 27 IA211030117-05 Page 3 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 1. Data Sheet August 19, 2008 Features • • • • • • • • • • • • • • • Pin-for-pin compatible with Texas Instruments TMS70C20 CMOS 8-Bit Microcontroller. Register-to-register architecture. Up to 4K bytes On-Chip ROM. 128 bytes Internal RAM. 13-Bit Timer. Memory-mapped ports for easy adressing. Eight Addressing formats. Single-instruction BCD add and subtract. Two external maskable interrupts. Two power-down modes. Wake-up (160A at 1 MHz typical) Halt, Xtal/clkin = gnd (1 A typical) CMOS technology. Operating Voltage: 5V +/- 10 %. Operating Temperature: Industrial Range (-40oC to +85oC). Maximum Osc Frequency: 5 MHz. Available packages: 44-pin Plastic Leaded Chip Carrier package (PLCC). 40-pin, 600 mil, dual in-line package (DIP). The IA70CX0 is a form, fit, and function replacement for the original Texas Instruments TMS70CX0 CMOS 8-Bit Microcontroller. The IA70CX0 incorporates a CPU, memory, bit I/ O, timer, interrupts and external bus interface logic on a single chip. Typical applications for the IA70CX0 microcontroller include industrial, consumer, computer, telecom and automotive applications. InnovASIC‟s version of the microcontroller includes all the features listed above and is “plug and play” with the original Texas Instruments device. InnovASIC produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. IA211030117-05 Page 4 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 2. Data Sheet August 19, 2008 Description The IA70C20 microcontroller replaces obsolete TI TMS70C20 devices, allowing customers to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts. A block diagram of the 70C20 microcontroller is depicted in Figure 1. Figure 1. IA70C20 Block Diagram IA211030117-05 Page 5 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 The 70C20 microcontroller consists of the following functional blocks: CPU Port A Port B Port C Port D Interrupt Controller Clock Controller Perf File Timer ROM A brief description of each block follows: 2.1 CPU The CPU block contains the microcode sequencer, the ALU, and the CPU registers. The microcode sequencer controls the process of reading and executing the microcode that enables the IA70C20 to execute assembly code. The ALU performs all of the logical and arithmetical operations for the device as required by the microcode. The CPU registers block contains basic information about the function of the IA70C20. The two registers are the 16 bit program counter (PC) and the 8 bit stack pointer (SP). 2.2 Port A Port A is an 8 bit input only port. Pin A7 has a second function as the clock for the on-chip Timer/Event counter. 2.3 Port B Port B is an 8-bit output port. Pins B3-B0 are general purpose bits while pins B7-B4 are dual function pins. When in single-chip mode these pins are general purpose bits, otherwise they are bus control bits. IA211030117-05 Page 6 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 2.4 Data Sheet August 19, 2008 Port C In single-chip mode, Port C is an 8-bit bi-directional port in which each pin may be individually set to be either an input or an output under the control of software. In all other modes, Port C becomes a multiplexed address/data port for the off-chip memory bus providing the least significant byte of a 16bit address. 2.5 Port D In either single-chip or peripheral expansion mode, Port D is an 8-bit bi-directional port in which each pin may be individually set to be either an input or an output under the control of software. In either full expansion or microprocessor mode, Port D contains the most significant byte of the 16-bit address. 2.6 Interrupt Controller There are four interrupt levels INT0-INT3, with INT0 having the highest priority. This block receives the external interrupt and alerts the CPU, enabling servicing of the interrupt. The interrupts are synced to the positive edge of x2_div_2, the divided clock. 2.7 Clock Controller Generates two enable pulse signals, one at ½ x2, and one at 1/16 x2, to clock internal registers at varying speeds. 2.8 Perf File Contains register file registers, data holding registers, and peripheral registers for port operations. 2.9 Timer A programmable timer/event counter. It is an 8 bit modulo-n counter with a programmable pre-scaled clock source. INT2 is an internal interrupt used by the timers. 2.10 ROM Customer specific 2K X 8 instruction ROM. IA211030117-05 Page 7 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Hexadecimal Instruction Table/Opcode Map 0000 0 High LOW 0000 0001 0 NOP 1 IDLE 0010 2 0011 3 0100 4 0101 5 EINT 0110 6 Dint 0111 7 SETC 1000 8 POP ST 1001 9 STSP 1010 A RETS 1011 B RETI 1100 C 1101 D LDSP 1110 E PUSH ST 1111 F 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A MOVP Pn,A MOV Rn,A AND Rn,A OR Rn,A XOR Rn,A BTJO Rn,A BTJZ Rn,A ADD Rn,A MOV %n,A AND %n,A OR %n,A XOR %n,A BTJO %n,A BTJZ %n,A ADD %n,A MOV Rn,B AND Rn,B OR Rn,B XOR Rn,B BTJO Rn,B BTJZ Rn,B ADD Rn,B MOV Rn,Rn AND Rn,Rn OR Rn,Rn XOR Rn,Rn BTJO Rn,Rn BTJZ Rn,Rn ADD Rn,Rn MOV %,n,B AND %,n,B OR %,n,B XOR %,n,B BTJO %,n,B BTJZ %,n,B ADD %,n,B MOV B,A AND B,A OR B,A XOR B,A BTJO B,A BTJZ B,A ADD B,A MOV %n,Pn AND %n,Pn OR %n,R XOR %n,R BTJO %n,R BTJZ %n,R ADD %n,R ADC Rn,A SUB Rn,A SBB Rn,A MPY Rn,A CMP Rn,A DAC Rn,A DSB Rn,A ADC %n,A SUB %n,A SBB %n,A MPY %n,A CMP %n,A DAC %n,A DSB %n,A ADC Rn,B SUB Rn,B SBB Rn,B MPY Rn,B CMP Rn,B DAC Rn,B DSB Rn,B ADC Rn,Rn SUB Rn,Rn SBB Rn,Rn MPY Rn,Rn CMP Rn,Rn DAC Rn,Rn DSB Rn,Rn ADC %,n,B SUB %,n,B SBB %,n,B MPY %,n,B CMP %,n,B DAC %,n,B DSB %,n,B ADC B,A SUB B,A SBB B,A MPY B,A CMP B,A DAC B,A DSB B,A ADC %n,R SUB %n,R SBB %n,R MPY %n,R CMP %n,R DAVC %n,R DSB %n,R A - Register A B - Register A MOVP A,Pn ANDP A,Pn ORP A,Pn XORP A,Pn BTJOP A,Pn BTJZP A,Pn MOVD %n,Rn LDA @n STA @n BR @n CMPA @n CALL @n MOVP Pn,B MOVP Pn,B ANDP B,Pn ORP B,Pn XORP B,Pn BTJOP B,Pn BTJZP B,Pn MOVD Rn,Rn LDA *Rn STA *Rn BR *Rn CMPA *Rn CALL *Rn MOVP %n,Pn ANDP %n,Pn ORP %n,Pn XORP %n,Pn BTJOP %n,Pn BTJZP %n,Pn MOVD %n,(B), Rn LDA @n(B) STA @n(B) BR @n(B) CMPA @n(B) CALL @n(B) Rn - Register File Register %n - Immediate Addressing Pn - Peripheral File Register @n - Direct Addressing IA211030117-05 Page 8 of 27 1011 B 1100 C 1101 D 1110 E 1111 F TSTA/ CLRC MOV A,B TSTB JMP JN/ JLT JZ/ JEQ JC/ JHS JP/ JGT JPZ/ JGE JNZ/ JNE JNC/ JL TRAP 23 TRAP 15 TRAP 14 TRAP 13 TRAP 12 TRAP 11 TRAP 10 TRAP 9 TRAP 8 TRAP 7 TRAP 22 TRAP 21 TRAP 20 TRAP 19 TRAP 18 TRAP 17 TRAP 16 TRAP 6 TRAP 5 TRAP 4 TRAP 3 TRAP 2 TRAP 1 TRAP 0 DEC A INC A INV A CLR A XCHB A SWAP A PUSH A DEC B INC B INV B CLR B XCHB B SWAP B PUSH B MOV A,Rn MOV B,Rn DEC Rn INC Rn INV Rn CLR Rn XCHB Rn SWAP Rn PUSH Rn POP A DJNZ A DECD A RR A RRC A RL A RLC A POP B DINZ B DECD B RR B RRC B RL B RLC B POP Rn DINZ Rn DECD Rn RR Rn RRC Rn RL Rn RLC Rn *Rn - Indirect Addressing http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Signal A0 A1 A2 A3 A4 A5 A6 A7/EC1 B0 B1 B2 B3 B4/ALATCH B5/R/W B6/ENABLE B7/CLKOUT C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 INT1 INT3 RESET MC XTAL2/CLKIN XTAL1 VCC VSS Data Sheet August 19, 2008 Pin PLCC DIP 7 8 9 10 11 18 16 12 3 4 5 41 42 1 43 2 31 32 33 34 35 36 37 38 30 29 27 26 25 24 22 21 14 13 15 40 19 20 28 44 39 23 6 7 8 9 10 16 15 11 3 4 5 37 38 1 39 2 28 29 30 31 32 33 34 35 27 26 24 23 22 21 20 19 13 12 14 36 17 18 25 40 I/O Description I I I I I I I I O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I O Port A. All pins may be used as high-impedance input-only lines. Pin A7/EC1 may also be used as the timer/event counter input. Port B. B0-B7 are general-purpose output-only pins. B4-B7 become memory-expansion control signals in peripheral-expansion, full-expansion, and microprocessor modes. Data output/memory interface address latch strobe. Data output/memory read/write signal. Data output/memory interface enable strobe. Data output/internal clockout. Port C. C0-C7 can be individually selected in software as general-purpose input or output pins in single-chip mode. C0-C7 become the LSB address/data bus in peripheral-expansion, fullexpansion, and microprocessor modes. Port D. D0-D7 can be individually selected in software as general-purpose input or output pins in single-chip or peripheral-expansion modes. D0-D7 become the MSB address/data bus in fullexpansion and microprocessor modes. Highest priority maskable interrupt Lowest priority maskable interrupt Device reset Mode control pin, VCC for microprocessor mode Crystal input for control of internal oscillator Crystal ouput for control of internal oscillator Supply voltage (positive) Ground reference * Also apply to SE70CP160A prototyping device. IA211030117-05 Page 9 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 b1/t1out 4 37 b3/txd b2 5 36 mc a0 7 a0 6 35 c7 a1 a1 7 34 c6 a2 8 33 a3 9 a4/sclk 1 2 3 4 5 6 44 43 42 41 40 39 mc b4/alatch b3/txd 38 b4/alatch 3 Vss b0/t2out b5/r/w_n b6/enable_n b7/clkout 39 b0/t2out 2 b7/clkout b1/t1out Vss 1 b2 40 b5/r/w_n nc U Data Sheet August 19, 2008 b6/enable_n IA70C20 8-Bit Microcontroller Vss 8 38 c7 a2 9 37 c6 c5 a3 10 36 c5 32 c4 a4/sclk 11 35 c4 10 31 c3 a7/ec1 12 34 c3 a7/ec1 11 30 c2 int3_n 13 33 c2 int3_n 12 29 c1 int1_n 14 32 c1 int1_n 13 28 c0 reset_n 15 31 c0 reset_n 14 27 d0 a6/ec2 16 30 d0 a6/ec2 15 26 d1 nc 17 29 d1 a5/rxd 16 25 Vcc xtal2/clkin 17 24 d2 xtal1 18 23 d3 d7 19 22 d4 d6 20 21 d5 d2 Vcc d3 d4 d5 Vss B. 44-Pin PLCC A. Plastic 40-Pin DIP 3. d6 d7 xtal1 xtal2/clkin a5/rxd 18 19 20 21 22 23 24 25 26 27 28 Addressing Modes IA70C20 assembly language supports eight addressing modes. These eight modes are listed in Table 1. A description of each mode follows the table. Table 1. IA70C20 Addressing Modes Addressing Mode Single register LABEL Dual register LABEL Peripheral file LABEL Immediate LABEL Example DEC INC CLR MOV ADD CMP XORP MOVP AND ANDP BTJO IA211030117-05 Page 10 of 27 B R45 R23 B,A A , R17 R32 , R73 A , R17 P42 , B %>C5 , R55 %VALUE , P32 %>D6 , R80 , LABEL http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Program counter relative LABEL 1 Direct memory LABEL Register file indirect Indexed LABEL LABEL 2 3.1 JMP DJNZ BTJO BTJOP LDA CMPA STA BR LABEL A , LABEL %>16 , R12 , LABEL B , P7 , LABEL @>F3D4 @LABEL *R43 @LABEL (B) Single-Register Addressing Mode In single-register addressing mode, a single register denoted by Rn (n is the register file number in the range 0-127) containing an eight-bit operand is used. A and B can denote R0 and R1, respectively. Figure 1 illustrates the object code generated by a single operand instruction for the following cases: IA211030117-05 Page 11 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Figure 1. Single-Register Addressing Mode Object Code Case 1 (PC) Case 2 (PC) OPCODE (PC + 1) Case 1 Rn <inst> A <inst> B <inst> Rn Case 2 3.2 OPCODE Dual-Register Addressing Mode In dual register addressing mode, instructions use a source and a destination register that each contain 8-bit operands. The source register is always listed prior to the destination register in the assembly language. Figure 2 illustrates the byte requirements for all dual addressing mode instructions. Figure 2. Dual-Register Addressing Mode Byte Requirements Destination A Source A B iop Rs B 1 Rd 2 1 2 2 2 3 2 2 3 Bytes Needed for Move Instructions Destination A Source A B iop Rs IA211030117-05 Page 12 of 27 B 2 Rd 3 1 3 2 2 3 2 2 3 Bytes Needed for All Other Instructions http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 3.3 Data Sheet August 19, 2008 Peripheral-File Addressing Mode In peripheral-file addressing mode, instructions perform I/O tasks. register is an 8-bit port that can be referred to as Pn. Each PF Four instructions use peripheral-file addressing mode: MOVP, ANDP, ORP, and XORP. These instructions may use register A or B as the source register and Pn as the destination register. MOVP may also be executed using Pn as the source register and A or B as the destination register. (BTJOP and BTJZP are also peripheral-file instructions but they have a different format.) Figure 3 illustrates the byte requirements of the instructions using the peripheral-file addressing mode. Figure 3. Peripheral-File Addressing Mode Byte Requirements Destination A B Pd Source A 2 B 2 iop 3 Ps 2 2 Bytes Needed for ANDP, ORP, and MOVP 3.4 Destination Pd Source A 3 B 3 iop 4 Bytes Needed for all BTJOP and BTJZP Immediate Addressing Mode In immediate addressing mode instructions use an immediate eight-bit operand. Either a constant value or a label preceded by a percent sign (%) can be used as the immediate value. The MOVD instruction uses 16-bit immediate operands in two special formats. Figure 4 illustrates the simplest case of an instruction using this mode. IA211030117-05 Page 13 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Figure 4. Immediate Addressing Mode Object Code (PC) OPCODE (PC + 1) 3.5 IOP Program Counter Relative Addressing Mode All jump instructions use program counter relative addressing mode. A target address (ta) must be included in any assembly language jump instruction. The offset is calculated as follows: offset = ta – pcn, where pcn is the location of the next instruction and –128 < ta < 127. Figure 5 illustrates object code generated by a jump instruction. Figure 5. Program Counter Relative Addressing Mode Object Code (PC) : N B Y T E S (PC + n) OPCODE IOP D S OFFSET IA211030117-05 Page 14 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 3.6 Data Sheet August 19, 2008 Direct Memory Addressing Mode The operand for a direct addressing mode instruction is located in memory. The location is indicated by a 16-bit address. The 16-bit address is preceded by an @ sign and can be written as a constant value or as a label. Figure 6 shows how the object code produced by an instruction using the direct memory addressing mode generates a 16-bit effective address. Figure 6. Direct Memory Addressing Mode Object Code (PC) (PC + 1) OPCODE ADDR MSB 16-Bit Effective Address (PC + 2) 3.7 ADDR LSB Register-File Indirect Addressing Mode A register pair containing a 16-bit effective address is used in register file indirect addressing mode. The indirect register file address is written as a register number (Rn) preceded by an asterisk (*), that is, *Rn. The LSB of the address is contained in Rn, and the MSB of the address is contained in the previous register (Rn-1). Figure 7 shows how the object code produced by an instruction using register file indirect addressing mode generates a 16-bit effective address. IA211030117-05 Page 15 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 Figure 7. Register-File Indirect Addressing Mode Object Code (PC) (PC + 1) 3.8 Rn-2 Rn-1 Rn Rn+1 OPCODE Rn Rn 16-Bit Effective Address Indexed Addressing Mode In indexed addressing mode, a 16-bit address formed by adding the contents of the B register to a 16-bit direct memory address is used to access the operand. The assembly language statement for the indexed addressing mode contains the direct memory address written as a 16-bit constant value or a label, preceded by an @ sign and followed by a B in parentheses: @LABEL(B). The addition automatically transfers any carries into the MSB. Figure 8 illustrates how the object code produced by an instruction using the indexed addressing mode generates a 16-bit effective address. Figure 8. Indexed Addressing Mode Object Code (PC) (PC + 1) 4. Reg B Index CO DE ADDR MSB ADDR LSB + (PC + 2) 1.1.1.1 OP 16-Bit Effective Address Instruction Overview Following is a listing of assembly language instructions for the IA70C20. Labels, mnemonics, operands, and comments must be separated by at least one space in the assembly code: TMS7000 Family Instruction Overview Mnemonic ADC B,A Rs,A Rs,B Rs,Rd %iop,A %iop,B Opcode Bytes 69 19 39 49 29 59 1 2 2 3 2 2 Cycles Tc(C) 5 8 8 10 7 7 Status CNZI RRRx IA211030117-05 Page 16 of 27 Operation Description (s) + (Rd) + (C) (Rd) Add the source, destination, and carry bit together. Store at the destination. http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller %iop,Rd ADD B,A Rs,A Rs,B Rs,Rd %iop,A %iop,B %iop,Rd AND B,A Rs,A Rs,B Rs,Rd %iop,A %iop,B %iop,Rd ANDP A,Pd B,Pd %iop,Pd Data Sheet August 19, 2008 79 68 18 38 48 28 58 78 63 13 33 43 23 53 73 83 93 A3 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 2 2 3 9 5 8 8 10 7 7 9 5 8 8 10 7 7 9 10 9 11 RRRx (s) + (Rd) (Rd) Add the source and destination operands at the destination address. 0RRx (s) AND (Rd) (Rd) AND the source and destination operands together and store at the destination address. 0RRx (s) AND (Pd) (Pd) AND the source and destination operands together and store at the destination address. Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 17 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic BR @Label @Label(B) *Rn (1) BTJO B,A,Ofst Rn,A,Ofst Rn,B,Ofst Rn,Rd,Ofst %iop,A,Ofst %iop,B,Ofst %iop,Rn,Ofst (1) BJOP A,Pn,Ofst B,Pn,Ofst %>iop,Pn,Ofst Opcode Bytes 8C AC 9C 3 3 2 Cycles Tc(C) 10 12 9 66 16 36 46 26 56 76 2 3 3 4 3 3 4 7 (9) 10 (12) 10 (12) 12 (14) 9 (11) 9 (11) 11 (13) 86 96 A6 3 3 4 11 (13) 10 (12) 12 (14) Status CNZI xxxx If (s [Bit x]) AND (Rn [Bit x]) 0, then (PC) + offset (PC) If the AND of the source and destination operands 0, the PC will be modified to include the offset. 0RRx If (s [Bit x]) AND (Pn [Bit x]) 0, then (PC) + offset (PC) If the AND of the source and destination operands 0, the PC will be modified to include the offset. 67 17 37 47 27 57 77 2 3 3 4 3 3 4 7 (9) 10 (12) 10 (12) 12 (14) 9 (11) 9 (11) 11 (13) 87 97 A7 3 3 4 11 (13) 10 (12) 12 (14) CALL @Label @Label(B) *Rn 8E AE 9E 3 3 2 14 16 13 xxxx CLR B5 C5 D5 B0 1 1 2 1 5 5 7 6 001x CLRC (XADDR) (PC) The PC will be replaced with the contents of the destination operand. 0RRx (1) BTJZ B,A,Ofst Rn,A,Ofst Rn,B,Ofst Rn,Rf,Ofst %>iop,A,Ofst %>iop,B,Ofst %>iop,Rn,Ofst (1) BTJZP A,Pn,Ofst B,Pb,Ofst %>iop,Pb,Ofst A B Rd Operation Description 0RRx If (s [Bit x]) AND NOT(Rn [Bitx]) 0, then (PC) + offset (PC) If the AND of the source and NOT(destination) operands 0, the PC will be modified to include the offset. 0RRx 0RRx If (s [Bit x]) AND NOT(Pn [Bitx]) 0, then (PC) + offset (PC) If the AND of the source and NOT(destination) operands 0, the PC will be modified to include the offset. (SP) + 1 (SP) (PC MSB) ((SP)) (SP) + 1 (SP) (PC LSB) ((SP)) (XADDR) (PC) 0 (Rd) Clear the destination operand. 0 (C) Clears the carry bit. Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 18 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic Opcode Bytes B,A Rn,A Rn,B Rn,Rn %iop,A %iop,B %iop,Rn CMPA @Label @Label(B) *Rn DAC B,A Rs,A Rs,B Rs,Rd %>iop,A %>iop,B %>iop,Rd DEC A B Rd DECD A B Rp DINT 6D 1D 3D 4D 2D 5D 7D 8D AD 9D 6E 1E 3E 4E 2E 5E 7E B2 C2 D2 BB CB DB 06 1 2 2 3 2 2 3 3 3 2 1 2 2 3 2 2 3 1 1 2 1 1 2 1 (1) DJNZ A,Ofst B,Ofst Rd,Ofst BA CA DA 1 2 2 7 (9) 7 (9) 9 (11) 1 2 2 3 2 2 3 1 7 10 10 12 9 9 11 5 RRRx EINT 6F 1F 3F 4F 2F 5F 7F 05 IDLE 01 1 6 xxxx CMP DSB B,A Rs,A Rs,B Rs,Rd %>iop,A %>iop,B %>iop,Rd Cycles Tc(C) 5 8 8 10 7 7 9 12 14 11 7 10 10 12 9 9 11 5 5 7 9 9 11 5 Status CNZI RRRx RRRx RRRx Operation Description (Rn) – (s) computed but not stored Set flags on the result of the source operand subtracted from the destination operand. (A) – (XADDR) computed but not stored Set flags on result of the source operand subtracted from A. (s) + (Rd) + (C) (Rd) (BCD) The source, destination, and the carry bit are added, and the BCD sum is stored at the destination address. Contents on the s + Rd operands initially need to be the BCD. RRRx (Rd) – 1 (Rd) Decrement destination operand by 1. RRRx (Rd) – 1 (Rp) Decrement register pair by 1.C=0 on 0 – FFFF transition 0 (global interrupt enable bit). Clear the I bit. 0000 xxxx (Rd) – 1 (Rd); If (Rd) 0, (PC) + offset (PC) 1111 (Rd) – (s) – 1 + (C) (Rd) (BCD) The source of the operand is subtracted from the destination; this sum is then reduced by 1 and the carry bit is then added to it. The result is stored as a BCD number. Contents on the s + Rd operands initially need to be BCD. 2 (global interrupt enable bit). 3 Set the I bit. (PC) (PC) until interrupt (PC) + 1 (PC) after return from interrupt Stops C execution until an interrupt. Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 19 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic INC INV JMP (1) JC JEQ JHS JL JN JNC JNE JNZ JP JPZ JZ LDA LDSP Opcode Bytes A B Rd A B Rd Ofst B3 C3 D3 B4 C4 D4 D0 1 1 2 1 1 2 2 Cycles Tc(C) 5 5 7 5 5 7 7 Ofst Ofst Ofst Ofst Ofst Ofst Ofst Ofst Ofst Ofst Ofst @Label @Label(B) *Rn E3 E2 E3 E7 E1 E7 E6 E6 E4 E5 E2 8A AA 9A 0D 2 2 2 2 2 2 2 2 2 2 2 3 3 2 1 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 5 (7) 11 13 10 5 Status CNZI RRRx Operation Description (Rd) + 1 (Rd) Increase the destination operand by 1 0RRx NOT(Rd) (Rd) 1‟s complement the destination operand. xxxx (PC) + offset (PC) The PC is modified by an offset to create a new PC value. xxxx If conditions are met, then (PC) + offset (PC) If the needed conditions are met, the PC is modified by the offset to form a new PC value. 0RRx (XADDR) (A) Move the source operand to A. xxxx (B) (SP) Load SP with register B‟s contents. (s) (Rd) Replace the destination operand with the source operand. MOV A,B C0 1 6 0RRx A,Rd D0 2 8 B,A 62 1 5 B,Rd D1 2 7 Rs,A 12 2 8 Rs,B 32 2 8 Rs,Rd 42 3 10 %>iop,A 22 2 7 %>iop,B 52 2 7 %>iop,Rd 72 3 9 MOVD %>iop,Rp 88 4 15 0RRx %>iop(B),Rp A8 4 17 Rp,Rp 98 3 14 MOVP A,Pd 82 2 10 0RRx B,Pd 92 2 9 %>iop,Pd A2 3 11 Ps,A 80 2 9 Ps,B 91 2 8 Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 20 of 27 (s) (Rd) Copy the source register pair to the destination register pair. (s) (Pd) or (Ps) (d) Copy the source operand into the destination operand. http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic Opcode Bytes 1 2 2 3 2 2 3 1 Cycles Tc(C) 44 47 47 49 46 46 48 4 Status CNZI 0RRx 6C 1C 3C 4C 2C 5C 7C 00 B,A Rs,A Rs,B Rd,Rd %>iop,A %>iop,B %>iop,Rd A,Pd B,Pd %>iop,Pd 64 14 34 44 24 54 74 84 94 A4 1 2 2 3 2 2 3 2 2 3 5 8 8 10 7 7 9 10 9 11 0RRx POP A B Rd B9 C9 D9 1 1 2 6 6 8 0RRx POP ST 08 1 6 Loaded from stack A B Rs PUSH ST B8 C8 D8 0E 1 1 2 1 6 6 8 6 xxxx RETI 0B 1 9 Loaded from stack RETS 0A 1 7 xxxx MPY B,A Rs,A Rs,B Rn,Rn %>iop,A %>iop,B %>iop,Rn NOP OR ORP PUSH xxxx 0RRx xxxx Operation Description (s) x (Rn) (A,B) Multiply the source and destination operands, store the result in registers A (MSB) and B (LSB). (PC) + 1 (Rd) Add 1 to the PC (s) OR (Rd) (Rd) Logically OR the source and destination operands, and store the results at the destination address. (s) OR (Pd) (Pd) Logically OR the source and destination operands, and store the results at the destination address. ((SP)) (Rd) (SP) – 1 (SP) Copy the last byte on the stack into the destination address. ((SP)) (ST) (SP) – 1 (SP) Replace the status register with the last byte of the stack. (SP) + 1 (SP) (Rs) (SP) Copy the operand onto the stack. (SP) + 1 (SP) (Status register) ((SP)) Copy the status register onto the stack. ((SP)) (PC) LSByte (SP) –1 (SP) ((SP)) (PC) MSByte (SP) –1 (SP) ((SP)) status register (SP) –1 (SP) ((SP)) (PC LSB) (SP) –1 (SP) ((SP)) (PC MSB) (SP) –1 (SP) Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 21 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic Opcode Bytes A B Rd RLC A B Rd RR A B Rd RRC A B Rd SBB B,A Rs,A Rs,B Rs,Rd %>iop,A %>iop,B %>iop,Rd SETC BE CE DE BF CF DF BC CC DC BD CD DD 6B 1B 3B 4B 2B 5B 7B 07 STA @Label @Label(B) *Rd STSP RL SUB B,A Rs,A Rs,B Rs,Rd %>iop,A %>iop,B %>iop,Rd SWAP A B Rn TRAP 0-23 1 1 2 1 1 2 1 1 2 1 1 2 1 2 2 3 2 2 3 1 Cycles Tc(C) 5 5 7 5 5 7 5 5 7 5 5 7 5 8 8 10 7 7 9 5 Status CNZI b7 R R x 8B AB 9B 09 3 3 2 1 11 13 10 6 0RRRx 6A 1A 3A 4A 2A 5A 7A B7 C7 D7 E8-FF 1 2 2 3 2 2 3 1 1 2 1 5 8 8 10 7 7 9 8 8 10 14 RRRx (SP) (B) Copy the SP into register B. (Rd) – (s) (Rd) Store the destination operand minus the source operand into the destination. RRRx Rd(Hn,Ln) Rd(Ln,Hn) Swap the operand‟s hi and lo nibbles. xxxx (SP) + 1 (SP) (PC MSB) ((SP)) (SP) +1 (SP) (PC LSB) ((SP)) (Entry vector) (PC) b7 R R x b0 R R x b0 R R x RRRx 101x xxxx Operation Description Bit(n) Bit(7) Bit(n + 1) Bit(0) and Carry Bit(n) Bit(n + 1) Carry Bit(0) But(7) Carry Bit(n +1) Bit(n) Bit(0) Bit(7) and Carry Bit(n +1) Bit(n) Carry Bit(7) Bit(0) Carry (Rd) – (s) –1 + (C) (Rd) Destination minus source minus 1 plus carry; stored at the destination address. 1 (C) Set the carry bit. (A) (XADDR) Store A at the destination. Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 22 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Data Sheet August 19, 2008 TMS7000 Family Instruction Overview (Continued) Mnemonic Opcode Bytes TSTA B0 TSTB XCHB A Rn XOR B,A Rs,A Rs,B Rs,Rd %>iop,A %>iop,B %>iop,Rd XORP A,Pd B,Pd %>iop,Pd 1 Cycles Tc(C) 6 Status CNZI 0RRx C1 1 6 0RRx B6 D6 65 15 35 45 25 55 75 85 95 A5 1 2 1 2 2 3 2 2 3 2 2 3 6 8 5 8 8 10 7 7 9 10 9 11 0RRx 0RRx 0RRx Operation Description 0 (C) Set carry bit; set sign and zero flags on the value of register A. 0 (C) Set carry bit; set sign and zero flags on the value register B. (B) (Rn) Swap the contents of register B with (d). (s) XOR (Rd) (Rd) Logically exclusive OR the source and destination operands, store at the destination address. (s) XOR (Pd) (Pd) Logically exclusive OR the source and destination operands, store at the destination. Note: Add two to cycle count if branch is taken Legend: 0 Status bit set always to 0. 1 Status bit set always to 1 R Status bit set to a 1 or a 0 depending on results of operation. x Status bit not affected. b Bit ( ) affected. Ofst Offset IA211030117-05 Page 23 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 5. Data Sheet August 19, 2008 DC Characteristics Ta = -40 C to Ta = 85 C, Supply voltage = 4.5V to 5.5Vdc unless otherwise specified. Parameter Symbol Conditions Input Voltage High Input Voltage Low Input Voltage High Input Voltage Low Input Capacitance Vih Vil Vih Vil Ci Output Voltage High Voh All Except INT1, INT3, RESET_N All Except INT1, INT3, RESET_N INT1, INT3, RESET_N INT1, INT3, RESET_N Not Tested - Guaranteed by process Ioh = 6mA Ioh = 24mA Output Voltage Low Vol Supply Current Icc Wake Up Current Halt Current Device CLK Active Halt Current Device CLK Stopped Input Leakage Current Iccwu Vcc = 5V, fosc(min) 1.35Mhz fosc(max) = 5Mhz Not Measured Icch Limits Unit Min 0.7*Vcc Vcc-0.3 3.22 Vcc-0.3 - Max Vcc+0.3 0.3*Vcc Vcc+0.3 1.84 4 Vcc-0.5 - V Vcc-2.0 - V 9.4 35.0 ma - - - Not Measured - - - Icchs Not Measured - - - Icchs Vcc = 5V - < 10 ua Tri-State Leakage Current Ii 4.5 < Vcc < 5.5 - 10 ua Low Voltage Operation Itsl Normal Operating Conditions 4.5 5.5 V Iol = 10mA IA211030117-05 Page 24 of 27 V V V V pf http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 6. Data Sheet August 19, 2008 AC Characteristics Ta = -40 C to Ta = 85 C, Supply voltage = 4.5V to 5.5 Vdc unless otherwise specified. Reference figures 3.4.2.2,3.4.2.3,3.4.2.4,3.4.2.5, for interface timing relationships. Parameter Symbol Conditions RC Network Frequency fosc R = 15k, C = 47pF, RC Network Osc Input Limits Max 2.1 MHz Vihrc 0.7*Vcc - V Vilrc - 0.3*Vcc V RC Clock to CLKOUTA Delay td Rtest = 1k, Ctest = 1pf Clockout External Cycle Time Clock Internal State Cycle Time Crystal Cycle Time tc( c) tc(s) tc(p) tc( c) = 2/fosc tc(s) = 2/fosc tc(p) = 1/fosc 952 952 741 1481 1481 476 Clockin Pulse Width High Clockin Pulse Width Low tf tw 45% to 55% of 1/fosc 55% to 45% of 1/fosc 333 333 214 214 Clockout Pulse Width High tw(ch) Clockout Pulse Width Low tw(cl) Clockout Rise to ALATCH Fall td(ch-jl) ALATCH Pulse Width High tw(jh) Address Valid High before ALATCH Fall Address Valid Low before ALATCH Fall Address HOLD Low before ALATCH Fall R/W Valid before ALATCH Fall Unit Min 1.4 28 ns Caution! This device is to be used in the single chip mode only. Other operating modes are used for td(ah-jl) functional testing purposes. These characteristics would be used for expansion (Memory) Modes and are td(al-jl) not applicable to the single chip mode. th(jl-al) td(rw-jl) IA211030117-05 Page 25 of 27 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller Signal Name pa_0 pa_1 pa_2 pa_3 pa_4 pa_5 pa_6 pa_7 pb_0 pb_1 pb_2 pb_3 pb_4 pb_5 pb_6 pb_7 pc_0 pc_1 pc_2 pc_3 pc_4 pc_5 pc_6 pc_7 pd_0 pd_1 pd_2 pd_3 pd_4 pd_5 pd_6 pd_7 int1_n int3_n mc Data Sheet August 19, 2008 req. setup measured time setup time 80 80 80 80 80 80 80 80 na na na na na na na na 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 na na na 1.38 1.35 1.33 1.29 1.22 1.15 1.14 1.19 na na na na na na na na 39.06 36.01 38.3 36.42 39.91 39.81 39.14 39.26 1.18 1.15 1.13 1.13 1.14 1.16 1.15 1.13 3.05 3.09 24.98 req. hold time 70 70 70 70 70 70 70 70 na na na na na na na na 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 na na na measured hold time 1.38 1.35 1.33 1.29 1.22 1.15 1.14 1.19 na na na na na na na na 39.06 38.15 38.74 38.53 39.91 39.94 39.99 39.26 1.18 1.15 1.13 1.13 1.14 1.16 1.15 1.13 2.93 3.09 45.68 IA211030117-05 Page 26 of 27 req. clock measured to out clock to out na na na na na na na na 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 na na na na na na na na na na na 24.27 24.33 24.31 24.28 25.83 25.95 25.71 26.68 56.05 56.91 56.54 56.35 57.27 57.77 58.28 56.53 26.27 26.13 26.03 26.1 26.09 26.09 26.44 26.49 na na na http://www.Innovasic.com Customer Support: 1-888-824-4184 IA70C20 8-Bit Microcontroller 7. Data Sheet August 19, 2008 70cX0 Errata When in MC mode, bus contents do not match cycle for cycle outside of qualified data times. IE. When ALE or ENABLE_N are not active, we do not necessarily match. When in MC mode, our part does NOT assert RW_N when performing writes to internal registers. OEM part does assert RW_N during internal writes, but not consistently. Stack addressing „underflow‟ or „under roll‟ behavior. Behavior is different between our part vs. oem when an uneven number of „pop‟ operations are done for a given number of „push‟ operations. If you „pop‟ below register file address 0x00 the OEM will stay at 0x00 for the first illegal pop, then go somewhere below 0x00. Given „n‟ illegal pop operations it will take „n-1‟ push operations to bring stack pointer back to a valid number (0x00). The InnovASIC design will pop down to 0x00 then stop. Any push operations after reaching 0x00 will result in incrementing of stack address. Register File addressing – when performing an instruction which manipulates two register file locations such as decrement double on address 0x00 of register file. OEM operates on first byte at 0x00, then decrements to 0xFF which is NOT a valid register file location. Our part decrements to the top of real physical memory 0x7F. 8. Revision History The table below presents the sequence of revisions to document IA211030117. Date August 19, 2008 Revision 05 Description Corrected control number and reformatted some elements to meet publication standards. IA211030117-05 Page 27 of 27 Page(s) NA http://www.Innovasic.com Customer Support: 1-888-824-4184