IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 ® IA186XL/IA188XL 16-Bit Microcontroller Data Sheet ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 1 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Copyright Data Sheet July 6, 2011 2011 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc. 3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107 MILES™ is a trademark Innovasic Semiconductor, Inc. Intel is a registered trademark of Intel Corporation ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 2 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 TABLE OF CONTENTS List of Figures ..................................................................................................................................5 List of Tables ...................................................................................................................................6 1. Introduction.............................................................................................................................7 1.1 General Description.......................................................................................................7 1.2 Features .........................................................................................................................7 2. Packaging, Pin Descriptions, and Physical Dimensions .........................................................9 2.1 Packages and Pinouts ....................................................................................................9 2.1.1 IA186XL 68 PLCC Package ..........................................................................10 2.1.2 IA188XL 68 PLCC Package ..........................................................................12 2.1.3 PLCC Physical Dimensions ............................................................................14 2.1.4 IA186XL 80 PQFP Package ...........................................................................15 2.1.5 IA188XL 80 PQFP Package ...........................................................................17 2.1.6 PQFP Physical Dimensions ............................................................................19 2.1.7 IA186XL 80 LQFP Package ...........................................................................20 2.1.8 IA188XL 80 LQFP Package ...........................................................................22 2.1.9 LQFP Physical Dimensions ............................................................................24 2.2 IA186XL Pin/Signal Descriptions ..............................................................................25 2.3 IA188XL Pin/Signal Descriptions ..............................................................................31 3. Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................37 4. Functional Description..........................................................................................................39 4.1 Device Architecture.....................................................................................................39 4.1.1 Bus Interface Unit ...........................................................................................39 4.1.2 Clock Generator ..............................................................................................42 4.1.3 Interrupt Control Unit .....................................................................................42 4.1.4 Timer/Counter Unit ........................................................................................42 4.1.5 Chip-Select/Ready Generation Logic .............................................................43 4.1.6 DMA ...............................................................................................................44 4.1.7 DRAM Refresh Control Unit..........................................................................44 4.1.8 Power-Save Control ........................................................................................44 4.2 Operating Modes .........................................................................................................45 4.2.1 Enhanced Mode ..............................................................................................45 4.2.2 Queue Status Mode .........................................................................................45 4.2.3 ONCE Mode ...................................................................................................45 4.2.4 Math Coprocessor (IA186XL Only) ...............................................................45 Table 12. Internal Register Map ..........................................................................................46 5. AC Specifications .................................................................................................................47 5.1 Major Cycle Timings – Read Cycle ............................................................................47 5.2 Major Cycle Timings – Write Cycle ...........................................................................49 5.3 Major Cycle Timings – Interrupt Acknowledge Cycle ...............................................51 5.4 Software Halt Cycle Timings ......................................................................................53 5.5 Clock Timings .............................................................................................................55 5.6 Ready, Peripheral and Queue Status Timings .............................................................56 ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 3 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 6. 7. 8. 9. 10. Data Sheet July 6, 2011 5.7 Reset and HOLD/HLDA Timings...............................................................................57 Instruction Execution Times .................................................................................................61 Innovasic Part Number Cross-Reference..............................................................................66 Errata.....................................................................................................................................69 8.1 Summary .....................................................................................................................69 8.2 Detail ...........................................................................................................................70 Data Sheet Revision History .................................................................................................74 For Additional Information...................................................................................................75 ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 4 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 LIST OF FIGURES Figure 1. IA186XL 68-Lead PLCC Package Diagram .................................................................10 Figure 2. IA188XL 68-Lead PLCC Package Diagram .................................................................12 Figure 3. PLCC Physical Package Dimensions ............................................................................14 Figure 4. IA186XL 80-Lead PQFP Package Diagram .................................................................15 Figure 5. IA188XL 80-Lead PQFP Package Diagram .................................................................17 Figure 6. PQFP Physical Package Dimensions.............................................................................19 Figure 7. IA186XL 80-Lead LQFP Package Diagram .................................................................20 Figure 8. IA188XL 80-Lead LQFP Package Diagram .................................................................22 Figure 9. LQFP Physical Package Dimensions ............................................................................24 Figure 10. IA186XL/IA188XL Functional Block Diagram .........................................................41 Figure 11. Clock Circuit Connection Options ..............................................................................43 Figure 12. Read Cycle Waveforms ...............................................................................................48 Figure 13. Write Cycle Waveforms ..............................................................................................50 Figure 14. Interrupt Acknowledge Cycle Waveforms ..................................................................52 Figure 15. Software Halt Cycle Waveforms .................................................................................54 Figure 16. Clock Waveforms ........................................................................................................58 Figure 17. Reset Waveforms.........................................................................................................58 Figure 18. Synchronous Ready (SRDY) Waveforms ...................................................................58 Figure 19. Asynchronous Ready (ARDY) Waveforms ................................................................59 Figure 20. Peripheral and Queue Status Waveforms ....................................................................59 Figure 21. HOLDA/HLDA Waveforms (Entering Hold) .............................................................60 Figure 22. HOLD/HLDA Waveforms (Leaving Hold) ................................................................60 ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 5 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 LIST OF TABLES Table 1. IA186XL 68-Lead PLCC Pin Listing .............................................................................11 Table 2. IA188XL 68-Lead PLCC Pin Listing .............................................................................13 Table 3. IA186XL 80-Lead PQFP Pin Listing .............................................................................16 Table 4. IA188XL 80-Lead PQFP Pin Listing .............................................................................18 Table 5. IA186XL 80-Lead LQFP Pin Listing .............................................................................21 Table 6. IA188XL 80-Lead LQFP Pin Listing .............................................................................23 Table 7. IA186XL Pin/Signal Descriptions ..................................................................................25 Table 8. IA188XL Pin/Signal Descriptions ..................................................................................31 Table 9. IA186XL and IA188XL Absolute Maximum Ratings ...................................................37 Table 10. IA186XL and IA188XL Thermal Characteristics ........................................................37 Table 11. IA186XL and IA188XL DC Parameters ......................................................................38 Table 13. Major Cycle Timings – Read Cycle .............................................................................47 Table 14. Major Cycle Timings – Write Cycle.............................................................................49 Table 15. Major Cycle Timings – Interrupt Acknowledge Cycle ................................................51 Table 16. Software Halt Cycle Timings .......................................................................................53 Table 17. Clock Timings...............................................................................................................55 Table 18. Ready, Peripheral and Queue Status Timings ..............................................................56 Table 19. Reset and HOLD/HLDA Timings ................................................................................57 Table 20. Instruction Set Timing ..................................................................................................61 Table 21. Innovasic Part Number Cross-Reference for the PLCC ...............................................66 Table 22. Innovasic Part Number Cross-Reference for the PQFP (Special Order only) ..............67 Table 23. Innovasic Part Number Cross-Reference for the LQFP (Special Order only) .............68 Table 24. Summary of Errata ........................................................................................................69 Table 25. Data Sheet Revision History .........................................................................................74 ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 6 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 1. Data Sheet July 6, 2011 Introduction The Innovasic Semiconductor IA186XL and IA188XL microcontrollers are form, fit, and function replacements for the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors. These devices are produced using Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which produces replacement ICs beyond simple emulations, ensures compatibility with the original device, including any “undocumented features.” Additionally, the MILES™ process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. The IA186XL and IA188XL microcontrollers replace the obsolete Intel 80C186XL and 80C188XL devices, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts. 1.1 General Description The Innovasic Semiconductor IA186XL and IA188XL microcontrollers have a set of base peripherals beneficial to many embedded applications and include a standard numeric interface, an interrupt control unit, a chip-select unit/Ready Generation Logic, a DRAM refresh control unit, a Power-Save Control unit, DMA and three 16-bit timer/counters. The IA186XL and IA188XL microcontrollers operate at 5.0 volts ± 10%. The following functional description describes the base architecture of the 80C186XL. The 80C186XL is a very high integration 16-bit microprocessor. It combines some of the most common microprocessor system components onto one chip. The 80C186XL is object-code compatible with the 8086/8088 microprocessors and adds ten new instruction types to the 8086/8088 instruction set. The 80C186XL has two major modes of operation, Compatible and Enhanced. In Compatible Mode, the 80C186XL is completely compatible with the 80186, with the exception of 8087 support. The Enhanced mode adds three new features to the system design. These are PowerSave control, Dynamic RAM refresh, and an asynchronous Numerics Coprocessor interface (80C186XL only). 1.2 Features The primary features of the IA186XL and IA188XL microcontrollers are as follows: Form, fit, and function compatible version of the low power Intel 80C186XL/80C188XL Operation modes: – Enhanced mode o DRAM refresh control unit ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 7 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 o Power-save mode o Direct interface to 80C187 (IA186XL only) – Compatible mode o Pin-for-pin replacement for NMOS 80186/80188 non-numeric applications Integrated feature set – Static, modular CPU – Clock generator – Two independent DMA channels – Programmable interrupt controller – Three programmable 16-bit timers – Dynamic RAM refresh control unit – Programmable memory and peripheral chip select logic – Programmable wait state generator – Local bus controller – Power-save mode – System-level testing support (high impedance test mode) Completely object-code compatible with existing 8086/8088 software and has ten additional instructions over 8086/8088 Crystal supports internal 20–25 MHz operation Direct addressing capability to 1 MByte memory and 64 Kbyte I/O Available in 68-Lead: – Plastic Leaded Chip Carrier (PLCC) Available in 80-Lead: – Plastic Quad Flat Pack (PQFP) – Low Profile Quad Flat Pack (LQFP) Extended Temperature Range (-40°C to +85°C) Chapter 4, Functional Description, provides details of the IA186XL and IA188XL microcontrollers, including the features listed above. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 8 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2. Data Sheet July 6, 2011 Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the IA186XL and the IA188XL is provided separately. Refer to sections, figures, and tables for information on the device of interest. 2.1 Packages and Pinouts The Innovasic Semiconductor IA186XL and IA188XL microcontroller is available in the following packages: 68-Lead Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package 80-Lead Plastic Quad Flat Pack (PQFP), equivalent to original PQFP package 80-Lead Low Profile Quad Flat Pack (LQFP), equivalent to original SQFP package ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 9 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.1 Data Sheet July 6, 2011 IA186XL 68 PLCC Package The pinout for the IA186XL 68 PLCC package is as shown in Figure 1. The corresponding pinout is provided in Table 1. Figure 1. IA186XL 68-Lead PLCC Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 10 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 1. IA186XL 68-Lead PLCC Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name ad15 ad7 ad14 ad6 ad13 ad5 ad12 ad4 vcc ad11 ad3 ad10 ad2 ad9 ad1 ad8 ad0 Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ® Name drq0 drq1 tmr in 0 tmr in 1 tmr out 0 tmr out 1 res_n pcs0_n vss pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n/a1 pcs6_n/a2 lcs_n ucs_n Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Name mcs3_n/nps_n mcs2_n mcs1 _n/error_n mcs0_n/pereq den_n dt/r_n int3/inta1_n int2/inta0_n vcc int1/select_n int0 nmi test_n /busy lock_n srdy hold hlda IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 11 of 75 Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name s0_n s1_n s2_n ardy clkout reset x2 x1 vss ale/qs0 rd_n/qsmd_n wr_n/qs1 bhe_n a19/s6 a18/s5 a17/s4 a16/s3 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.2 Data Sheet July 6, 2011 IA188XL 68 PLCC Package The pinout for the IA188XL 68 PLCC package is as shown in Figure 2. The corresponding pinout is provided in Table 2. NOTE: The Innovasic 68-Lead PLCC package has both an ink mark and an indentation to indicate proper orientation. Pin 1 is designated by the ink mark, as shown in Figure 2. Ink Mark (Pin 1 Indicator) Figure 2. IA188XL 68-Lead PLCC Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 12 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 2. IA188XL 68-Lead PLCC Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Name a15 ad7 a14 ad6 a13 ad5 a12 ad4 vcc a11 ad3 a10 ad2 a9 ad1 a8 ad0 Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ® Name drq0 drq1 tmr in 0 tmr in 1 tmr out 0 tmr out 1 res_n pcs0_n vss pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n/a1 pcs6 _n/a2 lcs_n ucs_n Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Name mcs3_n/nps_n mcs2_n mcs1 _n/error_n mcs0 _n/pereq den_n dt/r_n int3/inta1_n int2/inta0_n vcc int1/select_n int0 nmi test_n /busy lock_n srdy hold hlda IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 13 of 75 Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name s0_n s1_n s2_n ardy clkout reset x2 x1 vss ale/qs0 rd _n/qsmd_n wr _n/qs1 rfsh_n a19/s6 a18/s5 a17/s4 a16/s3 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.3 Data Sheet July 6, 2011 PLCC Physical Dimensions The physical dimensions for the 68 PLCC are as shown in Figure 3. Legend: 1 Symbol Min Nom Max c – 0.008 – D – 0.990 – D1 – 0.953 – D2 – 0.910 D3 – 0.800 – E – 0.990 – E1 – 0.953 – E2 – 0.910 – E3 – 0.800 – 1. Datums D–E and F–G to be determined where center leads exit plastic body at Datum Plane –H– . 2. Datum Plane –H– located at top of mold parting line and coincident with top of lead. Where lead exits plastic body. 1 Note: Controlling dimension in inches. Figure 3. PLCC Physical Package Dimensions ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 14 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 N IA186XL/IA188XL 16-Bit Microcontrollers 2.1.4 Data Sheet July 6, 2011 IA186XL 80 PQFP Package The pinout for the IA186XL 80 PQFP package is as shown in Figure 4. The corresponding pinout is provided in Table 3. Figure 4. IA186XL 80-Lead PQFP Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 15 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 3. IA186XL 80-Lead PQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name ad15 n.c. a16/s3 a17/s4 a18/s5 a19/s6 bhe_n wr_n/qs1 rd_n/qsmd_n ale/qs0 n.c. vss vss n.c. n.c. x1 x2 reset clkout ardy Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ® Name s2_n s1_n s0_n n.c. hlda hold srdy lock_n test_n /busy nmi int0 int1/select_n vcc vcc int2/inta0_n int3/inta1_n dt/r_n den_n mcs0 _n/pereq mcs1 _n/error_n Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name mcs2_n mcs3_n/nps_n n.c. n.c. ucs_n lcs_n pcs6 _n/a2 pcs5_n/a1 pcs4_n pcs3_n pcs2_n pcs1_n vss pcs0_n res_n tmr out 1 tmr out 0 tmr in 1 tmr in 0 drq1 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 16 of 75 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name drq0 n.c. n.c. ad0 ad8 ad1 ad9 ad2 ad10 ad3 ad11 vcc vcc ad4 ad12 ad5 ad13 ad6 ad14 ad7 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.5 Data Sheet July 6, 2011 IA188XL 80 PQFP Package The pinout for the IA186XL 80 PQFP package is as shown in Figure 5. The corresponding pinout is provided in Table 4. Figure 5. IA188XL 80-Lead PQFP Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 17 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 4. IA188XL 80-Lead PQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name a15 n.c. a16/s3 a17/s4 a18/s5 a19/s6 rfsh_n wr_n/qs1 rd_n/qsmd_n ale/qs0 n.c. vss vss n.c. n.c. x1 x2 reset clkout ardy Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ® Name s2_n s1_n s0_n n.c. hlda hold srdy lock_n test_n /busy nmi int0 int1/select_n vcc vcc int2/inta0_n int3/inta1_n dt/r_n den_n mcs0 _n/pereq mcs1 _n/error_n Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name mcs2_n mcs3_n/nps_n n.c. n.c. ucs_n lcs_n pcs6 _n/a2 pcs5_n/a1 pcs4_n pcs3_n pcs2_n pcs1_n vss pcs0_n res_n tmr out 1 tmr out 0 tmr in 1 tmr in 0 drq1 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 18 of 75 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name drq0 n.c. n.c. ad0 a8 ad1 a9 ad2 a10 ad3 a11 vcc vcc ad4 a12 ad5 a13 ad6 a14 ad7 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.6 Data Sheet July 6, 2011 PQFP Physical Dimensions The physical dimensions for the 80 PQFP are as shown in Figure 6. Legend: Notes: 1. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimension D1 and E1 do not include mold mismatch and are determined a datum plane –H– . 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion will not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius of the lead foot. Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 3.40 – – 0.134 A1 0.25 – – 0.010 – – A2 2.55 2.72 3.05 0.100 0.107 0.120 D 23.90 Basic 0.941 Basic D1 20.00 Basic 0.787 Basic E 17.90 Basic 0.705 Basic E1 14.00 Basic 0.551 Basic R2 0.013 – 0.30 0.005 – 0.012 R1 0.013 – – 0.005 – – θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° – – 0° – – a 7° REF 7° REF θ2, θ3 15° REF 15° REF θ2, θ3b c 0.11 0.15 0.23 0.004 0.006 0.009 L 0.73 0.88 1.03 0.029 0.035 0.041 L1 1.95 REF 0.077 REF S 0.40 – – 0.016 – – b 0.30 0.35 0.45 0.012 0.014 0.018 e 0.80 BSC 0.031 BSC D2 18.40 REF 0.724 E2 12.00 REF 0.472 Tolerances of Form and Position aaa 0.25 0.010 bbb 0.20 0.008 ccc 0.20 0.008 aAlloy 42 L/F. bCopper L/F. Figure 6. PQFP Physical Package Dimensions ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 19 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.7 Data Sheet July 6, 2011 IA186XL 80 LQFP Package The pinout for the IA186XL 80 LQFP package is as shown in Figure 7. The corresponding pinout is provided in Table 5. Figure 7. IA186XL 80-Lead LQFP Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 20 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 5. IA186XL 80-Lead LQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name ad0 ad8 ad1 n.c. ad9 ad2 ad10 ad3 ad11 vcc vcc ad4 ad12 ad5 ad13 ad6 ad14 ad7 ad15 vcc Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ® Name a16/s3 a17/s4 a18/s5 a19/s6 n.c. bhe_n wr_n/qs1 rd_n/qsmd_n ale/qs0 vss vss x1 x2 reset n.c. clkout ardy s2_n s1_n s0_n Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name vss hlda hold srdy lock_n test_n/busy nmi int0 int1/select_n vcc vcc int2/inta0_n int3/inta1_n dt/r_n n.c. den_n mcs0_n/pereq mcs1_n/error mcs2_n mcs3_n/nps_n IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 21 of 75 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name vcc ucs_n lcs_n pcs6_n/a2 pcs5_n/a1 pcs4_n pcs3_n pcs2_n pcs1_n vss pcs0_n n.c. res_n tmr out 1 tmr out 0 tmr in 1 tmr in 0 dqr1 dqr0 vss http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.8 Data Sheet July 6, 2011 IA188XL 80 LQFP Package The pinout for the IA188XL 80 LQFP package is as shown in Figure 8. The corresponding pinout is provided in Table 6. Figure 8. IA188XL 80-Lead LQFP Package Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 22 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 6. IA188XL 80-Lead LQFP Pin Listing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name ad0 a8 ad1 n.c. a9 ad2 a10 ad3 a11 vcc vcc ad4 a12 ad5 a13 ad6 a14 ad7 a15 vcc Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ® Name a16/s3 a17/s4 a18/s5 a19/s6 n.c. rfsh_n wr_n/qs1 rd_n/qsmd_n ale/qs0 vss vss x1 x2 reset n.c. clkout ardy s2_n s1_n s0_n Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name vss hlda hold srdy lock_n test_n/busy nmi int0 int1/select_n vcc vcc int2/inta0_n Int3/inta1_n dt/r_n n.c. den_n mcs0_n/pereq mcs1_n/error mcs2_n mcs3_n/nps_n IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 23 of 75 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name vcc ucs_n lcs_n pcs6_n/a2 pcs5_n/a1 pcs4_n pcs3_n pcs2_n pcs1_n vss pcs0_n n.c. res_n tmr out 1 tmr out 0 tmr in 1 tmr in 0 dqr1 dqr0 vss http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.1.9 Data Sheet July 6, 2011 LQFP Physical Dimensions The physical dimensions for the 80 LQFP are as shown in Figure 9. Legend: Symbol A A1 A2 b b1 c c1 D D1 E E1 e L L1 R1 R2 S θ θ1 θ2 θ3 Dimension in mm Min Nom Max – – 1.60 0.05 – 0.15 1.35 1.40 1.45 0.17 0.22 0.27 0.17 0.20 0.23 0.09 – 0.20 0.09 – 0.16 14.00 BSC 12.00 BSC 14.00 BSC 12.00 BSC 0.50 BSC 0.45 0.60 0.75 1.00 REF 0.08 – – 0.08 – 0.20 0.20 – – 0° 3.5° 7° 0° – – 11° 12° 13° 11° 12° 13° Dimension in Inch Min Nom Max – – 0.063 0.002 – 0.006 0.053 0.055 0.057 0.007 0.009 0.011 0.007 0.008 0.009 0.004 – 0.008 0.004 – 0.006 0.551 BSC 0.472 BSC 0.551 BSC 0.472 BSC 0.020 BSC 0.018 0.024 0.030 0.039 REF 0.003 – – 0.003 – 0.008 0.008 – – 0° 3.5° 7° 0° – – 11° 12° 13° 11° 12° 13° 1. To be determined at seating plane C. 2. Dimensions D1 and E1 do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimension b does not include dambar protrusion. Dambar cannot be located on the lower radius of the foot. 4. Exact shape of each corner is optional. 5. These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. Notes: 1. Exact shape of each corner is optional. 2. Controlling dimension: mm. Figure 9. LQFP Physical Package Dimensions ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 24 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.2 Data Sheet July 6, 2011 IA186XL Pin/Signal Descriptions Descriptions of the pin and signal functions for the IA186XL microcontroller are provided in Table 7. Several of the IA186XL pins have different functions depending on the operating mode of the device. Each of the different signals supported by a pin is listed and defined in Table 7, indexed alphabetically in the first column of the table. Additionally, the name of the pin associated with the signal as well as the pin numbers for the PLCC, PQFP, and LQFP packages are provided in the “Pin” column. Signals not used in a specific package type are designated “NA.” Table 7. IA186XL Pin/Signal Descriptions Signal a1 a2 a16 a17 a18 a19 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 Name pcs5_n/a1 pcs6_n/a2 a16/s3 a17/s4 a18/s5 a19/s6 Pin PLCC 31 32 68 67 66 65 PQFP 48 47 3 4 5 6 LQFP 65 64 21 22 23 24 Description Latched address bit a1. Output. Latched address bit a2. Output. address bits 16–19. Output. These pins provide the four most-significant bits of the Address Bus during T1 only. During T2, T3, TW and T4 they provide bus status. ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 17 15 13 11 8 6 4 2 16 14 12 10 7 5 3 1 64 66 68 70 74 76 78 80 65 67 69 71 75 77 79 1 1 3 6 8 12 14 16 18 2 5 7 9 13 15 17 19 address/data bits 0–15. Input/Output. These pins provide the multiplexed Address Bus and Data Bus. During the address portion of the IA186XL bus cycle, Address Bits [0–15] are presented on the bus and can be latched using the ale signal (see next table entry). During the data portion of the bus cycle, data are present on these lines. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 25 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 7. IA186XL Pin/Signal Descriptions (Continued) Signal ale ardy bhe_n Name ale/qs0 Pin PLCC 61 PQFP 10 LQFP 29 ardy 55 20 37 bhe_n 64 7 26 Description address latch enable. Output. Active High. This signal is used to latch valid address information on the falling edge of ale during the address portion of a bus cycle. asynchronous ready. Input. Indicates to the processor the addressed memory space or i/o device will complete the transfer. byte high enable. Output. Active Low. When bhe_n is asserted (low), it indicates that the bus cycle in progress is transferring data over the upper half of the data bus. Additionally, bhe_n and ad0 encode the following bus information: ad0 0 0 1 1 busy test_n/busy 47 29 46 clkout clkout 56 19 36 den_n den_n 39 38 56 drq0 drq1 18 19 61 60 79 78 drq0 drq1 ® bhe_n Bus Status 0 1 0 1 Word Transfer Even Byte Transfer Odd Byte Transfer Refresh Operation (Enhanced Mode) Note: bhe_n is used as refresh_n in the IA188XL. busy. Input. Active High. Used in Enhanced Mode. When the busy input is asserted, it causes the IA186XL to suspend operation during the execution of the Intel 80C187 Numerics Coprocessor instructions. Operation resumes when the pin is sampled low. clock output. Output. The clkout pin provides a timing reference for inputs and outputs of the IA186XL. This clock output is one-half the input clock (clkin) frequency. The clkout signal has a 50% duty cycle, transitioning every falling edge of clkin. data enable. Output. Active Low. This signal is used to enable bidirectional transceivers in a buffered system. The den_n signal is asserted (low) only when data are to be transferred on the bus. dma request 0 or 1. Input. Asserted high by an external device to request DMA Channel 0 or 1 to perform a transfer. These signals are level-triggered and internally synchronized. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 26 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 7. IA186XL Pin/Signal Descriptions (Continued) Signal dt/r_n Name dt/r_n Pin PLCC 40 PQFP 37 LQFP 54 error_n mcs1_n/error_n 37 40 58 hlda 51 25 42 hlda hold hold 50 26 43 int0 int1 int2 int3 int0 int1 int2/inta0_n int3/inta1_n 45 44 42 41 31 32 35 36 48 49 52 53 Description data transmit/receive. Output. This signal is used to control the direction of data flow for bidirectional buffers in a buffered system. When dt/r_n is high, the direction indicated is transmit; when dt/r_n is low, the direction indicated is receive. error. Input. Active Low. When this signal is asserted (low), it indicates that the last numerics coprocessor operation resulted in an exception condition. hold acknowledge. Output. Active High. When hlda is asserted (high), it indicates that the IA186XL has relinquished control of the local bus to another bus master in response to a HOLD request (see next table entry). When hlda is asserted, the IA186XL data bus and control signals are floated allowing another bus master to drive the signals directly. hold. Input. Active High. This signal is a request indicating that an external bus master wishes to gain control of the local bus. The IA186XL will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix. interrupt N (N = 0–3). Input. Active High. These maskable inputs interrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0: int1: int2: int3: inta 0_n inta 1_n int2/inta0_n int3/inta1_n ® 42 41 35 36 52 53 Type 12 Type 13 Type 14 Type 15 To allow interrupt expansion, int0 and int1 can be used with the interrupt acknowledge signals inta0_n and inta1_n (see next table entries). interrupt acknowledge. Output. Active low. When used with external interrupt controllers. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 27 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 7. IA186XL Pin/Signal Descriptions (Continued) Signal lcs_n Name lcs_n Pin PLCC 33 PQFP 46 LQFP 63 lock_n lock_n 48 28 45 mcs0_n mcs1_n mcs2_n mcs3_n n.c. nmi nps_n pcs0_n pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n pcs6_n pereq mcs0_n/pereq mcs1_n/error_n mcs2_n mcs3_n/nps_n n.c. 38 37 36 35 NA nmi mcs3_n/nps_n pcs0_n pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n/a1 pcs6_n/a2 mcs0_n/pereq ® 57 58 59 60 4, 25, 35, 55, 72 46 39 40 41 42 2, 11, 14, 15, 24, 43, 44, 62, 63 30 35 25 27 28 29 30 31 32 38 42 54 52 51 50 49 48 47 39 60 71 69 68 67 66 65 64 57 47 Description lower chip select. Output. Active Low. This pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. lock. Output. Active Low. When asserted (low), this signal indicates that the bus cycle in progress cannot be interrupted. While lock_n is active, the IA186XL will not service bus requests such as HOLD. When resin_n is active, this pin is weakly held high and must not be driven low. mid-range memory chip select. Output. not connected. non-maskable interrupt. Input. Active High. When the nmi signal is asserted (high) it causes a Type 2 interrupt. numeric processor select peripheral chip select signals 0–6. Output. numerics coprocessor external request. Input. Active High. When asserted (high), this signal indicates that a data transfer between an Intel 80C187 Numerics Coprocessor and the CPU is pending. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 28 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 7. IA186XL Pin/Signal Descriptions (Continued) Signal qs0 qs1 Name ale/qs0 wr_n/qs1 Pin PLCC 61 63 PQFP 10 8 LQFP 29 27 Description queue status 0, queue status 1. Output. QS1 0 0 qsmd_n rd_n rd_n/qsmd_n rd_n/qsmd_n 62 62 9 9 28 28 res_n res_n 24 55 73 reset reset 57 18 34 s0_n s1_n s2_n s0_n s1_n s2_n 52 53 54 23 22 21 40 39 38 QS0 0 No Queue operations 1 First byte of opcode pulled from Queue 1 1 Additional bytes pulled from Queue 1 0 Queue is flushed queue status mode. Input. Sampled at reset. read. output. Active Low. When asserted (low), rd_n indicates that the accessed memory or I/O device must drive data from the location being accessed onto the data bus. res_n. Input. Forces the processor to terminate present activity, reset the internal logic, and enter a dormant state until res_n goes high. reset is an output signal indicating the CPU is being reset. It can be used as a system reset. status [2:0]_n are outputs. During a bus cycle, the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s3 s4 s5 s6 srdy a16/s3 a17/s4 a18/s5 a19/s6 68 67 66 65 3 4 5 6 21 22 23 24 srdy 49 27 44 ® s0_n Bus Cycle Status 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Processor HALT 1 0 0 Queue Instruction Fetch 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 No Bus Activity status [6:3] are Outputs. Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3 T1 A19 A18 A17 A16 T2 N 0 0 0 T3 N 0 0 0 Tw N 0 0 0 T4 N 0 0 0 ____________ N = 0 for CPU bus cycle. N = 1 for DMA or refresh cycle. synchronous ready. Input. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 29 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 7. IA186XL Pin/Signal Descriptions (Continued) Signal test_n Name test_n/busy Pin PLCC 47 PQFP 29 LQFP 46 tmr in 0 tmr in 0 20 59 77 tmr in 1 tmr in 1 21 58 76 tmr out 0 tmr out 0 22 57 75 tmr out 1 tmr out 1 23 56 74 ucs_n ucs_n 34 45 62 vcc vcc 9, 43 33, 34, 72, 73 vss vss 26, 60 12, 13, 53 wr_n/qs1 63 8 10, 11, 20, 50, 51, 61 30, 31, 41, 70, 80 27 x1 x2 59 58 16 17 32 33 wr_n x1 x2 ® Description test. Input. Active Low. When the test_n input is high (i.e., not asserted), it causes the IA186XL to suspend operation during the execution of the WAIT instruction. Operation resumes when the pin is sampled low (asserted). timer 0 input. Input. Depending on the Timer Mode programmed for Timer 0, this input is used either as clock input or a control signal. timer 1 input. Input. Depending on the Timer Mode programmed for Timer 1, this input is used either as clock input or a control signal. timer 0 output. Output. Depending on the Timer Mode programmed for Timer 0, this output can provide a single pulse or a repetitive waveform. timer 1 output. Output. Depending on the Timer Mode programmed for Timer 1, this output can provide a single clock or a repetitive waveform. upper chip select. Output. Active Low. This pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. Power (VCC). This pin provides power for the IA186XL device. It must be connected to a +5V DC power source. Ground (VSS). This pin provides the digital ground (0V) for the IA186XL. It must be connected to a VSS board plane. write. Output. Active Low. When asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or I/O device. x1 and x2 are inputs for the crystal IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 30 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 2.3 Data Sheet July 6, 2011 IA188XL Pin/Signal Descriptions Descriptions of the pin and signal functions for the IA188XL microcontroller are provided in Table 8. Several of the IA188XL pins have different functions depending on the operating mode of the device. Each of the different signals supported by a pin is listed and defined in Table 8, indexed alphabetically in the first column of the table. Additionally, the name of the pin associated with the signal as well as the pin numbers for the PLCC, QFP, and LQFP packages are provided in the “Pin” column. Table 8. IA188XL Pin/Signal Descriptions Signal a1 a2 a16 a17 a18 a19 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 Name pcs5_n/a1 pcs6_n/a2 a16/s3 a17/s4 a18/s5 a19/s6 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 ® Pin PLCC 31 32 68 67 66 65 17 15 13 11 8 6 4 2 16 14 12 10 7 5 3 1 PQFP 48 47 3 4 5 6 64 66 68 70 74 76 78 80 65 67 69 71 75 77 79 1 LQFP 65 64 21 22 23 24 1 3 6 8 12 14 16 18 2 5 7 9 13 15 17 19 Description Latched address bit a1. Output. Latched address bit a2. Output. address bits 16–19. Output. These pins provide the four most-significant bits of the Address Bus during T1 only. During T2, T3, TW and T4 they provide bus status. address/data bits 0 - 15. Input/Output. These pins provide the multiplexed Address Bus and Data Bus. During the address portion of the IA188XL bus cycle, address bits 0 through 15 are presented on the bus and can be latched using the ale signal (see next table entry). During the data portion of the IA188XL bus cycle, data are present on these lines. valid address information is provided for the entire bus cycle IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 31 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 8. IA188XL Pin/Signal Descriptions (Continued) Signal ale Name ale/qs0 Pin PLCC 61 PQFP 10 LQFP 29 ardy ardy 55 20 37 clkout clkout 56 19 36 den_n den_n 39 38 56 drq0 drq1 drq0 drq1 18 19 61 60 79 78 dt/r_n dt/r_n 40 37 54 ® Description address latch enable. Output. Active High. This signal is used to latch address information during the address portion of a bus cycle. asynchronous ready. Input. Indicates to the processor the addressed memory space or i/o device will complete the transfer. clock output. Output. The clkout pin provides a timing reference for inputs and outputs of the IA188XL. This clock output is one-half the input clock (clkin) frequency. The clkout signal has a 50% duty cycle, transitioning every falling edge of clkin. data enable. Output. Active Low. This signal is used to enable bidirectional transceivers in a buffered system. The den_n signal is asserted (low) only when data are to be transferred on the bus. dma request 0 or 1. Input. Asserted high by an external device to request DMA Channel 0 or 1 to perform a transfer. These signals are level-triggered and internally synchronized data transmit/receive. Output. This signal is used to control the direction of data flow for bidirectional buffers in a buffered system. When dt/r_n is high, the direction indicated is transmit; when dt/r_n is low, the direction indicated is receive. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 32 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 8. IA188XL Pin/Signal Descriptions (Continued) Signal hlda Pin PLCC 51 Name hlda PQFP 25 LQFP 42 hold hold 50 26 43 int0 int1 int2 int3 int0 int1 int2/inta0_n int3/inta1_n 45 44 42 41 31 32 35 36 48 49 52 53 Description hold acknowledge. Output. Active High. When hlda is asserted (high), it indicates that the IA188XL has relinquished control of the local bus to another bus master in response to a HOLD request (see next table entry). When hlda is asserted, the IA188XL data bus and control signals are floated allowing another bus master to drive the signals directly. hold. Input. Active High. This signal is a request indicating that an external bus master wishes to gain control of the local bus. The IA188XL will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix. interrupt N (N = 03). Input. Active High. These maskable inputs interrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0: int1: int2: int3: inta 0_n inta 1_n lcs_n int2/inta0_n int3/inta1_n lcs_n ® 42 41 33 35 36 46 52 53 63 Type 12 Type 13 Type 14 Type 15 To allow interrupt expansion, int0 and int1 can be used with the interrupt acknowledge signals inta0_n and inta1_n (see next table entries). interrupt acknowledge. Output. Active low. When used with external interrupt controllers. lower chip select. Output. Active Low. This pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 33 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 8. IA188XL Pin/Signal Descriptions (Continued) Signal lock_n Name lock_n mcs0_n mcs0_n/pereq mcs1_n mcs1_n/error_n mcs2_n mcs2_n mcs3_n mcs3_n/nps_n n.c. n.c. Pin PLCC 48 38 37 36 35 NA PQFP 28 nmi nmi 46 39 40 41 42 2, 11, 14, 15, 24, 43, 44, 62, 63 30 pcs0_n pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n pcs6_n qs0 qs1 pcs0_n pcs1_n pcs2_n pcs3_n pcs4_n pcs5_n/a1 pcs6_n/a2 ale/qs0 wr_n/qs1 25 27 28 29 30 31 32 61 63 54 52 51 50 49 48 47 10 8 LQFP 45 57 58 59 60 4, 25, 35, 55, 72 71 69 68 67 66 65 64 29 27 47 Description lock. Output. Active Low. When asserted (low), this signal indicates that the bus cycle in progress cannot be interrupted. While lock_n is active, the IA188XL will not service bus requests such as HOLD. When resin_n is active, this pin is weakly held high and must not be driven low. mid-range memory chip select. Output. not connected non-maskable interrupt. Input. Active High. When the nmi signal is asserted (high) it causes a Type 2 interrupt . peripheral chip select signals 0–6. Output. queue status 0, queue status 1. Output. QS1 0 0 qsmd_n rd_n rd_n/qsmd_n rd_n/qsmd_n ® 62 62 9 9 28 28 QS0 0 No Queue operations 1 First byte of opcode pulled from Queue 1 1 Additional bytes pulled from Queue 1 0 Queue is flushed queue status mode. Input. Sampled at reset. read. output. Active Low. When asserted (low), rd_n indicates that the accessed memory or I/O device must drive data from the location being accessed onto the data bus. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 34 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 8. IA188XL Pin/Signal Descriptions (Continued) Signal res_n Name res_n Pin PLCC 24 PQFP 55 LQFP 73 reset reset 57 18 34 rfsh_n rfsh_n 64 7 26 s0_n s1_n s2_n s0_n s1_n s2_n 52 53 54 23 22 21 40 39 38 s3 s4 s5 s6 a16/s3 a17/s4 a18/s5 a19/s6 68 67 66 65 3 4 5 6 21 22 23 24 srdy test_n srdy test_n/busy 49 47 27 29 44 46 tmr in 0 tmr in 0 20 59 77 tmr in 1 tmr in 1 21 58 76 ® Description res_n. Input. Forces the processor to terminate its present activity, reset the internal logic, and enter a dormant state until res_n goes high. reset is an output signal indicating the CPU is being reset. It can be used as a system reset. refresh. Output. rfsh_n is asserted low to indicate a refresh bus cycle. status [2:0]_n are outputs. During a bus cycle the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s0_n Bus Cycle Status 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Processor HALT 1 0 0 Queue Instruction Fetch 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 No Bus Activity status [6:3] are outputs. Bus Cycle A19/s6 A18/s5 A17/s4 A16/s3 T1 A19 A18 A17 A16 T2 N 0 0 0 T3 N 0 0 0 Tw N 0 0 0 T4 N 0 0 0 ____________ N = 0 for CPU bus cycle. N = 1 for DMA or refresh cycle. synchronous ready. Input. test. Input. Active Low. When the test_n input is high (i.e., not asserted), it causes the IA188XL to suspend operation during the execution of the WAIT instruction. Operation resumes when the pin is sampled low (asserted). timer 0 input. Input. Depending on the Timer Mode programmed for Timer 0, this input is used either as clock input or a control signal. timer 1 input. Input. Depending on the Timer Mode programmed for Timer 1, this input is used either as clock input or a control signal. IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 35 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 8. IA188XL Pin/Signal Descriptions (Continued) Signal tmr out 0 Name tmr out 0 Pin PLCC 22 PQFP 57 LQFP 75 tmr out 1 tmr out 1 23 56 74 ucs_n ucs_n 34 45 62 vcc vcc 9, 43 33, 34, 72, 73 vss vss 26, 60 12, 13, 53 wr_n wr_n/qs1 63 8 10, 11, 20, 50, 51, 61 30, 31, 41, 70, 80 27 x1 x2 x1 x2 59 58 16 17 32 33 ® Description timer 0 output. Output. Depending on the Timer Mode programmed for Timer 0, this output can provide a single pulse or a repetitive waveform. timer 1 output. Output. Depending on the Timer Mode programmed for Timer 1, this output can provide a single pulse or a repetitive waveform. upper chip select. Output. Active Low. This pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. Power (VCC). This pin provides power for the IA188XL device. It must be connected to a +5V DC power source. Ground (VSS). This pin provides the digital ground (0V) for the IA186XL. It must be connected to a VSS board plane. write. Output. Active Low. When asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or I/O device. x1 and x2 are inputs for the crystal IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 36 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 3. Data Sheet July 6, 2011 Maximum Ratings, Thermal Characteristics, and DC Parameters For the Innovasic Semiconductor IA186XL and IA188XL microcontrollers, the absolute maximum ratings, thermal characteristics, and DC parameters are provided in Tables 9 through 11, respectively. Table 9. IA186XL and IA188XL Absolute Maximum Ratings Parameter Storage Temperature Supply Voltage with Respect to vss Voltage on Pins other than Supply with Respect to vss Rating −40°C to +125°C −0.3V to +6.0V −0.3V to +(Vcc + 0.3)V Table 10. IA186XL and IA188XL Thermal Characteristics Symbol TA PD ΘJa TJ Characteristic Ambient Temperature Power Dissipation 68-Lead PLCC Package 80-Lead PQFP Package 80-Lead LQFP Package Average Junction Temperature ® Value -40°C to 85°C MHz ICC V/1000 32 46 52 TA + (PD ΘJa) IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 37 of 75 Units °C W °C/W °C http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 11. IA186XL and IA188XL DC Parameters Symbol 5.0 Volt Operation VCC Parameter Min Max Supply Voltage 4.5 5.5 V – VIL Input Low Voltage −0.3 0.3 VCC V Input Hysteresis on resin_n = 0.50V VIH Input High Voltage VCC + 0.3 V _ VOL VOH Output Low Voltage VCC = 5.0V Output High Voltage VCC = 4.5V Input Leakage Current for Pins: ad0ad15, ad0-ad7 (IA188XL), resin_n, clkin, t0in_in, t1in_in, drq0, drq1, int0, int1, rmi, hold, srdy, ardy, int2_inta0_n, int3_inta1_n 0.4 - V V IOL = 12 mA IOH = −12 mA – ±1 µA 0V ≤ VIN ≤ VCC -.227 -.833 mA VIN = 0V – 0 0 ± 10 90 5 5 µA mA pF pF 0.45V ≤ VOUT ≤ VCC TF = 1 MHz TF = 1 MHz 0.7 VCC – 3.5 Units Notes ILEAK Input Leakage Current for pin (@5V): ucs_n, lcs_n, mcs0_n_pereq, mcs1_n_error_n, rd_n, test_n_busy ILO Output Leakage Current IID Supply Current (IDLE) - @ 50 MHz CIN Input Pin Capacitance COUT Output Pin Capacitance Operating temperature is −40°C to 85°C. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 38 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 4. Data Sheet July 6, 2011 Functional Description The follow descriptions apply to both the IA186XL and IA188XL unless otherwise noted. Module descriptions are followed by descriptions of special operating modes. Additional information on the operation and programming of the 80C186XL/80C188XL can be found in the following Intel® publications: 80C186XL/80C188XL and 80L186XL/80L188XL 16-Bit High-Integration Embedded Processors (272433-006) 80C186XL/80C188XL Microprocessor User’s Manual (270830-00n) 4.1 Device Architecture Architecturally, the IA186XL microcontrollers include the following functional modules: Bus Interface Unit Clock Generator Interrupt Control Unit Timer/Counter Unit Chip-Select Unit Refresh Control Unit Power-Save Control DMA Unit A functional block diagram of the IA186XL/IA188XL is shown in Figure 10. Descriptions of the functional modules are provided in the follow subsections. Control registers for the peripheral modules are located in a 256 byte control block. This block can be mapped to either memory or I/O space. The offset map for addressing these registers is given in Table 12. 4.1.1 Bus Interface Unit A local bus controller generates the local bus control signals. It also employs a hold/hlda protocol for relinquishing the local bus to other bus masters. Its outputs can be used to enable external buffers and to direct the flow of data on and off the local bus. The bus controller is responsible for generating 20 bits of address, read and write strobes, bus-cycle status information and data. This controller is also responsible for reading data from the local bus during a read operation. Synchronous and asynchronous ready input pins are provided to extend a bus cycle beyond the minimum four clocks. The bus controller also generates two control signals (den_n ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 39 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 and dt/r_n) when interfacing to external transceiver chips. This capability allows the addition of transceivers for simple buffering of the multiplexed address/data bus. During reset, the local bus controller performs the following actions: 1. 2. 3. 4. 5. 6. Floats ad0–15 (ad0–8), a16–19 (a9–a19), bhe_n (rfsh_n), dt/r_n Drives ale LOW Drives hlda LOW Drives lock_n HIGH and then floats Drives den_n, rd_n, and wr_n HIGH for one clock cycle, then floats them Drives s0_n, s1_n and s2_n to the inactive state (all HIGH) and then floats them ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 40 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Figure 10. IA186XL/IA188XL Functional Block Diagram ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 41 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 The rd_n/qsmd_n, ucs_n, lcs_n, mcs0_n/pereq, mcs1_n/error_n, and test_n/busy pins include internal pull-ups that are active while res_n is applied. The state of these pins during reset controls invoking various alternative operating modes as described below: 1 ONCE Mode – ucs_n and lcs_n driven low. 2 Enhanced Mode – test_n/busy driven low then high. 3 Queue Status Mode – rd_n/qsmd_n driven low. 4.1.2 Clock Generator The IA186XL/IA188XL uses an on-chip clock generator to supply internal and external clocks. The clock generator makes use of a crystal oscillator and includes a divide-by-two counter. Figure 11 shows the various operating modes of the clock circuit. The clock circuit can use either a parallel resonant fundamental mode crystal network (A) or a third-overtone mode crystal network (B), or it can be driven by an external clock source (C). The following parameters are recommended when choosing a crystal: Temperature Range: Application Specific ESR (Equivalent Series Resistance): 60 max C0 (Shunt Capacitance of Crystal): 7.0 pF max CL (Load Capacitance): 20 pF ± 2 pF Drive Level: 2 mW max 4.1.3 Interrupt Control Unit The IA186XL operates with several interrupt sources. A separate Interrupt Control Unit manages all sources based on priority to be individually handled by the CPU. The DMA and Timers produce internally generated requests. There are five externally generated interrupts - a single NMI and 4 others. 4.1.4 Timer/Counter Unit There are three programmable internal timers in the IA186XL. Two are very flexible and can be configured for many tasks. Each of these has a single input used for either control or clocking, and a single output to generate waveforms. The third timer is simpler and can only be clocked from an internal source. It can be used for simple timing applications. It can also be used as a prescaler to the other two timers or as a trigger for DMA requests. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 42 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Figure 11. Clock Circuit Connection Options 4.1.5 Chip-Select/Ready Generation Logic The IA186XL provides programmable chip-select generation for memories and peripherals. The chip can be programmed to provide READY or WAIT state generation. It can also provide latched address bits A1 and A2. Chip select behavior is the same whether the access is generated by the CPU or the DMA. A total of 6 chip selects are dedicated for different memory ranges. A single select for upper memory (ucs_n), with a fixed end address of 0FFFFH, is good for use as system memory since the reset vector points to FFFF0H. A single select for lower memory (lcs_n), with a fixed start address of 0H, is good for interrupt vectors which reside beginning at address 00000H. There are also four selects for anywhere else (exclusive of ucs_n and lcs_n areas) in the 1 Mbyte memory in the user-locatable memory block. For the middle chip selects, the base address and block size are programmable, while only the block size for the upper and lower chip selects are programmable. Seven additional chip selects can be programmed to access either peripherals or memory in seven contiguous fixed blocks of 128 bytes each. A single base address is programmable for these chip selects. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 43 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 A programmable number of wait states (0 - 3) can be used to generate an internal ready for each chip select range. The IA186XL can be programmed to use or not use the external ready signal with or without the internal wait states from the internal ready being factored in. At reset, the Chip-Select/Ready Logic will be configured as follows: 1. All chip-select outputs will be driven HIGH 2. Exiting RESET, the UCS control register (UMCS) is set to FFFBH, providing chip select to a 1-Kbyte block of memory with 3 wait states in combined with external ready. 3. All other chip select control registers are undefined after reset. The CPU must configure these control registers before the corresponding chips selects will become active. 4.1.6 DMA The IA186XL includes a DMA controller with two channels. Transfers can occur between any combination of Memory and I/O space, to either odd or even address. Data size can be either 8 or 16 bits, except on the IA188XL it can only be 8 bits. There are separate 20-bit source and destination pointers for each channel. These pointers can be configured to increment, decrement or stay static after each transfer. For word transfers, pointers are incremented or decrement by two and for byte transfers, by one. One bus cycle is required to fetch data and one cycle to deposit it. 4.1.7 DRAM Refresh Control Unit When in Enhanced Mode, the IA186XL supports DRAM refresh cycles. Reads are automatically generated at a programmable time interval. If enabled, chip selects are active for these reads. 4.1.8 Power-Save Control When in Enhanced Mode, the IA186XL supports a power save mode of operation. The internal clock frequency is divided by a programmable amount. This affects all internal logic including, timers, the refresh control unit and clkout generation. Timers and the refresh control unit need to be reprogrammed accordingly when going in and out of power save if you wish to maintain the same real time references. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 44 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 4.2 Data Sheet July 6, 2011 Operating Modes During reset the IA186XL can be configured to enable special operating modes described as follows. 4.2.1 Enhanced Mode If Enhanced Mode is enabled, the IA186XL has DRAM refresh, Power-Save and coprocessor support available in addition to the normal features available in Compatible Mode. Enhanced Mode will be invoked automatically if a coprocessor is attached. It can also be entered by tying the reset output to the test_n/busy input. An internal pull-up keeps the part from entering Enhanced mode during normal operation. When not in Enhanced Mode, none of the Enhanced Mode registers can be accessed. QueueStatus functions, except for the coprocessor support, will be available when not in Enhanced Mode. 4.2.2 Queue Status Mode When Queue Status Mode is enabled, information about the instruction queue is output on the ale/qs0 and wr_n/qs1 pins. To enter Queue Status Mode, the rd_n input should be tied low. It is sampled at reset, and if low, Queue Status Mode is entered. An internal pull-up keeps the part from entering Queue Status mode during normal operation. 4.2.3 ONCE Mode ONCE mode is a special test mode where all pins are set to a high impedance state. ONCE mode is entered by forcing lcs_n and ucs_n low during reset. These pins are sampled on the rising edge of res but should be held low for at least a full clock cycle after res goes high. ONCE mode is exited by reseting the part with lcs_n and ucs_n high. Internal pull-ups keep the part from entering ONCE mode during normal operation. 4.2.4 Math Coprocessor (IA186XL Only) When Enhanced mode is enabled, the IA186XL is configured to interface with a math coprocessor via three of the middle chip select pins. Pin mcs0/pereq is used for Processor Extension Request. Pin mcs1/error is used for coprocessor error indication. Pin mcs3/nps is used for Numeric Processor Select. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 45 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 12. Internal Register Map PCB Offset 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 36H 38H 3AH 3CH 3EH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EOI POLL POLLSTS IMASK PRIMSK INSERV REQST INSTS TCUCON DMA0CON DMA1CON I0CON I1CON I2CON I3CON PCB Offset 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved T0CNT T0CMPA T0CMPB T0CON T1CNT T1CMPA T1CMPB T1CON T2CNT T2CMPA Reserved T2CON Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCB Offset 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UMCS LMCS PACS MMCS MPCS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCB Offset C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH Function D0SRCL D0SRCH D0DSTL D0DSTH D0TC D0CON Reserved Reserved D1SRCL D1SRCH D1DSTL D1DSTH D1TC D1CON Reserved Reserved RFBASE RFTIME RFCON Reserved Reserved Reserved Reserved Reserved PWRSAV PWRCON Reserved 1 Step ID Reserved Reserved Reserved RELREG Note: 1 The Step ID register (offset 0xF6) for Revision 1 of the Innovasic device is read-only, and is uniquely identified in software by having a value of 0x0081. The original Intel device established a value between 0x0000 and 0x0003, depending on the revision of the part. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 46 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 5. AC Specifications 5.1 Major Cycle Timings – Read Cycle TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 13. Major Cycle Timings – Read Cycle Values Min 8 3 3 3 3 0 3 10 Symbol Parameter TDVCL TCLDX TCHSV TCHSH TCLAV TCLAX TCLDV TCHDX TCHLH TLHLL TCHLL TAVLL Data in Setup (A/D) Data in Hold (A/D) Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Address Valid to ALE Low TLLAX Address Hold from ALE Inactive TAVCH TCLAZ TCLCSV Address Valid to Clock High Address Float Delay Chip-Select Active Delay TCXCSX TCHCSX TDXDL TCVCTV TCVDEX TCHCTV TCLLV TAZRL TCLRL TRLRH TCLRH TRHLH Chip-Select Hold from Command Inactive Chip-Select Inactive Delay DEN Inactive to DT/R Low Control Active Delay 1 DEN Inactive Delay Control Active Delay 2 LOCK Valid/Invalid Delay Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High ® Max Test Conditions TCLCH - 10 ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading TCHCL - 8 ns Equal Loading 0 ns ns ns 20 20 20 20 20 TCLCL - 15 20 TCLAX 3 TCLCH - 10 3 0 3 3 3 3 0 3 2TCLCL - 15 3 TCLCH - 14 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 47 of 75 Unit 20 20 17 17 17 20 17 20 20 ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading Equal Loading Equal Loading http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers TRHAV Data Sheet July 6, 2011 RD Inactive to Address Active TCLCL - 15 ns Equal Loading TCHSH (1) (2) (3) (4) (6) (5) Figure 12. Read Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. Notes: (1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. (2) Status is inactive in the state preceding T4. (3) Only TCLCSV is applicable if latched A1 and A2 are selected instead of PCS5 and PCS6. (4) This applies when a write cycle is followed by read cycle. (5) This is T1 of next bus cycle. (6) This changes in the T-state preceding the next bus cycle if followed by a write. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 48 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.2 Data Sheet July 6, 2011 Major Cycle Timings – Write Cycle TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 14. Major Cycle Timings – Write Cycle Values Min 3 3 3 0 3 10 Parameter TCHSV TCHSH TCLAV TCLAX TCLDV TCHDX TCHLH TLHLL TCHLL Status Active Delay Status Inactive Delay Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay TAVLL Address Valid to ALE Low TCLCH - 10 ns Equal Loading TLLAX Address Hold from ALE Inactive TCHCL - 10 ns Equal Loading TAVCH TCLDOX TCVCTV TCVCTX TCLCSV Address Valid to Clock High Data Hold Time Control Active Delay 1 Control Inactive Delay Chip-Select Active Delay 0 3 3 3 3 ns ns ns ns ns TCXCSX Chip-Select Hold from Command Inactive TCHCSX Chip-Select Inactive Delay 3 TDXDL DEN Inactive to DT/R Low 0 TCLLV TWLWH LOCK Valid/Invalid Delay WR Pulse Width 3 2TCLCL - 15 TWHLH WR Inactive to ALE High TCLCH - 14 ns Equal Loading TWHDX Data Hold after WR TCLCL - 10 ns Equal Loading TWHDEX WR Inactive to DEN Inactive TCLCH - 10 ns Equal Loading ® Max 20 20 20 20 20 TCLCL - 15 20 20 17 20 TCLCH - 10 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 49 of 75 Unit Test Conditions Symbol ns ns ns ns ns ns ns ns ns ns 17 ns 17 Equal Loading ns Equal Loading ns ns http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 TCHSH (1) (2) (3) (4) (6) (5) Figure 13. Write Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. Notes: (1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. (2) Status is inactive in the state preceding T4. (3) Only TCLCSV is applicable if latched A1 and A2 are selected instead of PCS5 and PCS6. (4) This applies when a write cycle is followed by a read cycle. (5) This is T1 of next bus cycle. (6) This changes in the T-state preceding the next bus cycle if followed by a read, INTA or halt. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 50 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.3 Data Sheet July 6, 2011 Major Cycle Timings – Interrupt Acknowledge Cycle TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 15. Major Cycle Timings – Interrupt Acknowledge Cycle Values Min 8 3 3 3 3 0 0 3 10 Symbol Parameter TDVCL TCLDX TCHSV TCHSH TCLAV TAVCH TCLAX TCLDV TCHDX TCHLH TLHLL TCHLL Data in Setup (A/D) Data in Hold (A/D) Status Active Delay Status Inactive Delay Address Valid Delay Address Valid to Clock High Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay TAVLL Address Valid to ALE Low TCLCH - 10 ns TLLAX Address Hold to ALE Inactive TCHCL - 10 ns TCLAZ TCVCTV TCVCTX Address Float Delay Control Active Delay 1 Control Inactive Delay TDXDL DEN Inactive to DT/R Low 0 TCHCTV Control Active Delay 2 3 20 ns TCVDEX DEN Inactive Delay (Non-Write Cycles) 3 17 ns TCLLV LOCK Valid/Invalid Delay 3 17 ns ® Max 20 20 20 20 20 TCLCL - 15 20 TCLAX 3 3 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 51 of 75 20 17 17 Unit Test Conditions ns ns ns ns ns ns ns ns ns ns ns ns Equal Loading Equal Loading ns ns ns ns Equal Loading http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 TCHSH (1) (2) (3) (4) (5) (7) (6) Figure 14. Interrupt Acknowledge Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. Notes: (1) (2) (3) (4) (5) (6) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. Status is inactive in the state preceding T4. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to TCLDX (min). INTA occurs one clock later in Slave Mode. This applies when a write cycle is followed by an interrupt acknowledge cycle. LOCK is active upon T1 of the first interrupt acknowledge cycle, and inactive upon T2 of the second interrupt acknowledge cycle. (7) Changes in T-state preceding next bus cycle if followed by write. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 52 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.4 Data Sheet July 6, 2011 Software Halt Cycle Timings TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 16. Software Halt Cycle Timings Symbol Values Parameter Unit Min Max TCHSV Status Active Delay 3 20 ns TCHSH Status Inactive Delay 3 20 ns TCLAV Address Valid Delay 3 20 ns TCHLH ALE Active Delay 20 ns TLHLL ALE Width TCHLL ALE Inactive Delay 20 ns TDXDL DEN Inactive to DT/R Low 0 ns TCHCTV Control Active Delay 2 20 ns ® TCLCL - 15 3 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 53 of 75 Test Conditions ns Equal Loading http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 TCHSH (1) (2) Figure 15. Software Halt Cycle Waveforms Please note that pins indicated in the parentheses are for the IA188XL version. Notes: (1) The OEM part (80C186XL) operates differently in that it deasserts on the falling edge of CLKOUT. (2) This applies when a write cycle is followed by a halt cycle. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 54 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.5 Data Sheet July 6, 2011 Clock Timings TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 17. Clock Timings Symbol Parameter TCKIN Values Min Max CLKIN Period 20 ∞ TCLCK CLKIN Low Time 8 TCHCK CLKIN High Time 8 TCKHL CLKIN Fall Time TCKLH ∞ Unit Test Conditions ns ns 1.5V(2) ns 1.5V(2) 5 ns 3.5 to 1.0V CLKIN Rise Time 5 ns 1.0 to 3.5V TCICO CLKIN to CLKOUT Skew 17 ns TCLCL CLKOUT Period ∞ ns TCLCH CLKOUT Low Time 0.5 TCLCL - 5 ns CL = 100 pF(3) TCHCL CLKOUT High Time 0.5 TCLCL - 5 ns CL = 100 pF(4) TCH1CH2 CLKOUT Rise Time 6 ns 1.0 to 3.5V TCL2CL1 CLKOUT Fall Time 6 ns 3.5 to 1.0V 40 ∞ NOTES: 1. External clock applied to X1 and X2 not connected. 2. TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 40% of T CKIN. 3. Tested under worst case conditions: VCC = 5.5V. TA = 70￮C. 4. Tested under worst case conditions: VCC = 4.5V. TA = 0￮C. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 55 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.6 Data Sheet July 6, 2011 Ready, Peripheral and Queue Status Timings TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 18. Ready, Peripheral and Queue Status Timings Symbol TSRYCL TCLSRY TARYCH TCLARX TARYCHL TARYLCL TINVCH TINVCL TCLTMV TCHQSV Values Parameter Min Synchronous Ready (SRDY) Transition Setup Time(1) SRDY Transition Hold Time(1) ARDY Resolution Transition Setup Time(2) ARDY Active Hold Time(1) ARDY Inactive Holding Time Asynchronous Ready (ARDY) Setup Time(1) INTx, NMI, TEST, BUSY, TMR IN Setup Time(2) DRQ0, DRQ1 Setup Time(2) Timer Output Delay Queue Status Delay Max Unit 8 ns 8 ns 8 ns 8 8 ns ns 10 ns 8 ns 8 ns ns ns 17 22 Test Conditions NOTES: 1. To guarantee proper operation. 2. To guarantee recognition at clock edge. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 56 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 5.7 Data Sheet July 6, 2011 Reset and HOLD/HLDA Timings TA = -40￮C to +85￮C, VCC = 5V + 10% All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. All output test conditions are with CL = 50 pF. For AC tests, input VIL = 0.45V and VIH = 2.4V except at X1 where VIH = VCC – 0.5V. Table 19. Reset and HOLD/HLDA Timings Symbol TRESIN THVCL TCLAZ TCLAV TCLRO TCLHAV TCHCZ TCHCV Values Parameter RES Setup HOLD Setup(1) Address Float Delay Address Valid Delay Reset Delay HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) Min 15 8 TCLAX 3 3 Max Unit 20 20 17 17 22 ns ns ns ns ns ns ns 20 ns Test Conditions NOTE: 1. To guarantee recognition at next clock. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 57 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Figure 16. Clock Waveforms Figure 17. Reset Waveforms Figure 18. Synchronous Ready (SRDY) Waveforms ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 58 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Figure 19. Asynchronous Ready (ARDY) Waveforms Figure 20. Peripheral and Queue Status Waveforms ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 59 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Figure 21. HOLDA/HLDA Waveforms (Entering Hold) Figure 22. HOLD/HLDA Waveforms (Leaving Hold) ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 60 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 6. Data Sheet July 6, 2011 Instruction Execution Times Table 20 provides IA186XL and IA188XL execution times, mnemonic instruction, and additional information on execution, if required. Table 20. Instruction Set Timing Instruction AAA AAD AAM AAS ADC Immediate to accumulator ADC Immediate to register/memory ADC Register/memory with register to either ADD Immediate to accumulator ADD Immediate to register/memory ADD Register/memory with register either AND Immediate to accumulator AND Immediate to register/memory AND Register/memory and register to either BOUND CBW CLC CLD CLI CMC CMPS CS CWD DAA DAS DEC Register DEC Register/memory ® Clock Cycles IA186XL IA188XL 3 3 6 6 40 40 3 3 1 1 3 13 Comments – – – – – – 1/16 1/24 register/memory 1 1/19 1 1/32 register/memory 1/20 1/28 1 1/24 1 1/33 1/12 1/15 20/40 1 1 1 1 2 9 1 1 4 2 1 1/24 24/64 4 1 1 1 2 20 1 1 4 2 1 1/32 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 61 of 75 – – register/memory Interrupt not taken/Interrupt taken – – – – – – – – – – – register/memory http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 20. Instruction Set Timing (Continued) Instruction DIV Memory-Byte DIV Memory-Word DIV Register-Byte DIV Register-Word IDIV Memory-Byte IDIV Memory-Word IDIV Register-Byte IDIV Register-Word IMUL Immediate (signed) IMUL Memory-Byte IMUL Memory-Word IMUL Register-Byte IMUL Register-Word INC Register INS INS (repeated n times) INT Type specified INT Type 3 INTO IRET JA JAE JB JBE JCXZ JE JG JGE JL JLE JMP Direct intersegment JMP Direct within segment JMP Short/long JNA JNAE JNB JNBE JNE JNG JNGE JNL JNLE JNO JNP ® Clock Cycles IA186XL IA188XL 46 46 49 51 39 39 39 39 46 46 49 51 39 39 39 39 5/24 5/33 4 20 13 28 5 5 5 5 1 1 8 16 8+8n 16+16n 33 41 33 41 33 48 30 30 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/4 3/4 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3 3 3 3 4 4 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 62 of 75 Comments – – – – – – – – register/memory – – – – – – – – – – – Jump not taken/Jump taken Jump not taken/Jump taken Jump not taken/Jump taken – – – Jump not taken/Jump taken http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 20. Instruction Set Timing (Continued) Instruction JNS JNZ JO JP JPE JPO JS JZ LAHF LDS LEA LEAVE LES LOCK LODS LODS (repeated n times) LOOP LOOPE LOOPNE LOOPNZ LOOPZ MOV Accumulator to memory MOV Immediate to register MOV Immediate to register/memory MOV Memory to accumulator MOV Register to Register/Memory MOV Register/memory to register MOV Register/memory to segment register MOV Segment register to register/memory MOVS MOVS (repeated n times) MUL Memory-Byte MUL Memory-Word MUL Register-Byte MUL Register-Word NEG NOP NOT OR Immediate to accumulator ® Clock Cycles IA186XL IA188XL 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 2 2 1/24 1/33 3 3 12 12 12 32 1 1 8 12 8+8n 12+12n 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5 8/12 1 1 1/5 1/12 5 2/5 8/12 2/20 2/5 2/20 2/5 2/20 2/5 2/20 24 24+24n 16 15 5 5 1/32 1 1/24 1 32 32+32n 20 25 5 5 1/15 1 1/24 1 IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 63 of 75 Comments Jump not taken/Jump taken – register/memory – – – – – – Loop not taken/Loop taken Loop not taken/Loop taken 8-bit/16-bit register/memory 8-bit/16-bit register/memory – – – – – – register/memory – register/memory – http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 20. Instruction Set Timing (Continued) Instruction OR Immediate to register/memory OR Register/memory and register to either OUT Fixed port OUT Variable port OUTS OUTS (repeated n times) POP Memory POP Register POP Segment register POPA POPF PUSH Immediate PUSH Memory PUSH Register PUSH Segment register PUSHA PUSHF RET Inter-segment RET Inter-segment adding immediate to SP RET Within segment RET Within segment adding immediate to SP ROL Register/Memory by 1 ROL Register/Memory by CL ROL Register/Memory by Count ROR Register/Memory by 1 ROR Register/Memory by CL ROR Register/Memory by Count SAHF SBB Immediate from accumulator SBB Immediate from register/memory SBB Register/memory and register to either SCAS SCAS (repeated n times) SHL Register/Memory by 1 ® Clock Cycles IA186XL IA188XL 1/32 1/32 Comments register/memory 1/32 1/24 5 5 8 8+8n 10 10 16 80 13 8 15 4 4 64 4 14 25 8/12 12 12/20 12/20+12/20n 20 12 12 93 13 12 28 12 12 72 16 21 21 8-bit/16-bit – 8-bit/16-bit 8-bit/16-bit – – – – – – – – – – – – – 14 16 13 13 – – 1/8 1/8 1/8 1/16 1/16 1/24 register/memory 1/8 1/8 1/8 1/16 1/16 1/24 2 1 2 1 – – 1/15 1/28 register/memory 1/11 1/40 register/memory 11 11+8n 5 8/12 8/12+8/12n 1/32 8-bit/16-bit 8-bit/16-bit register/memory IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 64 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 20. Instruction Set Timing (Continued) Instruction SHL Register/Memory by CL SHL Register/Memory by Count SHR Register/Memory by 1 SHR Register/Memory by CL SHR Register/Memory by Count SS STC SUB Immediate from accumulator SUB Immediate from register/memory SUB Register/memory and register to either STD STI STOS STOS (repeated n times) TEST Immediate data and accumulator TEST Immediate data and register/memory TEST Register/memory and register WAIT XCHG Register with accumulator XCHG Register/memory with register XLAT XOR Immediate to accumulator XOR Immediate to register/memory XOR Register/memory and register to either ® Clock Cycles IA186XL IA188XL 1/20 1/24 1/11 1/24 Comments register/memory 1/5 1/20 1/11 1/24 1/28 1/24 1 1 1 1 1 1 – – - 1/11 1/28 register/memory 1/15 1/40 1 1 6 6+4n 1 1 1 8 8+8n 1 – – – – – 1/16 1/16 register/memory 1/12 1/20 register/memory 1 2 1 2 test_n = 0 – 3/16 3/20 register/memory 16 1 1/11 8 1 1/32 – register/memory 1/16 1/32 register/memory IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 65 of 75 – http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 7. Data Sheet July 6, 2011 Innovasic Part Number Cross-Reference Tables 21 through 23 cross-reference the Innovasic part number with the corresponding Intel part number. Table 21. Innovasic Part Number Cross-Reference for the PLCC Innovasic Part Number IA186XLPLC68IR1 (lead free–RoHS) IA188XLPLC68IR1 (lead free–RoHS) ® Intel Part Number N80C186XL25 N80C186XL20 N80C186XL12 TN80C186XL25 TN80C186XL20 TN80C186XL12 EE80C186XL25 EE80C186XL20 EE80C186XL12 EN80C186XL20 EN80C186XL12 N80C188XL25 N80C188XL20 N80C188XL12 TN80C188XL25 TN80C188XL20 TN80C188XL12 EE80C188XL25 EE80C188XL20 EE80C188XL12 EN80C188XL20 EN80C188XL12 Package Type Temperature Range 68-Lead PLCC Industrial 68-Lead PLCC Industrial IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 66 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 22. Innovasic Part Number Cross-Reference for the PQFP (Special Order only) Innovasic Part Number IA186XLPQF80IR1 (lead free–RoHS) IA188XLPQF80IR1 (lead free–RoHS) ® Intel Part Number S80C186XL25 S80C186XL20 S80C186XL12 TS80C186XL25 TS80C186XL20 TS80C186XL12 EG80C186XL25 EG80C186XL20 ES80C186XL20 S80C188XL25 S80C188XL20 S80C188XL12 TS80C188XL25 TS80C188XL20 TS80C188XL12 EG80C188XL25 EG80C188XL20 ES80C188XL20 Package Type Temperature Range 80-Lead PQFP Industrial 80-Lead PQFP Industrial IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 67 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Table 23. Innovasic Part Number Cross-Reference for the LQFP (Special Order only) Innovasic Part Number IA186XLPLQ80IR1 (lead free–RoHS) IA188XLPLQ80IR1 (lead free–RoHS) ® Intel Part Number SB80C186XL25 SB80C186XL20 SB80C186XL12 YW80C186XL25 YW80C186XL20 SB80C188XL25 SB80C188XL20 SB80C188XL12 YW80C188XL25 YW80C188XL20 Package Type Temperature Range 80-Lead LQFP Industrial 80-Lead LQFP Industrial IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 68 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 8. Data Sheet July 6, 2011 Errata The following errata are associated with the IA186XL/IA188XL. A workaround to the identified problem has been provided where possible. 8.1 Summary Table 24 presents a summary of errata. Table 24. Summary of Errata Errata No. Problem Ver. 0 Ver. 1 Ver. 2 Exists Exists Exists 1 Pin LOCK_n does not have an internal pullup and will float during reset and bus hold. 2 When the timer compare register for any of the timers is set to x0000, the max count is xFFFF instead of x10000 as in the OEM part. Exists Fixed Fixed 3 When using external interrupts IRQ0 or IRQ1 in Cascade Mode, the acknowledge signal on INTA0 or INTA1 may be lost or truncated. Exists Fixed Fixed 4 Memory->Memory moves interrupted by two DMA cycles can corrupt data. Exists Fixed Fixed 5 Bit 15 of RELREG (offset 0xFE) behaves differently than Intel device. Exists Fixed Fixed 6 Enhanced mode makes bit 15 of RELREG (offset 0xFE) read-only. Exists Fixed Fixed 7 Sbus deasserts on the wrong edge of CLKOUT. Exists Fixed Fixed Exists Exists Fixed Exists Exists Fixed Exists Exists Fixed 8 9 10 Timer2 count register must be written to enable counting. Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt. DMA can hang. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 69 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Errata No. Problem MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. 11 12 8.2 Data Sheet July 6, 2011 Ver. 0 Ver. 1 Ver. 2 Exists Exists Fixed Exists Exists Fixed Detail Errata No. 1 Problem: Pin LOCK_n does not have an internal pullup. Description: Because Pin LOCK_n does not have an internal pullup, it will float during reset and bus hold. Workaround: An external pullup may be necessary if there is high external load on the signal. Errata No. 2 Problem: When the timer compare register for any of the timers is set to x0000, the max count is xFFFF instead of x10000 as in the OEM part. Description: The timer output will change one count earlier than it should when the max count is set to x0000. Workaround: The workaround is application dependent. Please contact Innovasic Technical Support if this erratum is an issue. Errata No. 3 Problem: When using external interrupts IRQ0 or IRQ1 in Cascade Mode, the acknowledge signal on INTA0 or INTA1 may be lost or truncated. Description: The acknowledge for IRQ0 or IRQ1 will be lost or truncated in Cascade Mode if another interrupt, with a higher priority setting (as configured in the interrupt control registers), occurs just before or during the acknowledge. This does not apply to interrupts generated by the DMA. This also does not apply when using the inherent priority settings (all interrupts configured with the same priority). ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 70 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Workaround: When using external interrupts in cascade mode, do not program other interrupts to have a high priority (except DMAs). When using both IRQ0 and IRQ1 in Cascade Mode they must be programmed to have the same priority level. Errata No. 4 Problem: Memory->Memory moves interrupted by two DMA cycles can corrupt data. Description: This problem occurs if Memory->Memory operation is interrupted by 2 DMA cycles with the following sequence: 1. The instruction reads data from memory. 2. The first DMA cycle occurs. 3. The second DMA request occurs between 1 and 4 clocks after the falling edge of ALE for the deposit phase of the first DMA. 4. An instruction fetch occurs (this will be the data that shows up later). 5. The second DMA cycle occurs. 6. The write phase of the instruction happens with bad data (from step 4). If the second DMA request occurs earlier than 1 clock after ALE for the first DMA's deposit phase, step 4 will be preempted by the second DMA, and operation is correct. If the second DMA request occurs later than 4 clocks after ALE for the first DMA's deposit phase, the write phase will follow step 4 immediately, and operation is correct. Of the total 163 instructions, the following 8 are impacted by this issue, with both the 8 & 16 bit versions of the first 7 on the list being affected. 1. 2. 3. 4. 5. 6. 7. 8. MOVS PUSH mem POP mem INS IN OUTS OUT ENTER Workaround: If the conditions described above occur, there is no workaround. However, this DMA issue will be corrected in Revision 1 of the device. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 71 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Errata No. 5 Problem: Bit 15 of RELREG (offset 0xFE) behaves differently than Intel device. Description: For both 188 and 186 devices, an ESC opcode will generate a type 7 interrupt only when RELREG[15] is a 0. Workaround: Initialize RELREG[15] to 0 if a type 7 interrupt is desired. Errata No. 6 Problem: Enhanced mode makes bit 15 of RELREG (offset 0xFE) read-only. Description: If the device comes out of reset in enhanced mode, RELREG[15] will be set to a 1. Workaround: Avoid enhanced mode if a type 7 interrupt is desired. Errata No. 7 Problem: Sbus deasserts on the wrong edge of CLKOUT. Description: The sbus goes inactive (high) at the end of a bus cycle on the falling edge of CLKOUT. It should be on the rising edge of CLKOUT. Workaround: None. Errata No. 8 Problem: Timer2 count register must be written to enable counting. Description: If timer 2 count register is not explicitly written timer 2 will not count; this can also prevent timers 0 & 1 from counting if timer 2 is used as a prescaler. Workaround: Write timer 2 count register before enabling timer 2. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 72 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers Data Sheet July 6, 2011 Errata No. 9 Problem: Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt. Description: When instruction execution unit is in Decode state for 2 or more consecutive cycles and an NMI is recognized, it could be pre-empted by a maskable interrupt. Workaround: None. Errata No. 10 Problem: DMA can hang. Description: DMA to a region of memory using destination synchronization and a chip select with extra wait states can hang. Workaround: Do not use wait states and destination synchronization together. Errata No. 11 Problem: MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. Description: MOVS/POP/PUSH instructions interrupted by both a DMA transaction and an instruction fetch bus cycle can corrupt data. This affects the IA186XL only. Workaround: None. Errata No. 12 Problem: MOVS/POP/PUSH instructions interrupted by DMA can corrupt data. Description: MOVS/PUSH/POP instructions with 16-bit, non-aligned destination address interrupted by DMA can corrupt data. This affects the IA186XL only. Workaround: None. ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 73 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 9. Data Sheet July 6, 2011 Data Sheet Revision History Table 25 presents the sequence of revisions to document IA211080711. Table 25. Data Sheet Revision History Date Revision September 30, 2008 00 Initial release NA August 5, 2009 01 Updated DC Parameters; Updated AC Specifications and timing diagrams; Updated Instruction Set Timing; Added errata. Multiple pages throughout the document 02 Final version of the data sheet released to support production of Version 0 of the IA186/188 XL. Release date changed, “Preliminary” removed from heading and document number revised to reflect final release. No other changes. Headers and Footers on all pages 03 Updated the package dimensions table for the 68 PLCC; Added a note to Table 12 regarding the Step ID register; Updated Errata 4 to include more recent information. 14, 46, 69, 71 January 15, 2010 04 Updated AC and DC table notes to show TA at industrial temperature instead of commercial; Updated Errata information for Version 1of the device; Updated note regarding StepID register. 46, 47, 49, 51, 53, 55, 56, 57, 69 January 12, 2011 05 Updated to add Errata 8. 69, 72 January 13, 2011 06 Updated to add Errata 9 – 12. 69 - 73 March 23, 2011 07 Updated Instruction Set Timing Table to incorporate DIV and IDIV values. 62 June 30, 2011 08 Updated Errata table to note fixes in Ver. 2. 69, 70 July 6, 2011 09 Updated pin descriptions for inputs/outputs. 25, 28, 31, 32, 34 August 19, 2009 September 4, 2009 ® Description IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 74 of 75 Page(s) http://www.Innovasic.com Customer Support: 1-888-824-4184 IA186XL/IA188XL 16-Bit Microcontrollers 10. Data Sheet July 6, 2011 For Additional Information The Innovasic Semiconductor IA186XL and IA188XL microcontrollers are form, fit, and function replacements for the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team 3737 Princeton NE Suite 130 Albuquerque, NM 87107 (505) 883-5263 Fax: (505) 883-5477 Toll Free: (888) 824-4184 E-mail: [email protected] Website: http://www.Innovasic.com ® IA211080711-09 UNCONTROLLED WHEN PRINTED OR COPIED Page 75 of 75 http://www.Innovasic.com Customer Support: 1-888-824-4184